Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	331	1			T4	1		T6	8		T7	8
all_values[1]	331	1			T4	1		T6	8		T7	8
all_values[2]	331	1			T4	1		T6	8		T7	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

518

1

T4

3

T6

11

T7

11

auto[1]

475

1

T6

13

T7

13

T9

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

606

1

T4

3

T6

15

T7

9

auto[1]

387

1

T6

9

T7

15

T9

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	121	1			T4	1		T6	4		T7	2
all_values[0]	auto[0]	auto[1]	66	1			T6	2		T7	1		T9	2
all_values[0]	auto[1]	auto[0]	81	1			T6	1		T7	1		T8	2
all_values[0]	auto[1]	auto[1]	63	1			T6	1		T7	4		T8	4
all_values[1]	auto[0]	auto[0]	103	1			T4	1		T6	1		T7	2
all_values[1]	auto[0]	auto[1]	61	1			T6	1		T7	3		T9	1
all_values[1]	auto[1]	auto[0]	99	1			T6	4		T7	1		T8	3
all_values[1]	auto[1]	auto[1]	68	1			T6	2		T7	2		T9	1
all_values[2]	auto[0]	auto[0]	112	1			T4	1		T6	1		T12	1
all_values[2]	auto[0]	auto[1]	55	1			T6	2		T7	3		T9	1
all_values[2]	auto[1]	auto[0]	90	1			T6	4		T7	3		T9	2
all_values[2]	auto[1]	auto[1]	74	1			T6	1		T7	2		T9	1