Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
48.45	48.31	64.41	16.56	0.00	48.00	100.00	61.84

Total tests in report: 215

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
43.76	43.76	47.87	47.87	58.70	58.70	16.64	16.64	0.00	0.00	47.41	47.41	91.88	91.88	43.83	43.83	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2852738143
45.33	1.57	48.28	0.41	60.77	2.06	16.77	0.13	0.00	0.00	47.63	0.22	94.50	2.62	49.36	5.53	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.272407945
46.40	1.07	48.31	0.03	61.24	0.48	16.86	0.09	0.00	0.00	47.78	0.15	95.03	0.52	55.60	6.24	/workspace/coverage/cover_reg_top/19.kmac_intr_test.468642161
47.30	0.89	48.31	0.00	63.38	2.13	16.99	0.13	0.00	0.00	48.00	0.22	95.81	0.79	58.58	2.98	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.4254766957
47.70	0.41	48.31	0.00	63.38	0.00	17.29	0.30	0.00	0.00	48.00	0.00	97.64	1.83	59.29	0.71	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.4188806302
47.96	0.26	48.31	0.00	63.38	0.00	17.29	0.00	0.00	0.00	48.00	0.00	99.48	1.83	59.29	0.00	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.865910416
48.12	0.15	48.31	0.00	63.75	0.37	17.29	0.00	0.00	0.00	48.00	0.00	99.48	0.00	60.00	0.71	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1079150974
48.21	0.09	48.31	0.00	63.82	0.07	17.29	0.00	0.00	0.00	48.00	0.00	99.48	0.00	60.57	0.57	/workspace/coverage/cover_reg_top/12.kmac_intr_test.4055263657
48.29	0.08	48.31	0.00	63.82	0.00	17.29	0.00	0.00	0.00	48.00	0.00	99.48	0.00	61.13	0.57	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.409532736
48.37	0.08	48.31	0.00	64.37	0.55	17.29	0.00	0.00	0.00	48.00	0.00	99.48	0.00	61.13	0.00	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1268899398
48.43	0.06	48.31	0.00	64.37	0.00	17.29	0.00	0.00	0.00	48.00	0.00	99.48	0.00	61.56	0.43	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1611446763
48.47	0.04	48.31	0.00	64.37	0.00	17.29	0.00	0.00	0.00	48.00	0.00	99.74	0.26	61.56	0.00	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1601196281
48.51	0.04	48.31	0.00	64.37	0.00	17.29	0.00	0.00	0.00	48.00	0.00	100.00	0.26	61.56	0.00	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3040256451
48.53	0.02	48.31	0.00	64.37	0.00	17.29	0.00	0.00	0.00	48.00	0.00	100.00	0.00	61.70	0.14	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3190949317
48.55	0.02	48.31	0.00	64.37	0.00	17.29	0.00	0.00	0.00	48.00	0.00	100.00	0.00	61.84	0.14	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.142863560
48.55	0.01	48.31	0.00	64.41	0.04	17.29	0.00	0.00	0.00	48.00	0.00	100.00	0.00	61.84	0.00	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.4213430193

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1192947444
/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.229217101
/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3086292975
/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4185249248
/workspace/coverage/cover_reg_top/0.kmac_csr_rw.333016981
/workspace/coverage/cover_reg_top/0.kmac_intr_test.2258033989
/workspace/coverage/cover_reg_top/0.kmac_mem_walk.1051772498
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1866983905
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3160522743
/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3273041577
/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1160818072
/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2706530109
/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.198153951
/workspace/coverage/cover_reg_top/1.kmac_csr_rw.2059760260
/workspace/coverage/cover_reg_top/1.kmac_intr_test.1083900014
/workspace/coverage/cover_reg_top/1.kmac_mem_walk.837912825
/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3343468047
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3344714839
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1901797204
/workspace/coverage/cover_reg_top/1.kmac_tl_errors.428725419
/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.482245120
/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2224513143
/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3917241677
/workspace/coverage/cover_reg_top/10.kmac_intr_test.3782898427
/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.910195540
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2778920704
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1908729578
/workspace/coverage/cover_reg_top/10.kmac_tl_errors.3282895128
/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.510871035
/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1425283847
/workspace/coverage/cover_reg_top/11.kmac_csr_rw.778756042
/workspace/coverage/cover_reg_top/11.kmac_intr_test.2553289444
/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2552169138
/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3063408241
/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2165574485
/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.1315315358
/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3012217029
/workspace/coverage/cover_reg_top/12.kmac_csr_rw.2308518134
/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1657653522
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1088448346
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2878619875
/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2729619012
/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1576991160
/workspace/coverage/cover_reg_top/13.kmac_csr_rw.4113050847
/workspace/coverage/cover_reg_top/13.kmac_intr_test.2452363418
/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2705431558
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3769781060
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2024341461
/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.89065527
/workspace/coverage/cover_reg_top/14.kmac_csr_rw.2818380614
/workspace/coverage/cover_reg_top/14.kmac_intr_test.3868529022
/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1041752656
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2575100654
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3973535502
/workspace/coverage/cover_reg_top/14.kmac_tl_errors.326809412
/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3214478138
/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1950637781
/workspace/coverage/cover_reg_top/15.kmac_csr_rw.956420816
/workspace/coverage/cover_reg_top/15.kmac_intr_test.571435696
/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.675802895
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2767540460
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1168410040
/workspace/coverage/cover_reg_top/15.kmac_tl_errors.4125672379
/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1613540554
/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2111276941
/workspace/coverage/cover_reg_top/16.kmac_csr_rw.2206887858
/workspace/coverage/cover_reg_top/16.kmac_intr_test.3631392768
/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2421678864
/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1839930405
/workspace/coverage/cover_reg_top/16.kmac_tl_errors.3455836736
/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.237432557
/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4032991147
/workspace/coverage/cover_reg_top/17.kmac_csr_rw.2238959666
/workspace/coverage/cover_reg_top/17.kmac_intr_test.1172912240
/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3089597742
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2879274537
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2487134671
/workspace/coverage/cover_reg_top/17.kmac_tl_errors.2694853224
/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.353706160
/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2710264402
/workspace/coverage/cover_reg_top/18.kmac_csr_rw.484215605
/workspace/coverage/cover_reg_top/18.kmac_intr_test.3591662666
/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2788577546
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1234792230
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1768458274
/workspace/coverage/cover_reg_top/18.kmac_tl_errors.954136036
/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3578819308
/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3158378339
/workspace/coverage/cover_reg_top/19.kmac_csr_rw.4032102139
/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2426948219
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1517916949
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1644603952
/workspace/coverage/cover_reg_top/19.kmac_tl_errors.4246702496
/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.805362100
/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.4217309735
/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1005546258
/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.684098406
/workspace/coverage/cover_reg_top/2.kmac_csr_rw.1979922663
/workspace/coverage/cover_reg_top/2.kmac_intr_test.611357791
/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3940776448
/workspace/coverage/cover_reg_top/2.kmac_mem_walk.340205847
/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.971411389
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2268312608
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.4086289117
/workspace/coverage/cover_reg_top/2.kmac_tl_errors.4110781560
/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.894350639
/workspace/coverage/cover_reg_top/20.kmac_intr_test.92754333
/workspace/coverage/cover_reg_top/21.kmac_intr_test.3127739748
/workspace/coverage/cover_reg_top/22.kmac_intr_test.2317354502
/workspace/coverage/cover_reg_top/23.kmac_intr_test.250574395
/workspace/coverage/cover_reg_top/24.kmac_intr_test.1341753112
/workspace/coverage/cover_reg_top/25.kmac_intr_test.2982757762
/workspace/coverage/cover_reg_top/26.kmac_intr_test.3333104735
/workspace/coverage/cover_reg_top/27.kmac_intr_test.99952041
/workspace/coverage/cover_reg_top/28.kmac_intr_test.1391595437
/workspace/coverage/cover_reg_top/29.kmac_intr_test.2710699037
/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3843767744
/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2317688857
/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2545991719
/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2770409990
/workspace/coverage/cover_reg_top/3.kmac_csr_rw.1426924980
/workspace/coverage/cover_reg_top/3.kmac_intr_test.2918454360
/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2161365756
/workspace/coverage/cover_reg_top/3.kmac_mem_walk.1409935844
/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.661079909
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.161896824
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.883383553
/workspace/coverage/cover_reg_top/3.kmac_tl_errors.22785146
/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2613619821
/workspace/coverage/cover_reg_top/30.kmac_intr_test.2249274846
/workspace/coverage/cover_reg_top/31.kmac_intr_test.3461924806
/workspace/coverage/cover_reg_top/32.kmac_intr_test.2538465811
/workspace/coverage/cover_reg_top/33.kmac_intr_test.3308479103
/workspace/coverage/cover_reg_top/34.kmac_intr_test.153889868
/workspace/coverage/cover_reg_top/35.kmac_intr_test.342202709
/workspace/coverage/cover_reg_top/36.kmac_intr_test.1993895111
/workspace/coverage/cover_reg_top/37.kmac_intr_test.783363108
/workspace/coverage/cover_reg_top/38.kmac_intr_test.2874326184
/workspace/coverage/cover_reg_top/39.kmac_intr_test.524736417
/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2727680424
/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.716451044
/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.4107834059
/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2990339272
/workspace/coverage/cover_reg_top/4.kmac_csr_rw.970126826
/workspace/coverage/cover_reg_top/4.kmac_intr_test.3547554940
/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2878176960
/workspace/coverage/cover_reg_top/4.kmac_mem_walk.2560872452
/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1009628807
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3972651552
/workspace/coverage/cover_reg_top/4.kmac_tl_errors.124337392
/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1328720138
/workspace/coverage/cover_reg_top/40.kmac_intr_test.3837163623
/workspace/coverage/cover_reg_top/41.kmac_intr_test.1590769940
/workspace/coverage/cover_reg_top/42.kmac_intr_test.3747269781
/workspace/coverage/cover_reg_top/43.kmac_intr_test.1718007829
/workspace/coverage/cover_reg_top/44.kmac_intr_test.2226210587
/workspace/coverage/cover_reg_top/45.kmac_intr_test.1818934320
/workspace/coverage/cover_reg_top/46.kmac_intr_test.2524221205
/workspace/coverage/cover_reg_top/47.kmac_intr_test.4049707131
/workspace/coverage/cover_reg_top/48.kmac_intr_test.506668363
/workspace/coverage/cover_reg_top/49.kmac_intr_test.232095241
/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3337010238
/workspace/coverage/cover_reg_top/5.kmac_csr_rw.4207944446
/workspace/coverage/cover_reg_top/5.kmac_intr_test.3016838238
/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3149294123
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3758234550
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1449734592
/workspace/coverage/cover_reg_top/5.kmac_tl_errors.338793852
/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2051860962
/workspace/coverage/cover_reg_top/6.kmac_csr_rw.3429991054
/workspace/coverage/cover_reg_top/6.kmac_intr_test.4289773143
/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2965130280
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1937216867
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3958380491
/workspace/coverage/cover_reg_top/6.kmac_tl_errors.2638832012
/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.159144757
/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3968179230
/workspace/coverage/cover_reg_top/7.kmac_csr_rw.2242650090
/workspace/coverage/cover_reg_top/7.kmac_intr_test.4193934736
/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1407175158
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1934687777
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2683274622
/workspace/coverage/cover_reg_top/7.kmac_tl_errors.1724663934
/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.513751308
/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.994252139
/workspace/coverage/cover_reg_top/8.kmac_csr_rw.1673171222
/workspace/coverage/cover_reg_top/8.kmac_intr_test.1792619804
/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2375109116
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.542799733
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.977110832
/workspace/coverage/cover_reg_top/8.kmac_tl_errors.3186633051
/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2545820495
/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2945227057
/workspace/coverage/cover_reg_top/9.kmac_csr_rw.1119158352
/workspace/coverage/cover_reg_top/9.kmac_intr_test.24285191
/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3498748387
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.4103761770
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3069051434
/workspace/coverage/cover_reg_top/9.kmac_tl_errors.691125827

Total test records in report: 215

tests.html | tests1.html | tests2.html | tests3.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.510871035	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:37 PM PDT 24	82544438 ps
T2	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2852738143	Mar 14 01:11:15 PM PDT 24	Mar 14 01:11:17 PM PDT 24	55695432 ps
T3	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2683274622	Mar 14 01:10:28 PM PDT 24	Mar 14 01:10:32 PM PDT 24	188419547 ps
T4	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.326809412	Mar 14 01:10:46 PM PDT 24	Mar 14 01:10:48 PM PDT 24	27257409 ps
T5	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2224513143	Mar 14 01:10:37 PM PDT 24	Mar 14 01:10:39 PM PDT 24	25003313 ps
T6	/workspace/coverage/cover_reg_top/12.kmac_intr_test.4055263657	Mar 14 01:10:44 PM PDT 24	Mar 14 01:10:45 PM PDT 24	12555829 ps
T10	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.2308518134	Mar 14 01:10:45 PM PDT 24	Mar 14 01:10:46 PM PDT 24	86359559 ps
T7	/workspace/coverage/cover_reg_top/8.kmac_intr_test.1792619804	Mar 14 01:10:35 PM PDT 24	Mar 14 01:10:36 PM PDT 24	50671957 ps
T11	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3843767744	Mar 14 01:10:29 PM PDT 24	Mar 14 01:10:37 PM PDT 24	1085356194 ps
T9	/workspace/coverage/cover_reg_top/39.kmac_intr_test.524736417	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:14 PM PDT 24	18578703 ps
T12	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2165574485	Mar 14 01:10:37 PM PDT 24	Mar 14 01:10:39 PM PDT 24	440241495 ps
T21	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.4107834059	Mar 14 01:10:27 PM PDT 24	Mar 14 01:10:30 PM PDT 24	390744048 ps
T22	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2421678864	Mar 14 01:10:54 PM PDT 24	Mar 14 01:10:56 PM PDT 24	106868945 ps
T8	/workspace/coverage/cover_reg_top/19.kmac_intr_test.468642161	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:14 PM PDT 24	19329824 ps
T13	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.865910416	Mar 14 01:10:13 PM PDT 24	Mar 14 01:10:15 PM PDT 24	31481304 ps
T14	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.124337392	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:37 PM PDT 24	183811843 ps
T33	/workspace/coverage/cover_reg_top/44.kmac_intr_test.2226210587	Mar 14 01:11:11 PM PDT 24	Mar 14 01:11:11 PM PDT 24	21080150 ps
T34	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.837912825	Mar 14 01:10:13 PM PDT 24	Mar 14 01:10:14 PM PDT 24	36290481 ps
T35	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.970126826	Mar 14 01:10:27 PM PDT 24	Mar 14 01:10:30 PM PDT 24	28056324 ps
T15	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.272407945	Mar 14 01:10:14 PM PDT 24	Mar 14 01:10:17 PM PDT 24	410469062 ps
T16	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.89065527	Mar 14 01:10:46 PM PDT 24	Mar 14 01:10:49 PM PDT 24	114843984 ps
T27	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1449734592	Mar 14 01:10:31 PM PDT 24	Mar 14 01:10:36 PM PDT 24	102049298 ps
T25	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2613619821	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:38 PM PDT 24	96665478 ps
T24	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1328720138	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:37 PM PDT 24	123863622 ps
T23	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3190949317	Mar 14 01:10:12 PM PDT 24	Mar 14 01:10:16 PM PDT 24	148288531 ps
T53	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3917241677	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:36 PM PDT 24	36264868 ps
T54	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.1426924980	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:35 PM PDT 24	315128273 ps
T17	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.3282895128	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:37 PM PDT 24	320145108 ps
T28	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2375109116	Mar 14 01:10:35 PM PDT 24	Mar 14 01:10:38 PM PDT 24	622608684 ps
T49	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1657653522	Mar 14 01:10:45 PM PDT 24	Mar 14 01:10:47 PM PDT 24	155847554 ps
T86	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.2560872452	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:34 PM PDT 24	10521680 ps
T29	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3040256451	Mar 14 01:10:14 PM PDT 24	Mar 14 01:10:16 PM PDT 24	96901019 ps
T71	/workspace/coverage/cover_reg_top/7.kmac_intr_test.4193934736	Mar 14 01:10:28 PM PDT 24	Mar 14 01:10:30 PM PDT 24	103968858 ps
T18	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4032991147	Mar 14 01:10:53 PM PDT 24	Mar 14 01:10:54 PM PDT 24	91135909 ps
T87	/workspace/coverage/cover_reg_top/26.kmac_intr_test.3333104735	Mar 14 01:11:11 PM PDT 24	Mar 14 01:11:12 PM PDT 24	10693584 ps
T26	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.894350639	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:39 PM PDT 24	139075883 ps
T72	/workspace/coverage/cover_reg_top/10.kmac_intr_test.3782898427	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:36 PM PDT 24	18704552 ps
T88	/workspace/coverage/cover_reg_top/36.kmac_intr_test.1993895111	Mar 14 01:11:15 PM PDT 24	Mar 14 01:11:16 PM PDT 24	13030908 ps
T30	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2575100654	Mar 14 01:10:39 PM PDT 24	Mar 14 01:10:41 PM PDT 24	77104057 ps
T31	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.4217309735	Mar 14 01:10:31 PM PDT 24	Mar 14 01:10:42 PM PDT 24	295818000 ps
T55	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1079150974	Mar 14 01:10:48 PM PDT 24	Mar 14 01:10:49 PM PDT 24	34608764 ps
T19	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.338793852	Mar 14 01:10:27 PM PDT 24	Mar 14 01:10:31 PM PDT 24	50853628 ps
T89	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.3429991054	Mar 14 01:10:27 PM PDT 24	Mar 14 01:10:29 PM PDT 24	61207868 ps
T68	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.333016981	Mar 14 01:10:13 PM PDT 24	Mar 14 01:10:15 PM PDT 24	114882795 ps
T69	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.4188806302	Mar 14 01:10:42 PM PDT 24	Mar 14 01:10:47 PM PDT 24	423442172 ps
T50	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3149294123	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:34 PM PDT 24	48005579 ps
T20	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2945227057	Mar 14 01:10:35 PM PDT 24	Mar 14 01:10:37 PM PDT 24	31322925 ps
T70	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2778920704	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:36 PM PDT 24	48949745 ps
T83	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2545820495	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:37 PM PDT 24	99418087 ps
T57	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3758234550	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:36 PM PDT 24	62459383 ps
T73	/workspace/coverage/cover_reg_top/9.kmac_intr_test.24285191	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:35 PM PDT 24	101503875 ps
T90	/workspace/coverage/cover_reg_top/24.kmac_intr_test.1341753112	Mar 14 01:11:15 PM PDT 24	Mar 14 01:11:16 PM PDT 24	41061095 ps
T32	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2879274537	Mar 14 01:10:53 PM PDT 24	Mar 14 01:10:55 PM PDT 24	157002131 ps
T91	/workspace/coverage/cover_reg_top/18.kmac_intr_test.3591662666	Mar 14 01:11:14 PM PDT 24	Mar 14 01:11:15 PM PDT 24	44892048 ps
T62	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.4246702496	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:16 PM PDT 24	57417030 ps
T61	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.2638832012	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:36 PM PDT 24	299768670 ps
T51	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.2238959666	Mar 14 01:10:53 PM PDT 24	Mar 14 01:10:54 PM PDT 24	18660619 ps
T56	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.4254766957	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:38 PM PDT 24	178901102 ps
T74	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2538465811	Mar 14 01:11:14 PM PDT 24	Mar 14 01:11:15 PM PDT 24	11265525 ps
T92	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3273041577	Mar 14 01:10:28 PM PDT 24	Mar 14 01:10:39 PM PDT 24	600994673 ps
T93	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3337010238	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:36 PM PDT 24	158450817 ps
T94	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1425283847	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:36 PM PDT 24	45772839 ps
T95	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1160818072	Mar 14 01:10:35 PM PDT 24	Mar 14 01:10:46 PM PDT 24	754064864 ps
T58	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1517916949	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:14 PM PDT 24	90086878 ps
T96	/workspace/coverage/cover_reg_top/40.kmac_intr_test.3837163623	Mar 14 01:11:12 PM PDT 24	Mar 14 01:11:12 PM PDT 24	20905418 ps
T78	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.353706160	Mar 14 01:10:58 PM PDT 24	Mar 14 01:11:02 PM PDT 24	203247867 ps
T97	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2767540460	Mar 14 01:10:43 PM PDT 24	Mar 14 01:10:45 PM PDT 24	23600119 ps
T98	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.229217101	Mar 14 01:10:16 PM PDT 24	Mar 14 01:10:26 PM PDT 24	637767389 ps
T52	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1908729578	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:36 PM PDT 24	78694288 ps
T99	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.428725419	Mar 14 01:10:16 PM PDT 24	Mar 14 01:10:19 PM PDT 24	333655385 ps
T100	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1041752656	Mar 14 01:10:39 PM PDT 24	Mar 14 01:10:42 PM PDT 24	37086890 ps
T36	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1601196281	Mar 14 01:10:13 PM PDT 24	Mar 14 01:10:15 PM PDT 24	118995514 ps
T40	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2545991719	Mar 14 01:10:31 PM PDT 24	Mar 14 01:10:34 PM PDT 24	22289459 ps
T41	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1005546258	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:35 PM PDT 24	246926263 ps
T42	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.22785146	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:36 PM PDT 24	69275029 ps
T43	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2552169138	Mar 14 01:10:37 PM PDT 24	Mar 14 01:10:39 PM PDT 24	284977386 ps
T44	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.3186633051	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:36 PM PDT 24	186892489 ps
T45	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1937216867	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:36 PM PDT 24	131553101 ps
T46	/workspace/coverage/cover_reg_top/17.kmac_intr_test.1172912240	Mar 14 01:10:54 PM PDT 24	Mar 14 01:10:55 PM PDT 24	18055416 ps
T47	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1768458274	Mar 14 01:11:12 PM PDT 24	Mar 14 01:11:15 PM PDT 24	232258242 ps
T48	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3344714839	Mar 14 01:10:12 PM PDT 24	Mar 14 01:10:14 PM PDT 24	160527792 ps
T101	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.661079909	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:37 PM PDT 24	92990605 ps
T102	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1009628807	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:36 PM PDT 24	214143587 ps
T103	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3127739748	Mar 14 01:11:10 PM PDT 24	Mar 14 01:11:11 PM PDT 24	20166685 ps
T65	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2051860962	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:34 PM PDT 24	31736825 ps
T77	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.1315315358	Mar 14 01:10:36 PM PDT 24	Mar 14 01:10:41 PM PDT 24	164741098 ps
T82	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1613540554	Mar 14 01:10:51 PM PDT 24	Mar 14 01:10:56 PM PDT 24	1288061021 ps
T104	/workspace/coverage/cover_reg_top/37.kmac_intr_test.783363108	Mar 14 01:11:10 PM PDT 24	Mar 14 01:11:11 PM PDT 24	27598900 ps
T105	/workspace/coverage/cover_reg_top/22.kmac_intr_test.2317354502	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:14 PM PDT 24	31118690 ps
T106	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1168410040	Mar 14 01:10:41 PM PDT 24	Mar 14 01:10:43 PM PDT 24	287274437 ps
T107	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2770409990	Mar 14 01:10:35 PM PDT 24	Mar 14 01:10:37 PM PDT 24	237502825 ps
T108	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4185249248	Mar 14 01:10:16 PM PDT 24	Mar 14 01:10:19 PM PDT 24	127226299 ps
T109	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3086292975	Mar 14 01:10:15 PM PDT 24	Mar 14 01:10:17 PM PDT 24	156540651 ps
T79	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.237432557	Mar 14 01:10:44 PM PDT 24	Mar 14 01:10:47 PM PDT 24	83873508 ps
T64	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.4110781560	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:35 PM PDT 24	57275186 ps
T110	/workspace/coverage/cover_reg_top/45.kmac_intr_test.1818934320	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:13 PM PDT 24	33037968 ps
T111	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2705431558	Mar 14 01:10:51 PM PDT 24	Mar 14 01:10:54 PM PDT 24	137770155 ps
T112	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3958380491	Mar 14 01:10:31 PM PDT 24	Mar 14 01:10:35 PM PDT 24	135224194 ps
T113	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1901797204	Mar 14 01:10:11 PM PDT 24	Mar 14 01:10:14 PM PDT 24	492272610 ps
T114	/workspace/coverage/cover_reg_top/49.kmac_intr_test.232095241	Mar 14 01:11:14 PM PDT 24	Mar 14 01:11:15 PM PDT 24	13905543 ps
T66	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.1724663934	Mar 14 01:10:31 PM PDT 24	Mar 14 01:10:36 PM PDT 24	190831238 ps
T80	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.513751308	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:38 PM PDT 24	808651731 ps
T115	/workspace/coverage/cover_reg_top/16.kmac_intr_test.3631392768	Mar 14 01:10:45 PM PDT 24	Mar 14 01:10:46 PM PDT 24	15830872 ps
T60	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2878619875	Mar 14 01:10:47 PM PDT 24	Mar 14 01:10:50 PM PDT 24	496494532 ps
T116	/workspace/coverage/cover_reg_top/2.kmac_intr_test.611357791	Mar 14 01:10:27 PM PDT 24	Mar 14 01:10:28 PM PDT 24	24987657 ps
T117	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.484215605	Mar 14 01:11:11 PM PDT 24	Mar 14 01:11:13 PM PDT 24	27274879 ps
T118	/workspace/coverage/cover_reg_top/3.kmac_intr_test.2918454360	Mar 14 01:10:28 PM PDT 24	Mar 14 01:10:31 PM PDT 24	19492754 ps
T119	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2729619012	Mar 14 01:10:40 PM PDT 24	Mar 14 01:10:42 PM PDT 24	147200495 ps
T120	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1576991160	Mar 14 01:10:51 PM PDT 24	Mar 14 01:10:53 PM PDT 24	73015206 ps
T121	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2727680424	Mar 14 01:10:29 PM PDT 24	Mar 14 01:10:37 PM PDT 24	809930268 ps
T122	/workspace/coverage/cover_reg_top/34.kmac_intr_test.153889868	Mar 14 01:11:21 PM PDT 24	Mar 14 01:11:22 PM PDT 24	12936806 ps
T123	/workspace/coverage/cover_reg_top/46.kmac_intr_test.2524221205	Mar 14 01:11:09 PM PDT 24	Mar 14 01:11:10 PM PDT 24	12296149 ps
T124	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.4032102139	Mar 14 01:11:11 PM PDT 24	Mar 14 01:11:12 PM PDT 24	138601439 ps
T125	/workspace/coverage/cover_reg_top/43.kmac_intr_test.1718007829	Mar 14 01:11:09 PM PDT 24	Mar 14 01:11:10 PM PDT 24	56241063 ps
T126	/workspace/coverage/cover_reg_top/30.kmac_intr_test.2249274846	Mar 14 01:11:14 PM PDT 24	Mar 14 01:11:15 PM PDT 24	49189008 ps
T127	/workspace/coverage/cover_reg_top/33.kmac_intr_test.3308479103	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:14 PM PDT 24	17927943 ps
T128	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2317688857	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:51 PM PDT 24	3847490427 ps
T129	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2487134671	Mar 14 01:10:52 PM PDT 24	Mar 14 01:10:55 PM PDT 24	153170108 ps
T130	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.956420816	Mar 14 01:10:41 PM PDT 24	Mar 14 01:10:42 PM PDT 24	51148790 ps
T67	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1268899398	Mar 14 01:10:52 PM PDT 24	Mar 14 01:10:54 PM PDT 24	58560929 ps
T81	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1611446763	Mar 14 01:10:31 PM PDT 24	Mar 14 01:10:38 PM PDT 24	380868714 ps
T131	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.4103761770	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:36 PM PDT 24	212991508 ps
T132	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.883383553	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:37 PM PDT 24	64682643 ps
T133	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1839930405	Mar 14 01:10:44 PM PDT 24	Mar 14 01:10:46 PM PDT 24	83939080 ps
T134	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1950637781	Mar 14 01:10:51 PM PDT 24	Mar 14 01:10:53 PM PDT 24	21581407 ps
T37	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3940776448	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:36 PM PDT 24	108609905 ps
T135	/workspace/coverage/cover_reg_top/47.kmac_intr_test.4049707131	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:13 PM PDT 24	18291712 ps
T136	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2990339272	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:35 PM PDT 24	29529982 ps
T137	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3578819308	Mar 14 01:11:11 PM PDT 24	Mar 14 01:11:14 PM PDT 24	101432117 ps
T138	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.4207944446	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:35 PM PDT 24	20954568 ps
T139	/workspace/coverage/cover_reg_top/31.kmac_intr_test.3461924806	Mar 14 01:11:10 PM PDT 24	Mar 14 01:11:11 PM PDT 24	19640145 ps
T140	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3089597742	Mar 14 01:10:51 PM PDT 24	Mar 14 01:10:54 PM PDT 24	484681100 ps
T141	/workspace/coverage/cover_reg_top/29.kmac_intr_test.2710699037	Mar 14 01:11:14 PM PDT 24	Mar 14 01:11:15 PM PDT 24	55252765 ps
T142	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2706530109	Mar 14 01:10:15 PM PDT 24	Mar 14 01:10:16 PM PDT 24	25860692 ps
T143	/workspace/coverage/cover_reg_top/11.kmac_intr_test.2553289444	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:35 PM PDT 24	28848173 ps
T84	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1234792230	Mar 14 01:10:58 PM PDT 24	Mar 14 01:10:59 PM PDT 24	61258568 ps
T144	/workspace/coverage/cover_reg_top/48.kmac_intr_test.506668363	Mar 14 01:11:14 PM PDT 24	Mar 14 01:11:15 PM PDT 24	21530547 ps
T145	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2965130280	Mar 14 01:10:31 PM PDT 24	Mar 14 01:10:35 PM PDT 24	211234330 ps
T146	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.994252139	Mar 14 01:10:35 PM PDT 24	Mar 14 01:10:38 PM PDT 24	100758645 ps
T147	/workspace/coverage/cover_reg_top/23.kmac_intr_test.250574395	Mar 14 01:11:14 PM PDT 24	Mar 14 01:11:15 PM PDT 24	25758600 ps
T85	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.161896824	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:35 PM PDT 24	36982639 ps
T148	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.2206887858	Mar 14 01:10:47 PM PDT 24	Mar 14 01:10:48 PM PDT 24	19939186 ps
T149	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3968179230	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:36 PM PDT 24	48760934 ps
T150	/workspace/coverage/cover_reg_top/13.kmac_intr_test.2452363418	Mar 14 01:10:47 PM PDT 24	Mar 14 01:10:48 PM PDT 24	13350107 ps
T151	/workspace/coverage/cover_reg_top/0.kmac_intr_test.2258033989	Mar 14 01:10:12 PM PDT 24	Mar 14 01:10:13 PM PDT 24	27312137 ps
T152	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1934687777	Mar 14 01:10:31 PM PDT 24	Mar 14 01:10:34 PM PDT 24	61755030 ps
T75	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.482245120	Mar 14 01:10:13 PM PDT 24	Mar 14 01:10:18 PM PDT 24	626734176 ps
T153	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2111276941	Mar 14 01:10:52 PM PDT 24	Mar 14 01:10:55 PM PDT 24	1551674707 ps
T154	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.971411389	Mar 14 01:10:31 PM PDT 24	Mar 14 01:10:35 PM PDT 24	85077098 ps
T155	/workspace/coverage/cover_reg_top/5.kmac_intr_test.3016838238	Mar 14 01:10:35 PM PDT 24	Mar 14 01:10:36 PM PDT 24	15179810 ps
T156	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.4086289117	Mar 14 01:10:35 PM PDT 24	Mar 14 01:10:37 PM PDT 24	121143687 ps
T157	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3343468047	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:35 PM PDT 24	49376560 ps
T158	/workspace/coverage/cover_reg_top/20.kmac_intr_test.92754333	Mar 14 01:11:12 PM PDT 24	Mar 14 01:11:12 PM PDT 24	37729941 ps
T38	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2878176960	Mar 14 01:10:28 PM PDT 24	Mar 14 01:10:31 PM PDT 24	62193430 ps
T159	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3012217029	Mar 14 01:10:43 PM PDT 24	Mar 14 01:10:44 PM PDT 24	24000263 ps
T160	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2024341461	Mar 14 01:10:41 PM PDT 24	Mar 14 01:10:42 PM PDT 24	52328400 ps
T161	/workspace/coverage/cover_reg_top/27.kmac_intr_test.99952041	Mar 14 01:11:10 PM PDT 24	Mar 14 01:11:11 PM PDT 24	30005367 ps
T162	/workspace/coverage/cover_reg_top/14.kmac_intr_test.3868529022	Mar 14 01:10:43 PM PDT 24	Mar 14 01:10:44 PM PDT 24	60516876 ps
T163	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.542799733	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:36 PM PDT 24	55045387 ps
T63	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.2694853224	Mar 14 01:10:55 PM PDT 24	Mar 14 01:10:59 PM PDT 24	686099613 ps
T164	/workspace/coverage/cover_reg_top/15.kmac_intr_test.571435696	Mar 14 01:10:43 PM PDT 24	Mar 14 01:10:44 PM PDT 24	17136600 ps
T165	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.1051772498	Mar 14 01:10:16 PM PDT 24	Mar 14 01:10:17 PM PDT 24	30442283 ps
T166	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.2242650090	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:36 PM PDT 24	19031530 ps
T167	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.910195540	Mar 14 01:10:37 PM PDT 24	Mar 14 01:10:39 PM PDT 24	155527792 ps
T168	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3547554940	Mar 14 01:10:31 PM PDT 24	Mar 14 01:10:34 PM PDT 24	11077412 ps
T169	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.684098406	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:37 PM PDT 24	160118115 ps
T170	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.977110832	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:37 PM PDT 24	126123562 ps
T171	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.954136036	Mar 14 01:11:14 PM PDT 24	Mar 14 01:11:16 PM PDT 24	57313087 ps
T172	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.1673171222	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:36 PM PDT 24	75581340 ps
T173	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.691125827	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:37 PM PDT 24	41066466 ps
T174	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3063408241	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:37 PM PDT 24	469913131 ps
T175	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.1409935844	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:33 PM PDT 24	17660902 ps
T176	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3069051434	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:38 PM PDT 24	194962561 ps
T177	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3214478138	Mar 14 01:10:52 PM PDT 24	Mar 14 01:10:56 PM PDT 24	148039899 ps
T178	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2788577546	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:15 PM PDT 24	50819729 ps
T179	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1407175158	Mar 14 01:10:50 PM PDT 24	Mar 14 01:10:53 PM PDT 24	104996323 ps
T180	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.198153951	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:36 PM PDT 24	173775331 ps
T181	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.3455836736	Mar 14 01:10:46 PM PDT 24	Mar 14 01:10:48 PM PDT 24	628448779 ps
T182	/workspace/coverage/cover_reg_top/1.kmac_intr_test.1083900014	Mar 14 01:10:14 PM PDT 24	Mar 14 01:10:15 PM PDT 24	30524906 ps
T183	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.4113050847	Mar 14 01:10:44 PM PDT 24	Mar 14 01:10:45 PM PDT 24	113963422 ps
T39	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2161365756	Mar 14 01:10:28 PM PDT 24	Mar 14 01:10:33 PM PDT 24	148888363 ps
T184	/workspace/coverage/cover_reg_top/35.kmac_intr_test.342202709	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:14 PM PDT 24	15889103 ps
T185	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1192947444	Mar 14 01:10:14 PM PDT 24	Mar 14 01:10:23 PM PDT 24	1785915794 ps
T186	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.1119158352	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:36 PM PDT 24	27649692 ps
T187	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.1979922663	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:34 PM PDT 24	29066952 ps
T188	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3158378339	Mar 14 01:11:10 PM PDT 24	Mar 14 01:11:12 PM PDT 24	91440877 ps
T189	/workspace/coverage/cover_reg_top/25.kmac_intr_test.2982757762	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:14 PM PDT 24	169744493 ps
T190	/workspace/coverage/cover_reg_top/28.kmac_intr_test.1391595437	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:14 PM PDT 24	15436231 ps
T76	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.409532736	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:38 PM PDT 24	1375242689 ps
T59	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3972651552	Mar 14 01:10:32 PM PDT 24	Mar 14 01:10:35 PM PDT 24	33045192 ps
T191	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2710264402	Mar 14 01:11:14 PM PDT 24	Mar 14 01:11:16 PM PDT 24	59519549 ps
T192	/workspace/coverage/cover_reg_top/41.kmac_intr_test.1590769940	Mar 14 01:11:12 PM PDT 24	Mar 14 01:11:13 PM PDT 24	18618337 ps
T193	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.142863560	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:36 PM PDT 24	82265602 ps
T194	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3160522743	Mar 14 01:10:14 PM PDT 24	Mar 14 01:10:17 PM PDT 24	95568010 ps
T195	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.805362100	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:39 PM PDT 24	1030497667 ps
T196	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.778756042	Mar 14 01:10:34 PM PDT 24	Mar 14 01:10:36 PM PDT 24	29395751 ps
T197	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.340205847	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:35 PM PDT 24	18158377 ps
T198	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.159144757	Mar 14 01:10:33 PM PDT 24	Mar 14 01:10:37 PM PDT 24	165193807 ps
T199	/workspace/coverage/cover_reg_top/6.kmac_intr_test.4289773143	Mar 14 01:10:31 PM PDT 24	Mar 14 01:10:35 PM PDT 24	11135830 ps
T200	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2268312608	Mar 14 01:10:28 PM PDT 24	Mar 14 01:10:32 PM PDT 24	65727649 ps
T201	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1866983905	Mar 14 01:10:18 PM PDT 24	Mar 14 01:10:19 PM PDT 24	22875409 ps
T202	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1644603952	Mar 14 01:11:14 PM PDT 24	Mar 14 01:11:16 PM PDT 24	40119624 ps
T203	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.675802895	Mar 14 01:10:51 PM PDT 24	Mar 14 01:10:54 PM PDT 24	143972674 ps
T204	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3498748387	Mar 14 01:10:35 PM PDT 24	Mar 14 01:10:37 PM PDT 24	128369512 ps
T205	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1088448346	Mar 14 01:10:40 PM PDT 24	Mar 14 01:10:41 PM PDT 24	67074968 ps
T206	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3973535502	Mar 14 01:10:44 PM PDT 24	Mar 14 01:10:47 PM PDT 24	499396649 ps
T207	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.716451044	Mar 14 01:10:30 PM PDT 24	Mar 14 01:10:43 PM PDT 24	516414898 ps
T208	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.4125672379	Mar 14 01:10:45 PM PDT 24	Mar 14 01:10:48 PM PDT 24	355879658 ps
T209	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.2059760260	Mar 14 01:10:15 PM PDT 24	Mar 14 01:10:17 PM PDT 24	87453429 ps
T210	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.4213430193	Mar 14 01:10:47 PM PDT 24	Mar 14 01:10:48 PM PDT 24	43493162 ps
T211	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.2818380614	Mar 14 01:10:46 PM PDT 24	Mar 14 01:10:47 PM PDT 24	82550703 ps
T212	/workspace/coverage/cover_reg_top/42.kmac_intr_test.3747269781	Mar 14 01:11:10 PM PDT 24	Mar 14 01:11:11 PM PDT 24	42062916 ps
T213	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3769781060	Mar 14 01:10:44 PM PDT 24	Mar 14 01:10:45 PM PDT 24	60471181 ps
T214	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2426948219	Mar 14 01:11:11 PM PDT 24	Mar 14 01:11:13 PM PDT 24	157839288 ps
T215	/workspace/coverage/cover_reg_top/38.kmac_intr_test.2874326184	Mar 14 01:11:13 PM PDT 24	Mar 14 01:11:14 PM PDT 24	25975534 ps

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2852738143
Short name	T2
Test name
Test status
Simulation time	55695432 ps
CPU time	2.46 seconds
Started	Mar 14 01:11:15 PM PDT 24
Finished	Mar 14 01:11:17 PM PDT 24
Peak memory	206756 kb
Host	smart-84e6c0d8-cf36-4e27-a4fe-a657bd56975a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852738143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2852 738143 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.272407945
Short name	T15
Test name
Test status
Simulation time	410469062 ps
CPU time	2.78 seconds
Started	Mar 14 01:10:14 PM PDT 24
Finished	Mar 14 01:10:17 PM PDT 24
Peak memory	215048 kb
Host	smart-4ca96f0b-e5de-4ea0-b0cf-13ce2abb19b0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272407945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.272407945 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.468642161
Short name	T8
Test name
Test status
Simulation time	19329824 ps
CPU time	0.84 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:14 PM PDT 24
Peak memory	206648 kb
Host	smart-baeff715-7e1c-4bf6-a0e1-f2245db9637f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468642161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.468642161 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.4254766957
Short name	T56
Test name
Test status
Simulation time	178901102 ps
CPU time	3.19 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:38 PM PDT 24
Peak memory	223684 kb
Host	smart-044e2d75-b6a4-4acc-9eb9-7ebca9afe65f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254766957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.4254766957 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.4188806302
Short name	T69
Test name
Test status
Simulation time	423442172 ps
CPU time	4.83 seconds
Started	Mar 14 01:10:42 PM PDT 24
Finished	Mar 14 01:10:47 PM PDT 24
Peak memory	214956 kb
Host	smart-927999cc-cfa3-40d8-bad3-0da36ee74457
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188806302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.4188 806302 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.865910416
Short name	T13
Test name
Test status
Simulation time	31481304 ps
CPU time	1.25 seconds
Started	Mar 14 01:10:13 PM PDT 24
Finished	Mar 14 01:10:15 PM PDT 24
Peak memory	215016 kb
Host	smart-a3916c2c-e726-46d1-bcb8-6cb3918c0a06
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865910416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial _access.865910416 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1079150974
Short name	T55
Test name
Test status
Simulation time	34608764 ps
CPU time	1.27 seconds
Started	Mar 14 01:10:48 PM PDT 24
Finished	Mar 14 01:10:49 PM PDT 24
Peak memory	215480 kb
Host	smart-a4f6aec7-97d5-4385-a7f2-03d43e1e4d74
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079150974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg _errors.1079150974 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.4055263657
Short name	T6
Test name
Test status
Simulation time	12555829 ps
CPU time	0.8 seconds
Started	Mar 14 01:10:44 PM PDT 24
Finished	Mar 14 01:10:45 PM PDT 24
Peak memory	206688 kb
Host	smart-0b9500dd-df23-4468-af5e-f65d3aa10211
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055263657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.4055263657 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.409532736
Short name	T76
Test name
Test status
Simulation time	1375242689 ps
CPU time	3.05 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:38 PM PDT 24
Peak memory	214952 kb
Host	smart-9e7c343b-b656-4a87-82e9-d79e420da48b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409532736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.409532 736 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1268899398
Short name	T67
Test name
Test status
Simulation time	58560929 ps
CPU time	1.89 seconds
Started	Mar 14 01:10:52 PM PDT 24
Finished	Mar 14 01:10:54 PM PDT 24
Peak memory	215104 kb
Host	smart-0800dd08-f69d-421c-a6e3-2adf61e82c3d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268899398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1268899398 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1611446763
Short name	T81
Test name
Test status
Simulation time	380868714 ps
CPU time	4.54 seconds
Started	Mar 14 01:10:31 PM PDT 24
Finished	Mar 14 01:10:38 PM PDT 24
Peak memory	214884 kb
Host	smart-0957df2e-457e-42cc-9c85-fae828ce8998
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611446763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.16114 46763 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1601196281
Short name	T36
Test name
Test status
Simulation time	118995514 ps
CPU time	1.43 seconds
Started	Mar 14 01:10:13 PM PDT 24
Finished	Mar 14 01:10:15 PM PDT 24
Peak memory	214892 kb
Host	smart-4f30944a-7d71-4f5c-922c-2eeeecea0bba
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601196281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.1601196281 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3040256451
Short name	T29
Test name
Test status
Simulation time	96901019 ps
CPU time	2.54 seconds
Started	Mar 14 01:10:14 PM PDT 24
Finished	Mar 14 01:10:16 PM PDT 24
Peak memory	215156 kb
Host	smart-5a1857d7-f1ec-42d8-a7e7-5e3c181c8c4b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040256451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.3040256451 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3190949317
Short name	T23
Test name
Test status
Simulation time	148288531 ps
CPU time	4.21 seconds
Started	Mar 14 01:10:12 PM PDT 24
Finished	Mar 14 01:10:16 PM PDT 24
Peak memory	214988 kb
Host	smart-94e1eb09-43b4-4864-9aba-859776e5f748
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190949317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.31909 49317 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.142863560
Short name	T193
Test name
Test status
Simulation time	82265602 ps
CPU time	1.07 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	207324 kb
Host	smart-67472084-454a-4c8e-af44-2c786efcf652
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142863560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_ errors.142863560 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.4213430193
Short name	T210
Test name
Test status
Simulation time	43493162 ps
CPU time	1.47 seconds
Started	Mar 14 01:10:47 PM PDT 24
Finished	Mar 14 01:10:48 PM PDT 24
Peak memory	215148 kb
Host	smart-a2fccdf8-562f-4b01-9212-2ca509fb6f6d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213430193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.4213430193 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1192947444
Short name	T185
Test name
Test status
Simulation time	1785915794 ps
CPU time	9.15 seconds
Started	Mar 14 01:10:14 PM PDT 24
Finished	Mar 14 01:10:23 PM PDT 24
Peak memory	206756 kb
Host	smart-5731d70c-309c-4155-8842-170661a13f14
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192947444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1192947 444 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.229217101
Short name	T98
Test name
Test status
Simulation time	637767389 ps
CPU time	10.01 seconds
Started	Mar 14 01:10:16 PM PDT 24
Finished	Mar 14 01:10:26 PM PDT 24
Peak memory	206764 kb
Host	smart-e5662412-c38a-4541-8d34-ea2ba5a42d16
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229217101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.22921710 1 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3086292975
Short name	T109
Test name
Test status
Simulation time	156540651 ps
CPU time	1.04 seconds
Started	Mar 14 01:10:15 PM PDT 24
Finished	Mar 14 01:10:17 PM PDT 24
Peak memory	206644 kb
Host	smart-6eb69607-86da-48ce-bc72-3d7159a88bed
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086292975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3086292 975 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4185249248
Short name	T108
Test name
Test status
Simulation time	127226299 ps
CPU time	2.61 seconds
Started	Mar 14 01:10:16 PM PDT 24
Finished	Mar 14 01:10:19 PM PDT 24
Peak memory	223224 kb
Host	smart-c546c5e8-43d7-40d9-a077-6922b7621fd3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185249248 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.4185249248 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.333016981
Short name	T68
Test name
Test status
Simulation time	114882795 ps
CPU time	1.11 seconds
Started	Mar 14 01:10:13 PM PDT 24
Finished	Mar 14 01:10:15 PM PDT 24
Peak memory	206704 kb
Host	smart-8f2f8aaf-e077-458e-9ccb-7497861bd22d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333016981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.333016981 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.2258033989
Short name	T151
Test name
Test status
Simulation time	27312137 ps
CPU time	0.76 seconds
Started	Mar 14 01:10:12 PM PDT 24
Finished	Mar 14 01:10:13 PM PDT 24
Peak memory	206648 kb
Host	smart-9280074c-a5f8-436c-bd02-63ad7563b728
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258033989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2258033989 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.1051772498
Short name	T165
Test name
Test status
Simulation time	30442283 ps
CPU time	0.77 seconds
Started	Mar 14 01:10:16 PM PDT 24
Finished	Mar 14 01:10:17 PM PDT 24
Peak memory	206684 kb
Host	smart-dba97062-cc50-40e0-8826-18e8882be453
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051772498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1051772498 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1866983905
Short name	T201
Test name
Test status
Simulation time	22875409 ps
CPU time	1.1 seconds
Started	Mar 14 01:10:18 PM PDT 24
Finished	Mar 14 01:10:19 PM PDT 24
Peak memory	215476 kb
Host	smart-14ef89ec-c1fa-44cd-ae4b-b30fbbd999f4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866983905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.1866983905 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3160522743
Short name	T194
Test name
Test status
Simulation time	95568010 ps
CPU time	2.63 seconds
Started	Mar 14 01:10:14 PM PDT 24
Finished	Mar 14 01:10:17 PM PDT 24
Peak memory	223088 kb
Host	smart-197bf29f-dc15-4a63-b514-d70e6fb83216
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160522743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac _shadow_reg_errors_with_csr_rw.3160522743 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3273041577
Short name	T92
Test name
Test status
Simulation time	600994673 ps
CPU time	9.82 seconds
Started	Mar 14 01:10:28 PM PDT 24
Finished	Mar 14 01:10:39 PM PDT 24
Peak memory	206788 kb
Host	smart-05d0c611-0490-44c8-ad17-17054538bf37
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273041577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3273041 577 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1160818072
Short name	T95
Test name
Test status
Simulation time	754064864 ps
CPU time	10.76 seconds
Started	Mar 14 01:10:35 PM PDT 24
Finished	Mar 14 01:10:46 PM PDT 24
Peak memory	206776 kb
Host	smart-1e52cb35-5c50-4e42-885b-65749d37902c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160818072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1160818 072 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2706530109
Short name	T142
Test name
Test status
Simulation time	25860692 ps
CPU time	1.08 seconds
Started	Mar 14 01:10:15 PM PDT 24
Finished	Mar 14 01:10:16 PM PDT 24
Peak memory	214876 kb
Host	smart-33041405-857a-4341-aabf-784088b2b91d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706530109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2706530 109 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.198153951
Short name	T180
Test name
Test status
Simulation time	173775331 ps
CPU time	1.58 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	214948 kb
Host	smart-d5185fc4-3047-434d-89b1-3165bb7699eb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198153951 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.198153951 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.2059760260
Short name	T209
Test name
Test status
Simulation time	87453429 ps
CPU time	1.17 seconds
Started	Mar 14 01:10:15 PM PDT 24
Finished	Mar 14 01:10:17 PM PDT 24
Peak memory	214860 kb
Host	smart-e2b5885b-a5c6-4298-9559-0d14e96fe86f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059760260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2059760260 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.1083900014
Short name	T182
Test name
Test status
Simulation time	30524906 ps
CPU time	0.74 seconds
Started	Mar 14 01:10:14 PM PDT 24
Finished	Mar 14 01:10:15 PM PDT 24
Peak memory	206680 kb
Host	smart-52d0f43a-d71f-484f-aba5-e6edb0708196
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083900014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1083900014 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.837912825
Short name	T34
Test name
Test status
Simulation time	36290481 ps
CPU time	0.73 seconds
Started	Mar 14 01:10:13 PM PDT 24
Finished	Mar 14 01:10:14 PM PDT 24
Peak memory	206664 kb
Host	smart-dc8cf46d-dcca-4f12-8ae2-d83e08e00675
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837912825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.837912825 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3343468047
Short name	T157
Test name
Test status
Simulation time	49376560 ps
CPU time	1.52 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	215028 kb
Host	smart-48218508-1fb5-4d73-81da-f045150ebce6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343468047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr _outstanding.3343468047 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3344714839
Short name	T48
Test name
Test status
Simulation time	160527792 ps
CPU time	1.29 seconds
Started	Mar 14 01:10:12 PM PDT 24
Finished	Mar 14 01:10:14 PM PDT 24
Peak memory	215384 kb
Host	smart-2ca6ff4b-c5a1-4dff-89af-f1ca483e0f01
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344714839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_ errors.3344714839 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1901797204
Short name	T113
Test name
Test status
Simulation time	492272610 ps
CPU time	2.61 seconds
Started	Mar 14 01:10:11 PM PDT 24
Finished	Mar 14 01:10:14 PM PDT 24
Peak memory	215476 kb
Host	smart-7ac45890-5c13-4905-9730-3374a054504f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901797204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac _shadow_reg_errors_with_csr_rw.1901797204 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.428725419
Short name	T99
Test name
Test status
Simulation time	333655385 ps
CPU time	2.73 seconds
Started	Mar 14 01:10:16 PM PDT 24
Finished	Mar 14 01:10:19 PM PDT 24
Peak memory	215088 kb
Host	smart-c89ef999-610b-4588-a868-0fc9e3619e8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428725419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.428725419 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.482245120
Short name	T75
Test name
Test status
Simulation time	626734176 ps
CPU time	4.92 seconds
Started	Mar 14 01:10:13 PM PDT 24
Finished	Mar 14 01:10:18 PM PDT 24
Peak memory	214948 kb
Host	smart-c91be0a4-c6ea-426c-b12f-a5824b3f8bbc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482245120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.482245 120 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2224513143
Short name	T5
Test name
Test status
Simulation time	25003313 ps
CPU time	1.71 seconds
Started	Mar 14 01:10:37 PM PDT 24
Finished	Mar 14 01:10:39 PM PDT 24
Peak memory	215076 kb
Host	smart-f52f019d-b5e8-4b7e-96b2-5a93a136466a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224513143 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.2224513143 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3917241677
Short name	T53
Test name
Test status
Simulation time	36264868 ps
CPU time	1.13 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	215008 kb
Host	smart-61a88709-a794-4f73-9670-8bd8d7b8794d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917241677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.3917241677 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.3782898427
Short name	T72
Test name
Test status
Simulation time	18704552 ps
CPU time	0.88 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	206648 kb
Host	smart-0777c613-108e-4700-88c8-bac5bdd40042
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782898427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3782898427 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.910195540
Short name	T167
Test name
Test status
Simulation time	155527792 ps
CPU time	2.2 seconds
Started	Mar 14 01:10:37 PM PDT 24
Finished	Mar 14 01:10:39 PM PDT 24
Peak memory	215080 kb
Host	smart-99b5b19e-21ac-47aa-8b8c-24fc09df5b85
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910195540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr _outstanding.910195540 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2778920704
Short name	T70
Test name
Test status
Simulation time	48949745 ps
CPU time	1.14 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	215528 kb
Host	smart-68e74539-6d7f-4619-9e14-54ed1218d247
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778920704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg _errors.2778920704 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1908729578
Short name	T52
Test name
Test status
Simulation time	78694288 ps
CPU time	1.95 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	215436 kb
Host	smart-47024caf-8041-41ab-989c-118b1889bc59
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908729578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma c_shadow_reg_errors_with_csr_rw.1908729578 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.3282895128
Short name	T17
Test name
Test status
Simulation time	320145108 ps
CPU time	1.74 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	215140 kb
Host	smart-5acd363c-731d-4be9-92b3-7864bf0ec058
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282895128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3282895128 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.510871035
Short name	T1
Test name
Test status
Simulation time	82544438 ps
CPU time	2.35 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	206772 kb
Host	smart-eda6b956-b0dd-42de-8e3d-ea27e3bbc844
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510871035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.51087 1035 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1425283847
Short name	T94
Test name
Test status
Simulation time	45772839 ps
CPU time	1.53 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	223060 kb
Host	smart-73cd9223-0702-4ea5-8b23-760ee35332b2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425283847 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1425283847 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.778756042
Short name	T196
Test name
Test status
Simulation time	29395751 ps
CPU time	0.91 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	206608 kb
Host	smart-52654f76-d71b-42b6-9389-299be825a6d7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778756042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.778756042 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.2553289444
Short name	T143
Test name
Test status
Simulation time	28848173 ps
CPU time	0.77 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	206540 kb
Host	smart-5dd1edad-8fb6-4b52-afec-98bd6f22b8a8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553289444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2553289444 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2552169138
Short name	T43
Test name
Test status
Simulation time	284977386 ps
CPU time	1.61 seconds
Started	Mar 14 01:10:37 PM PDT 24
Finished	Mar 14 01:10:39 PM PDT 24
Peak memory	215032 kb
Host	smart-3f571e14-39e3-4b13-9e1a-187934b69c26
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552169138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs r_outstanding.2552169138 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3063408241
Short name	T174
Test name
Test status
Simulation time	469913131 ps
CPU time	1.9 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	215464 kb
Host	smart-d9bd3bd7-5be6-4983-9d85-ddf9bc70ed7d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063408241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma c_shadow_reg_errors_with_csr_rw.3063408241 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2165574485
Short name	T12
Test name
Test status
Simulation time	440241495 ps
CPU time	1.97 seconds
Started	Mar 14 01:10:37 PM PDT 24
Finished	Mar 14 01:10:39 PM PDT 24
Peak memory	223248 kb
Host	smart-6f63db51-e88d-4ff3-86fa-2f69f91768e9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165574485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2165574485 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.1315315358
Short name	T77
Test name
Test status
Simulation time	164741098 ps
CPU time	4.08 seconds
Started	Mar 14 01:10:36 PM PDT 24
Finished	Mar 14 01:10:41 PM PDT 24
Peak memory	214968 kb
Host	smart-4353c21c-97c2-4c93-9a21-14aedf9f75e4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315315358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.1315 315358 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3012217029
Short name	T159
Test name
Test status
Simulation time	24000263 ps
CPU time	1.61 seconds
Started	Mar 14 01:10:43 PM PDT 24
Finished	Mar 14 01:10:44 PM PDT 24
Peak memory	223172 kb
Host	smart-593c118a-302e-4c9d-a5ea-5b0935c268bd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012217029 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.3012217029 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.2308518134
Short name	T10
Test name
Test status
Simulation time	86359559 ps
CPU time	1.14 seconds
Started	Mar 14 01:10:45 PM PDT 24
Finished	Mar 14 01:10:46 PM PDT 24
Peak memory	214956 kb
Host	smart-83084263-8aa2-4a6f-93fa-083b7e42c9a2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308518134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2308518134 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1657653522
Short name	T49
Test name
Test status
Simulation time	155847554 ps
CPU time	2.25 seconds
Started	Mar 14 01:10:45 PM PDT 24
Finished	Mar 14 01:10:47 PM PDT 24
Peak memory	214928 kb
Host	smart-4cf11c11-44fe-4714-9072-992a015fa7e7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657653522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.1657653522 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1088448346
Short name	T205
Test name
Test status
Simulation time	67074968 ps
CPU time	1.02 seconds
Started	Mar 14 01:10:40 PM PDT 24
Finished	Mar 14 01:10:41 PM PDT 24
Peak memory	215408 kb
Host	smart-ba43f331-c8d9-4b03-8f65-07ea06b087f4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088448346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.1088448346 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2878619875
Short name	T60
Test name
Test status
Simulation time	496494532 ps
CPU time	2.96 seconds
Started	Mar 14 01:10:47 PM PDT 24
Finished	Mar 14 01:10:50 PM PDT 24
Peak memory	215424 kb
Host	smart-013c57ad-43d0-4881-bf00-b5fd13d93d2d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878619875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma c_shadow_reg_errors_with_csr_rw.2878619875 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2729619012
Short name	T119
Test name
Test status
Simulation time	147200495 ps
CPU time	2.37 seconds
Started	Mar 14 01:10:40 PM PDT 24
Finished	Mar 14 01:10:42 PM PDT 24
Peak memory	215016 kb
Host	smart-151ada04-7d0b-4dcb-989c-bc2037b29c9e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729619012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2729 619012 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1576991160
Short name	T120
Test name
Test status
Simulation time	73015206 ps
CPU time	1.57 seconds
Started	Mar 14 01:10:51 PM PDT 24
Finished	Mar 14 01:10:53 PM PDT 24
Peak memory	223204 kb
Host	smart-377ddef3-849c-416a-a22d-5fad3b57ae8f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576991160 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.1576991160 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.4113050847
Short name	T183
Test name
Test status
Simulation time	113963422 ps
CPU time	1.18 seconds
Started	Mar 14 01:10:44 PM PDT 24
Finished	Mar 14 01:10:45 PM PDT 24
Peak memory	206796 kb
Host	smart-e1744702-016c-4fb6-a7ca-943c3fcc5225
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113050847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.4113050847 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.2452363418
Short name	T150
Test name
Test status
Simulation time	13350107 ps
CPU time	0.79 seconds
Started	Mar 14 01:10:47 PM PDT 24
Finished	Mar 14 01:10:48 PM PDT 24
Peak memory	206688 kb
Host	smart-7b40c437-e6f3-4ca1-b00d-eff61e7703e0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452363418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2452363418 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2705431558
Short name	T111
Test name
Test status
Simulation time	137770155 ps
CPU time	2.25 seconds
Started	Mar 14 01:10:51 PM PDT 24
Finished	Mar 14 01:10:54 PM PDT 24
Peak memory	215060 kb
Host	smart-7dc8821f-836b-4a83-968e-5498409e92c9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705431558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs r_outstanding.2705431558 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3769781060
Short name	T213
Test name
Test status
Simulation time	60471181 ps
CPU time	0.94 seconds
Started	Mar 14 01:10:44 PM PDT 24
Finished	Mar 14 01:10:45 PM PDT 24
Peak memory	206744 kb
Host	smart-1348206b-96ca-4775-a70c-0ac50209a4e6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769781060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.3769781060 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2024341461
Short name	T160
Test name
Test status
Simulation time	52328400 ps
CPU time	1.61 seconds
Started	Mar 14 01:10:41 PM PDT 24
Finished	Mar 14 01:10:42 PM PDT 24
Peak memory	215440 kb
Host	smart-f3f66026-7dff-49d1-8bfe-31c5b5beb39b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024341461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.2024341461 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.89065527
Short name	T16
Test name
Test status
Simulation time	114843984 ps
CPU time	2.39 seconds
Started	Mar 14 01:10:46 PM PDT 24
Finished	Mar 14 01:10:49 PM PDT 24
Peak memory	223220 kb
Host	smart-3c9aacb4-b4c5-463f-ae68-2c38bc5a5ea9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89065527 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.89065527 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.2818380614
Short name	T211
Test name
Test status
Simulation time	82550703 ps
CPU time	1.07 seconds
Started	Mar 14 01:10:46 PM PDT 24
Finished	Mar 14 01:10:47 PM PDT 24
Peak memory	206760 kb
Host	smart-a77fef83-703e-4936-8cf8-62039c1cbaf7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818380614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2818380614 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.3868529022
Short name	T162
Test name
Test status
Simulation time	60516876 ps
CPU time	0.77 seconds
Started	Mar 14 01:10:43 PM PDT 24
Finished	Mar 14 01:10:44 PM PDT 24
Peak memory	206688 kb
Host	smart-94a013e8-6d5e-4e80-90c8-c1b8593cc07e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868529022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3868529022 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1041752656
Short name	T100
Test name
Test status
Simulation time	37086890 ps
CPU time	2.06 seconds
Started	Mar 14 01:10:39 PM PDT 24
Finished	Mar 14 01:10:42 PM PDT 24
Peak memory	215064 kb
Host	smart-226af4c1-83b4-43d9-a6e4-c0946233c88c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041752656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs r_outstanding.1041752656 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2575100654
Short name	T30
Test name
Test status
Simulation time	77104057 ps
CPU time	1.24 seconds
Started	Mar 14 01:10:39 PM PDT 24
Finished	Mar 14 01:10:41 PM PDT 24
Peak memory	215492 kb
Host	smart-782414f0-6326-462a-a8c8-3ee65bb1d01c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575100654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg _errors.2575100654 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3973535502
Short name	T206
Test name
Test status
Simulation time	499396649 ps
CPU time	3.07 seconds
Started	Mar 14 01:10:44 PM PDT 24
Finished	Mar 14 01:10:47 PM PDT 24
Peak memory	223188 kb
Host	smart-bcf9dd7d-1cef-4da7-a5b2-7feb620e0811
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973535502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.3973535502 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.326809412
Short name	T4
Test name
Test status
Simulation time	27257409 ps
CPU time	1.21 seconds
Started	Mar 14 01:10:46 PM PDT 24
Finished	Mar 14 01:10:48 PM PDT 24
Peak memory	215144 kb
Host	smart-30cfb249-ac85-41aa-ac94-cdecc73bb6f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326809412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.326809412 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3214478138
Short name	T177
Test name
Test status
Simulation time	148039899 ps
CPU time	4.22 seconds
Started	Mar 14 01:10:52 PM PDT 24
Finished	Mar 14 01:10:56 PM PDT 24
Peak memory	217628 kb
Host	smart-472a59b3-4bc2-405c-b6cc-41b0941129be
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214478138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3214 478138 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1950637781
Short name	T134
Test name
Test status
Simulation time	21581407 ps
CPU time	1.46 seconds
Started	Mar 14 01:10:51 PM PDT 24
Finished	Mar 14 01:10:53 PM PDT 24
Peak memory	222184 kb
Host	smart-f6bbabf9-8124-406e-a266-f723ce49c136
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950637781 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1950637781 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.956420816
Short name	T130
Test name
Test status
Simulation time	51148790 ps
CPU time	1.12 seconds
Started	Mar 14 01:10:41 PM PDT 24
Finished	Mar 14 01:10:42 PM PDT 24
Peak memory	215248 kb
Host	smart-5a333d9e-5320-48ed-b68d-11e00073513d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956420816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.956420816 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.571435696
Short name	T164
Test name
Test status
Simulation time	17136600 ps
CPU time	0.76 seconds
Started	Mar 14 01:10:43 PM PDT 24
Finished	Mar 14 01:10:44 PM PDT 24
Peak memory	206708 kb
Host	smart-b53b790d-6952-448f-a47b-663353346a87
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571435696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.571435696 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.675802895
Short name	T203
Test name
Test status
Simulation time	143972674 ps
CPU time	2.32 seconds
Started	Mar 14 01:10:51 PM PDT 24
Finished	Mar 14 01:10:54 PM PDT 24
Peak memory	215136 kb
Host	smart-a08d39c7-067c-465a-a238-f042e5bd3030
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675802895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr _outstanding.675802895 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2767540460
Short name	T97
Test name
Test status
Simulation time	23600119 ps
CPU time	1.03 seconds
Started	Mar 14 01:10:43 PM PDT 24
Finished	Mar 14 01:10:45 PM PDT 24
Peak memory	215520 kb
Host	smart-85cda545-684f-425d-9aef-a97dbafa2476
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767540460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.2767540460 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1168410040
Short name	T106
Test name
Test status
Simulation time	287274437 ps
CPU time	1.59 seconds
Started	Mar 14 01:10:41 PM PDT 24
Finished	Mar 14 01:10:43 PM PDT 24
Peak memory	215736 kb
Host	smart-0cd5a8d5-806b-4334-8bdb-8c27755bf94c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168410040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma c_shadow_reg_errors_with_csr_rw.1168410040 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.4125672379
Short name	T208
Test name
Test status
Simulation time	355879658 ps
CPU time	2.9 seconds
Started	Mar 14 01:10:45 PM PDT 24
Finished	Mar 14 01:10:48 PM PDT 24
Peak memory	214948 kb
Host	smart-8545ba8f-c7fe-464f-a10a-1282a7f7bba4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125672379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.4125672379 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1613540554
Short name	T82
Test name
Test status
Simulation time	1288061021 ps
CPU time	4.01 seconds
Started	Mar 14 01:10:51 PM PDT 24
Finished	Mar 14 01:10:56 PM PDT 24
Peak memory	214944 kb
Host	smart-3e35627f-fdba-4769-8ff2-301073123e1b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613540554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1613 540554 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2111276941
Short name	T153
Test name
Test status
Simulation time	1551674707 ps
CPU time	2.46 seconds
Started	Mar 14 01:10:52 PM PDT 24
Finished	Mar 14 01:10:55 PM PDT 24
Peak memory	223212 kb
Host	smart-b407854a-9a56-42ea-8616-af0ba4642722
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111276941 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2111276941 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.2206887858
Short name	T148
Test name
Test status
Simulation time	19939186 ps
CPU time	0.95 seconds
Started	Mar 14 01:10:47 PM PDT 24
Finished	Mar 14 01:10:48 PM PDT 24
Peak memory	206660 kb
Host	smart-e1efa2f4-66df-4ade-ac0d-0b9846c1dd08
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206887858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2206887858 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.3631392768
Short name	T115
Test name
Test status
Simulation time	15830872 ps
CPU time	0.8 seconds
Started	Mar 14 01:10:45 PM PDT 24
Finished	Mar 14 01:10:46 PM PDT 24
Peak memory	206540 kb
Host	smart-82c021c2-8de6-4fed-8528-07487df37cff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631392768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3631392768 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2421678864
Short name	T22
Test name
Test status
Simulation time	106868945 ps
CPU time	2.34 seconds
Started	Mar 14 01:10:54 PM PDT 24
Finished	Mar 14 01:10:56 PM PDT 24
Peak memory	214908 kb
Host	smart-7a8b0dfb-d487-4691-a92b-e38aaf621c47
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421678864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.2421678864 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1839930405
Short name	T133
Test name
Test status
Simulation time	83939080 ps
CPU time	1.53 seconds
Started	Mar 14 01:10:44 PM PDT 24
Finished	Mar 14 01:10:46 PM PDT 24
Peak memory	215428 kb
Host	smart-f2d9bea8-e786-4f66-8a56-f7d2609ecf53
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839930405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma c_shadow_reg_errors_with_csr_rw.1839930405 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.3455836736
Short name	T181
Test name
Test status
Simulation time	628448779 ps
CPU time	2.02 seconds
Started	Mar 14 01:10:46 PM PDT 24
Finished	Mar 14 01:10:48 PM PDT 24
Peak memory	215060 kb
Host	smart-266fe59f-3d17-4a70-a9a6-eae076fc806f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455836736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3455836736 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.237432557
Short name	T79
Test name
Test status
Simulation time	83873508 ps
CPU time	2.52 seconds
Started	Mar 14 01:10:44 PM PDT 24
Finished	Mar 14 01:10:47 PM PDT 24
Peak memory	214992 kb
Host	smart-786181df-3991-4844-8156-2214d723d56a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237432557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.23743 2557 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4032991147
Short name	T18
Test name
Test status
Simulation time	91135909 ps
CPU time	1.62 seconds
Started	Mar 14 01:10:53 PM PDT 24
Finished	Mar 14 01:10:54 PM PDT 24
Peak memory	223192 kb
Host	smart-4460878a-20af-4f5a-bd87-970ac0230b29
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032991147 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.4032991147 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.2238959666
Short name	T51
Test name
Test status
Simulation time	18660619 ps
CPU time	1 seconds
Started	Mar 14 01:10:53 PM PDT 24
Finished	Mar 14 01:10:54 PM PDT 24
Peak memory	206804 kb
Host	smart-59c50b0b-fd8c-494f-8236-37061d9c26fa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238959666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.2238959666 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.1172912240
Short name	T46
Test name
Test status
Simulation time	18055416 ps
CPU time	0.82 seconds
Started	Mar 14 01:10:54 PM PDT 24
Finished	Mar 14 01:10:55 PM PDT 24
Peak memory	206636 kb
Host	smart-d392e28a-4dc2-4f1d-95b7-09a07d18a421
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172912240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1172912240 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3089597742
Short name	T140
Test name
Test status
Simulation time	484681100 ps
CPU time	2.45 seconds
Started	Mar 14 01:10:51 PM PDT 24
Finished	Mar 14 01:10:54 PM PDT 24
Peak memory	214888 kb
Host	smart-b5f54067-9556-4dce-af5f-f1596dcce3c5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089597742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.3089597742 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2879274537
Short name	T32
Test name
Test status
Simulation time	157002131 ps
CPU time	1.22 seconds
Started	Mar 14 01:10:53 PM PDT 24
Finished	Mar 14 01:10:55 PM PDT 24
Peak memory	215468 kb
Host	smart-72b601b8-e854-43b2-87cc-fd21a51236a1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879274537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg _errors.2879274537 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2487134671
Short name	T129
Test name
Test status
Simulation time	153170108 ps
CPU time	2.45 seconds
Started	Mar 14 01:10:52 PM PDT 24
Finished	Mar 14 01:10:55 PM PDT 24
Peak memory	215432 kb
Host	smart-6a04e756-06a5-41d3-bb62-0c9a339befa5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487134671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma c_shadow_reg_errors_with_csr_rw.2487134671 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.2694853224
Short name	T63
Test name
Test status
Simulation time	686099613 ps
CPU time	3.08 seconds
Started	Mar 14 01:10:55 PM PDT 24
Finished	Mar 14 01:10:59 PM PDT 24
Peak memory	215108 kb
Host	smart-2867f78c-ade4-43a8-b8f1-64f472ddfbca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694853224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2694853224 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.353706160
Short name	T78
Test name
Test status
Simulation time	203247867 ps
CPU time	4.01 seconds
Started	Mar 14 01:10:58 PM PDT 24
Finished	Mar 14 01:11:02 PM PDT 24
Peak memory	206988 kb
Host	smart-677f0fe7-593a-4d73-8c5b-212f71c28bef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353706160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.35370 6160 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2710264402
Short name	T191
Test name
Test status
Simulation time	59519549 ps
CPU time	1.86 seconds
Started	Mar 14 01:11:14 PM PDT 24
Finished	Mar 14 01:11:16 PM PDT 24
Peak memory	214952 kb
Host	smart-cd9b4d2a-8c5c-4172-a589-5d14f7bbd9d8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710264402 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.2710264402 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.484215605
Short name	T117
Test name
Test status
Simulation time	27274879 ps
CPU time	0.97 seconds
Started	Mar 14 01:11:11 PM PDT 24
Finished	Mar 14 01:11:13 PM PDT 24
Peak memory	206656 kb
Host	smart-f1650351-1eef-4dc1-b062-5b448151fd81
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484215605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.484215605 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.3591662666
Short name	T91
Test name
Test status
Simulation time	44892048 ps
CPU time	0.83 seconds
Started	Mar 14 01:11:14 PM PDT 24
Finished	Mar 14 01:11:15 PM PDT 24
Peak memory	206672 kb
Host	smart-ce188077-4d0a-473d-a2ad-435543f19ec7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591662666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3591662666 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2788577546
Short name	T178
Test name
Test status
Simulation time	50819729 ps
CPU time	1.65 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:15 PM PDT 24
Peak memory	215028 kb
Host	smart-63d8ce97-96fd-451c-9798-77deb4153064
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788577546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.2788577546 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1234792230
Short name	T84
Test name
Test status
Simulation time	61258568 ps
CPU time	1.14 seconds
Started	Mar 14 01:10:58 PM PDT 24
Finished	Mar 14 01:10:59 PM PDT 24
Peak memory	215468 kb
Host	smart-bd968a17-57ef-4939-8846-7d5f6ee18463
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234792230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.1234792230 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1768458274
Short name	T47
Test name
Test status
Simulation time	232258242 ps
CPU time	2.77 seconds
Started	Mar 14 01:11:12 PM PDT 24
Finished	Mar 14 01:11:15 PM PDT 24
Peak memory	215444 kb
Host	smart-048647da-73ea-448e-b1ba-39e5ee27a89c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768458274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.1768458274 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.954136036
Short name	T171
Test name
Test status
Simulation time	57313087 ps
CPU time	1.59 seconds
Started	Mar 14 01:11:14 PM PDT 24
Finished	Mar 14 01:11:16 PM PDT 24
Peak memory	215008 kb
Host	smart-9e31637f-cec4-490c-8567-7caf112202e5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954136036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.954136036 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3578819308
Short name	T137
Test name
Test status
Simulation time	101432117 ps
CPU time	2.92 seconds
Started	Mar 14 01:11:11 PM PDT 24
Finished	Mar 14 01:11:14 PM PDT 24
Peak memory	214960 kb
Host	smart-ce939e9f-fb5d-494a-b322-fc9af5e555d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578819308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3578 819308 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3158378339
Short name	T188
Test name
Test status
Simulation time	91440877 ps
CPU time	1.67 seconds
Started	Mar 14 01:11:10 PM PDT 24
Finished	Mar 14 01:11:12 PM PDT 24
Peak memory	215016 kb
Host	smart-65174a76-2de5-43b0-a60d-45abc7d749f5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158378339 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3158378339 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.4032102139
Short name	T124
Test name
Test status
Simulation time	138601439 ps
CPU time	0.92 seconds
Started	Mar 14 01:11:11 PM PDT 24
Finished	Mar 14 01:11:12 PM PDT 24
Peak memory	206668 kb
Host	smart-3d6d50b4-f361-4c78-a692-bbbd9c243c82
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032102139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.4032102139 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2426948219
Short name	T214
Test name
Test status
Simulation time	157839288 ps
CPU time	1.59 seconds
Started	Mar 14 01:11:11 PM PDT 24
Finished	Mar 14 01:11:13 PM PDT 24
Peak memory	214936 kb
Host	smart-d1da7ac6-bc02-49ed-baa4-af1220d3ac63
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426948219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs r_outstanding.2426948219 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1517916949
Short name	T58
Test name
Test status
Simulation time	90086878 ps
CPU time	1.39 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:14 PM PDT 24
Peak memory	215468 kb
Host	smart-936097ea-0520-4f56-bf73-0d08d80f66fa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517916949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.1517916949 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1644603952
Short name	T202
Test name
Test status
Simulation time	40119624 ps
CPU time	1.7 seconds
Started	Mar 14 01:11:14 PM PDT 24
Finished	Mar 14 01:11:16 PM PDT 24
Peak memory	215356 kb
Host	smart-dbcce50c-51a6-4929-8c9c-cee8e40e05a0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644603952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma c_shadow_reg_errors_with_csr_rw.1644603952 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.4246702496
Short name	T62
Test name
Test status
Simulation time	57417030 ps
CPU time	2.63 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:16 PM PDT 24
Peak memory	215084 kb
Host	smart-0c108616-c68c-4a1b-a53b-05cb361af491
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246702496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.4246702496 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.805362100
Short name	T195
Test name
Test status
Simulation time	1030497667 ps
CPU time	4.79 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:39 PM PDT 24
Peak memory	206828 kb
Host	smart-c087d2a4-2438-43ca-8d49-68ea3876e471
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805362100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.80536210 0 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.4217309735
Short name	T31
Test name
Test status
Simulation time	295818000 ps
CPU time	8.28 seconds
Started	Mar 14 01:10:31 PM PDT 24
Finished	Mar 14 01:10:42 PM PDT 24
Peak memory	206636 kb
Host	smart-98feb71d-2bc4-4f43-a12a-8883946f9636
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217309735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.4217309 735 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1005546258
Short name	T41
Test name
Test status
Simulation time	246926263 ps
CPU time	1.15 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	214960 kb
Host	smart-a6df03eb-274e-4946-afa3-8c322b40f106
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005546258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1005546 258 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.684098406
Short name	T169
Test name
Test status
Simulation time	160118115 ps
CPU time	2.36 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	223236 kb
Host	smart-f0714399-6066-494e-87f7-b73f860036a6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684098406 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.684098406 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.1979922663
Short name	T187
Test name
Test status
Simulation time	29066952 ps
CPU time	1.13 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:34 PM PDT 24
Peak memory	206732 kb
Host	smart-17023109-e97f-43dd-9fc6-11a5d7ded445
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979922663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1979922663 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.611357791
Short name	T116
Test name
Test status
Simulation time	24987657 ps
CPU time	0.77 seconds
Started	Mar 14 01:10:27 PM PDT 24
Finished	Mar 14 01:10:28 PM PDT 24
Peak memory	206644 kb
Host	smart-1adb744f-7f04-4cfd-823d-4aaefb95dcb0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611357791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.611357791 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3940776448
Short name	T37
Test name
Test status
Simulation time	108609905 ps
CPU time	1.28 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	214992 kb
Host	smart-3a376991-3903-4607-b646-e5357d8a8716
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940776448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.3940776448 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.340205847
Short name	T197
Test name
Test status
Simulation time	18158377 ps
CPU time	0.72 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	206628 kb
Host	smart-14c9e020-ef06-4a9a-b8c1-457c5891e242
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340205847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.340205847 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.971411389
Short name	T154
Test name
Test status
Simulation time	85077098 ps
CPU time	1.48 seconds
Started	Mar 14 01:10:31 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	214952 kb
Host	smart-526c9052-8811-48f4-8cd6-573853ba3237
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971411389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_ outstanding.971411389 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2268312608
Short name	T200
Test name
Test status
Simulation time	65727649 ps
CPU time	1.45 seconds
Started	Mar 14 01:10:28 PM PDT 24
Finished	Mar 14 01:10:32 PM PDT 24
Peak memory	215320 kb
Host	smart-2e49455b-7cfa-4f5f-bf1d-33fbf1906dfa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268312608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_ errors.2268312608 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.4086289117
Short name	T156
Test name
Test status
Simulation time	121143687 ps
CPU time	1.99 seconds
Started	Mar 14 01:10:35 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	223612 kb
Host	smart-c3cec701-e5ab-4acf-8c4e-a960e465924d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086289117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac _shadow_reg_errors_with_csr_rw.4086289117 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.4110781560
Short name	T64
Test name
Test status
Simulation time	57275186 ps
CPU time	1.71 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	215064 kb
Host	smart-e81b38a4-4ca7-4cc2-84fe-27087de7ca28
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110781560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.4110781560 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.894350639
Short name	T26
Test name
Test status
Simulation time	139075883 ps
CPU time	4.01 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:39 PM PDT 24
Peak memory	206688 kb
Host	smart-fb17d273-85c5-4138-9e7f-e1cbd5666273
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894350639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.894350 639 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.92754333
Short name	T158
Test name
Test status
Simulation time	37729941 ps
CPU time	0.78 seconds
Started	Mar 14 01:11:12 PM PDT 24
Finished	Mar 14 01:11:12 PM PDT 24
Peak memory	206680 kb
Host	smart-0837c5f0-ffc1-4412-be17-12b911a8ee83
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92754333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.92754333 +enable_mas king=0 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3127739748
Short name	T103
Test name
Test status
Simulation time	20166685 ps
CPU time	0.81 seconds
Started	Mar 14 01:11:10 PM PDT 24
Finished	Mar 14 01:11:11 PM PDT 24
Peak memory	206632 kb
Host	smart-cbe104bf-c8d6-436e-8bfe-8742e5fa690e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127739748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3127739748 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.2317354502
Short name	T105
Test name
Test status
Simulation time	31118690 ps
CPU time	0.79 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:14 PM PDT 24
Peak memory	206700 kb
Host	smart-8024fccf-93a3-43be-8cbe-8f712038a57e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317354502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2317354502 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.250574395
Short name	T147
Test name
Test status
Simulation time	25758600 ps
CPU time	0.82 seconds
Started	Mar 14 01:11:14 PM PDT 24
Finished	Mar 14 01:11:15 PM PDT 24
Peak memory	206720 kb
Host	smart-277dd73c-b3ce-466a-b762-6d86d7751393
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250574395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.250574395 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.1341753112
Short name	T90
Test name
Test status
Simulation time	41061095 ps
CPU time	0.76 seconds
Started	Mar 14 01:11:15 PM PDT 24
Finished	Mar 14 01:11:16 PM PDT 24
Peak memory	206604 kb
Host	smart-0969d57c-d543-4b60-abff-714f2a5f6d8c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341753112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1341753112 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.2982757762
Short name	T189
Test name
Test status
Simulation time	169744493 ps
CPU time	0.78 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:14 PM PDT 24
Peak memory	206604 kb
Host	smart-38bd730b-0e92-470e-b646-504bfd4fb911
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982757762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2982757762 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.3333104735
Short name	T87
Test name
Test status
Simulation time	10693584 ps
CPU time	0.75 seconds
Started	Mar 14 01:11:11 PM PDT 24
Finished	Mar 14 01:11:12 PM PDT 24
Peak memory	206608 kb
Host	smart-36ada3fc-0199-421b-a6ef-695f98639886
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333104735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3333104735 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.99952041
Short name	T161
Test name
Test status
Simulation time	30005367 ps
CPU time	0.73 seconds
Started	Mar 14 01:11:10 PM PDT 24
Finished	Mar 14 01:11:11 PM PDT 24
Peak memory	206592 kb
Host	smart-b54b8ae8-2269-4b4e-87ea-f67ee94f82a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99952041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.99952041 +enable_mas king=0 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.1391595437
Short name	T190
Test name
Test status
Simulation time	15436231 ps
CPU time	0.78 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:14 PM PDT 24
Peak memory	206700 kb
Host	smart-183d5dea-f4e0-4873-aefe-3c511247838d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391595437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1391595437 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.2710699037
Short name	T141
Test name
Test status
Simulation time	55252765 ps
CPU time	0.83 seconds
Started	Mar 14 01:11:14 PM PDT 24
Finished	Mar 14 01:11:15 PM PDT 24
Peak memory	206672 kb
Host	smart-e6d8d547-9e5a-40cd-b318-538a499f0f99
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710699037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2710699037 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3843767744
Short name	T11
Test name
Test status
Simulation time	1085356194 ps
CPU time	5.7 seconds
Started	Mar 14 01:10:29 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	206780 kb
Host	smart-5559fcb3-69b9-4f50-8fd5-6449b9eaf717
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843767744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3843767 744 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2317688857
Short name	T128
Test name
Test status
Simulation time	3847490427 ps
CPU time	17.98 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:51 PM PDT 24
Peak memory	206836 kb
Host	smart-e8822aea-b12c-4c07-9902-d056493adf58
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317688857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2317688 857 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2545991719
Short name	T40
Test name
Test status
Simulation time	22289459 ps
CPU time	0.96 seconds
Started	Mar 14 01:10:31 PM PDT 24
Finished	Mar 14 01:10:34 PM PDT 24
Peak memory	206624 kb
Host	smart-76db02d1-73dd-4a24-80a2-80e6c500d1ac
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545991719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2545991 719 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2770409990
Short name	T107
Test name
Test status
Simulation time	237502825 ps
CPU time	2.16 seconds
Started	Mar 14 01:10:35 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	223216 kb
Host	smart-3a066f08-8b5f-434b-baf9-5d60dc34387d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770409990 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.2770409990 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.1426924980
Short name	T54
Test name
Test status
Simulation time	315128273 ps
CPU time	1.09 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	206816 kb
Host	smart-068ee774-0bab-4b40-a5a3-998a9a5c704e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426924980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1426924980 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.2918454360
Short name	T118
Test name
Test status
Simulation time	19492754 ps
CPU time	0.79 seconds
Started	Mar 14 01:10:28 PM PDT 24
Finished	Mar 14 01:10:31 PM PDT 24
Peak memory	206660 kb
Host	smart-70f8c159-5b97-4a69-aedc-77d0eede856c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918454360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2918454360 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2161365756
Short name	T39
Test name
Test status
Simulation time	148888363 ps
CPU time	1.55 seconds
Started	Mar 14 01:10:28 PM PDT 24
Finished	Mar 14 01:10:33 PM PDT 24
Peak memory	215020 kb
Host	smart-61f02bf5-6727-4501-be60-c553db04ee22
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161365756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.2161365756 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.1409935844
Short name	T175
Test name
Test status
Simulation time	17660902 ps
CPU time	0.77 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:33 PM PDT 24
Peak memory	206692 kb
Host	smart-b8d7c301-c9bc-49f6-b3fa-158de040ef9e
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409935844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1409935844 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.661079909
Short name	T101
Test name
Test status
Simulation time	92990605 ps
CPU time	2.39 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	215112 kb
Host	smart-8924bea2-a710-4d3f-8673-349965580cf0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661079909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_ outstanding.661079909 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.161896824
Short name	T85
Test name
Test status
Simulation time	36982639 ps
CPU time	1.18 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	215464 kb
Host	smart-a5f18d25-7c1d-43b5-8aca-0377ed496691
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161896824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e rrors.161896824 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.883383553
Short name	T132
Test name
Test status
Simulation time	64682643 ps
CPU time	1.85 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	222816 kb
Host	smart-6d4fe57c-3fc2-49fe-b105-39e43f7c1507
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883383553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_ shadow_reg_errors_with_csr_rw.883383553 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.22785146
Short name	T42
Test name
Test status
Simulation time	69275029 ps
CPU time	2.35 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	215140 kb
Host	smart-ff89ac7b-29d2-49a7-8846-8d2e13d3adb3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22785146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.22785146 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2613619821
Short name	T25
Test name
Test status
Simulation time	96665478 ps
CPU time	4 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:38 PM PDT 24
Peak memory	214888 kb
Host	smart-4820a0cb-9ec9-432a-adb6-c31e759b6b9a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613619821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.26136 19821 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.2249274846
Short name	T126
Test name
Test status
Simulation time	49189008 ps
CPU time	0.74 seconds
Started	Mar 14 01:11:14 PM PDT 24
Finished	Mar 14 01:11:15 PM PDT 24
Peak memory	206580 kb
Host	smart-aaea724c-50f8-474f-b6f4-1b59a7d8668c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249274846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2249274846 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.3461924806
Short name	T139
Test name
Test status
Simulation time	19640145 ps
CPU time	0.74 seconds
Started	Mar 14 01:11:10 PM PDT 24
Finished	Mar 14 01:11:11 PM PDT 24
Peak memory	206636 kb
Host	smart-2e022571-a46a-4e82-b48e-b249b7b73751
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461924806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3461924806 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2538465811
Short name	T74
Test name
Test status
Simulation time	11265525 ps
CPU time	0.91 seconds
Started	Mar 14 01:11:14 PM PDT 24
Finished	Mar 14 01:11:15 PM PDT 24
Peak memory	206540 kb
Host	smart-05a5189d-4291-43a2-ac6a-63c58ed9fc13
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538465811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2538465811 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.3308479103
Short name	T127
Test name
Test status
Simulation time	17927943 ps
CPU time	0.85 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:14 PM PDT 24
Peak memory	206688 kb
Host	smart-19fd83eb-fa8e-4d55-a1a0-a31764cc5e6e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308479103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3308479103 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.153889868
Short name	T122
Test name
Test status
Simulation time	12936806 ps
CPU time	0.77 seconds
Started	Mar 14 01:11:21 PM PDT 24
Finished	Mar 14 01:11:22 PM PDT 24
Peak memory	206708 kb
Host	smart-58297e73-7f18-4549-b2b4-3f0b1e3ac2cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153889868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.153889868 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.342202709
Short name	T184
Test name
Test status
Simulation time	15889103 ps
CPU time	0.79 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:14 PM PDT 24
Peak memory	206708 kb
Host	smart-54bd0d56-0d0c-436e-a4b2-589bdaa3e43e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342202709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.342202709 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.1993895111
Short name	T88
Test name
Test status
Simulation time	13030908 ps
CPU time	0.8 seconds
Started	Mar 14 01:11:15 PM PDT 24
Finished	Mar 14 01:11:16 PM PDT 24
Peak memory	206604 kb
Host	smart-1832d01d-d7e8-43d1-a2c5-60607bb98287
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993895111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1993895111 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.783363108
Short name	T104
Test name
Test status
Simulation time	27598900 ps
CPU time	0.75 seconds
Started	Mar 14 01:11:10 PM PDT 24
Finished	Mar 14 01:11:11 PM PDT 24
Peak memory	206624 kb
Host	smart-d8905779-1e31-44bf-89b2-54f4a6971a32
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783363108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.783363108 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.2874326184
Short name	T215
Test name
Test status
Simulation time	25975534 ps
CPU time	0.8 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:14 PM PDT 24
Peak memory	206684 kb
Host	smart-bad0d555-02f0-4be2-a24d-13600704de4e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874326184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2874326184 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.524736417
Short name	T9
Test name
Test status
Simulation time	18578703 ps
CPU time	0.76 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:14 PM PDT 24
Peak memory	206604 kb
Host	smart-2a65603f-73c3-461d-843f-dea33534f381
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524736417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.524736417 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2727680424
Short name	T121
Test name
Test status
Simulation time	809930268 ps
CPU time	5.01 seconds
Started	Mar 14 01:10:29 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	206800 kb
Host	smart-d7f007d9-e75d-4235-978d-5de213f4f93a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727680424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2727680 424 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.716451044
Short name	T207
Test name
Test status
Simulation time	516414898 ps
CPU time	9.49 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:43 PM PDT 24
Peak memory	206708 kb
Host	smart-f0135247-b02a-4cf4-bd8a-cf69818c2b67
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716451044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.71645104 4 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.4107834059
Short name	T21
Test name
Test status
Simulation time	390744048 ps
CPU time	1.23 seconds
Started	Mar 14 01:10:27 PM PDT 24
Finished	Mar 14 01:10:30 PM PDT 24
Peak memory	206752 kb
Host	smart-f14653e5-0f5b-431d-80f9-de7ba2b2c213
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107834059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.4107834 059 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2990339272
Short name	T136
Test name
Test status
Simulation time	29529982 ps
CPU time	1.72 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	223092 kb
Host	smart-75c8a707-4df3-43db-a894-adc6307a5ad9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990339272 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2990339272 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.970126826
Short name	T35
Test name
Test status
Simulation time	28056324 ps
CPU time	1.07 seconds
Started	Mar 14 01:10:27 PM PDT 24
Finished	Mar 14 01:10:30 PM PDT 24
Peak memory	214932 kb
Host	smart-3a04d4ec-092c-4825-87b0-a03b1128e88c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970126826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.970126826 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3547554940
Short name	T168
Test name
Test status
Simulation time	11077412 ps
CPU time	0.72 seconds
Started	Mar 14 01:10:31 PM PDT 24
Finished	Mar 14 01:10:34 PM PDT 24
Peak memory	206708 kb
Host	smart-36abb6b4-229b-439f-ab8c-ebebf7c0aa3c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547554940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3547554940 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2878176960
Short name	T38
Test name
Test status
Simulation time	62193430 ps
CPU time	1.12 seconds
Started	Mar 14 01:10:28 PM PDT 24
Finished	Mar 14 01:10:31 PM PDT 24
Peak memory	214900 kb
Host	smart-c44752b1-68b3-418f-a1b6-31a9f557abc0
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878176960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.2878176960 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.2560872452
Short name	T86
Test name
Test status
Simulation time	10521680 ps
CPU time	0.73 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:34 PM PDT 24
Peak memory	206692 kb
Host	smart-5f77eb45-2d73-4c20-96ad-21a0191fba63
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560872452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2560872452 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1009628807
Short name	T102
Test name
Test status
Simulation time	214143587 ps
CPU time	1.56 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	214992 kb
Host	smart-bf965a76-3807-4914-a3e7-b6da392cdb72
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009628807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr _outstanding.1009628807 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3972651552
Short name	T59
Test name
Test status
Simulation time	33045192 ps
CPU time	1.17 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	215328 kb
Host	smart-de007394-9e8a-4113-b209-3b4149856107
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972651552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.3972651552 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.124337392
Short name	T14
Test name
Test status
Simulation time	183811843 ps
CPU time	2.97 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	215108 kb
Host	smart-04b56926-9cc9-4ebe-b78b-6a9a59427158
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124337392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.124337392 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1328720138
Short name	T24
Test name
Test status
Simulation time	123863622 ps
CPU time	2.86 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	214980 kb
Host	smart-cc8d08de-60a2-4135-8b00-e1f868eff4ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328720138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.13287 20138 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.3837163623
Short name	T96
Test name
Test status
Simulation time	20905418 ps
CPU time	0.74 seconds
Started	Mar 14 01:11:12 PM PDT 24
Finished	Mar 14 01:11:12 PM PDT 24
Peak memory	206660 kb
Host	smart-671fc8d0-1711-4569-8e5f-cb8e3e161bd9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837163623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3837163623 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.1590769940
Short name	T192
Test name
Test status
Simulation time	18618337 ps
CPU time	0.83 seconds
Started	Mar 14 01:11:12 PM PDT 24
Finished	Mar 14 01:11:13 PM PDT 24
Peak memory	206648 kb
Host	smart-e609aa08-b366-4626-a2c4-8cc4a9ad8739
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590769940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1590769940 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.3747269781
Short name	T212
Test name
Test status
Simulation time	42062916 ps
CPU time	0.78 seconds
Started	Mar 14 01:11:10 PM PDT 24
Finished	Mar 14 01:11:11 PM PDT 24
Peak memory	206608 kb
Host	smart-6301fea7-d12f-49f7-9f6d-aa1d66e08dea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747269781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3747269781 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.1718007829
Short name	T125
Test name
Test status
Simulation time	56241063 ps
CPU time	0.77 seconds
Started	Mar 14 01:11:09 PM PDT 24
Finished	Mar 14 01:11:10 PM PDT 24
Peak memory	206580 kb
Host	smart-67583dda-4d38-450d-9200-2dda6eab68b3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718007829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1718007829 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.2226210587
Short name	T33
Test name
Test status
Simulation time	21080150 ps
CPU time	0.78 seconds
Started	Mar 14 01:11:11 PM PDT 24
Finished	Mar 14 01:11:11 PM PDT 24
Peak memory	206676 kb
Host	smart-a87d3ff0-98d0-40e6-8ec9-644518c4bea6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226210587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2226210587 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.1818934320
Short name	T110
Test name
Test status
Simulation time	33037968 ps
CPU time	0.78 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:13 PM PDT 24
Peak memory	206656 kb
Host	smart-cf7f12d0-5b0e-45a1-961e-6958951765e0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818934320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1818934320 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.2524221205
Short name	T123
Test name
Test status
Simulation time	12296149 ps
CPU time	0.78 seconds
Started	Mar 14 01:11:09 PM PDT 24
Finished	Mar 14 01:11:10 PM PDT 24
Peak memory	206652 kb
Host	smart-fdee4f6e-1b7d-4d1d-b04b-84960a9eeac2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524221205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2524221205 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.4049707131
Short name	T135
Test name
Test status
Simulation time	18291712 ps
CPU time	0.76 seconds
Started	Mar 14 01:11:13 PM PDT 24
Finished	Mar 14 01:11:13 PM PDT 24
Peak memory	206700 kb
Host	smart-b9726a72-f252-4c45-a586-a92d58b99e2c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049707131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.4049707131 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.506668363
Short name	T144
Test name
Test status
Simulation time	21530547 ps
CPU time	0.77 seconds
Started	Mar 14 01:11:14 PM PDT 24
Finished	Mar 14 01:11:15 PM PDT 24
Peak memory	206676 kb
Host	smart-a8c7ac41-2999-4ff1-b3be-56a162688123
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506668363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.506668363 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.232095241
Short name	T114
Test name
Test status
Simulation time	13905543 ps
CPU time	0.77 seconds
Started	Mar 14 01:11:14 PM PDT 24
Finished	Mar 14 01:11:15 PM PDT 24
Peak memory	206604 kb
Host	smart-d242c104-5e6b-4d62-bc21-d8c21b12ebee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232095241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.232095241 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3337010238
Short name	T93
Test name
Test status
Simulation time	158450817 ps
CPU time	1.66 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	215088 kb
Host	smart-b2136c78-231a-4ca5-813e-79f1d36eed77
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337010238 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3337010238 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.4207944446
Short name	T138
Test name
Test status
Simulation time	20954568 ps
CPU time	1.08 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	206688 kb
Host	smart-eed5c5f7-2635-4a64-bb7d-a4fb68f6143c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207944446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.4207944446 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.3016838238
Short name	T155
Test name
Test status
Simulation time	15179810 ps
CPU time	0.79 seconds
Started	Mar 14 01:10:35 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	206672 kb
Host	smart-2e194169-594c-4a80-b374-a725cf49459e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016838238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3016838238 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3149294123
Short name	T50
Test name
Test status
Simulation time	48005579 ps
CPU time	1.34 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:34 PM PDT 24
Peak memory	215084 kb
Host	smart-ae902a3d-e656-4231-a686-3afe19b0c95e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149294123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.3149294123 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3758234550
Short name	T57
Test name
Test status
Simulation time	62459383 ps
CPU time	1.25 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	215444 kb
Host	smart-eb091c15-4722-42b2-bd66-8aca5b92703e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758234550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_ errors.3758234550 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1449734592
Short name	T27
Test name
Test status
Simulation time	102049298 ps
CPU time	2.22 seconds
Started	Mar 14 01:10:31 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	214960 kb
Host	smart-addf9463-9683-47c1-b66d-b4864dd4f491
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449734592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.1449734592 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.338793852
Short name	T19
Test name
Test status
Simulation time	50853628 ps
CPU time	1.47 seconds
Started	Mar 14 01:10:27 PM PDT 24
Finished	Mar 14 01:10:31 PM PDT 24
Peak memory	215032 kb
Host	smart-cab77f9f-37e1-414b-8226-60687475f6ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338793852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.338793852 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2051860962
Short name	T65
Test name
Test status
Simulation time	31736825 ps
CPU time	2.18 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:34 PM PDT 24
Peak memory	223204 kb
Host	smart-55e42733-8981-4f53-908b-a9ed15161dc2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051860962 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2051860962 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.3429991054
Short name	T89
Test name
Test status
Simulation time	61207868 ps
CPU time	0.9 seconds
Started	Mar 14 01:10:27 PM PDT 24
Finished	Mar 14 01:10:29 PM PDT 24
Peak memory	206636 kb
Host	smart-aa4cc331-1136-4449-9904-bb1aaefd5501
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429991054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3429991054 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.4289773143
Short name	T199
Test name
Test status
Simulation time	11135830 ps
CPU time	0.75 seconds
Started	Mar 14 01:10:31 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	206580 kb
Host	smart-09890f82-a90e-4747-8fc5-64c0e9fad614
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289773143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.4289773143 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2965130280
Short name	T145
Test name
Test status
Simulation time	211234330 ps
CPU time	2.14 seconds
Started	Mar 14 01:10:31 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	215004 kb
Host	smart-baaf927a-2b4c-4680-aa40-36bd06f5ece8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965130280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr _outstanding.2965130280 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1937216867
Short name	T45
Test name
Test status
Simulation time	131553101 ps
CPU time	0.95 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	215316 kb
Host	smart-d6bf6913-be55-4445-a64d-6aaf6d1fae1d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937216867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.1937216867 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3958380491
Short name	T112
Test name
Test status
Simulation time	135224194 ps
CPU time	1.56 seconds
Started	Mar 14 01:10:31 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	215408 kb
Host	smart-128df72f-7d84-4bc4-b2b6-fa0629e218a0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958380491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac _shadow_reg_errors_with_csr_rw.3958380491 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.2638832012
Short name	T61
Test name
Test status
Simulation time	299768670 ps
CPU time	1.31 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	215084 kb
Host	smart-81e2aebc-e4f4-4672-8fdb-ba0ede7bdb6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638832012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2638832012 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.159144757
Short name	T198
Test name
Test status
Simulation time	165193807 ps
CPU time	2.73 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	214948 kb
Host	smart-8f819101-ac07-4eb2-94a0-4a833cb5eadc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159144757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.159144 757 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3968179230
Short name	T149
Test name
Test status
Simulation time	48760934 ps
CPU time	1.85 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	215000 kb
Host	smart-d44db909-6562-4293-852f-7c8d2a7e208b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968179230 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3968179230 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.2242650090
Short name	T166
Test name
Test status
Simulation time	19031530 ps
CPU time	0.92 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	206648 kb
Host	smart-0f899622-e6c1-43ba-a14d-177b130cda32
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242650090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2242650090 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.4193934736
Short name	T71
Test name
Test status
Simulation time	103968858 ps
CPU time	0.73 seconds
Started	Mar 14 01:10:28 PM PDT 24
Finished	Mar 14 01:10:30 PM PDT 24
Peak memory	206680 kb
Host	smart-c9e31652-55f7-47c2-a619-4abd8ae736cc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193934736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.4193934736 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1407175158
Short name	T179
Test name
Test status
Simulation time	104996323 ps
CPU time	1.72 seconds
Started	Mar 14 01:10:50 PM PDT 24
Finished	Mar 14 01:10:53 PM PDT 24
Peak memory	215088 kb
Host	smart-7c293569-d88b-46d9-9284-fac431fef888
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407175158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr _outstanding.1407175158 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1934687777
Short name	T152
Test name
Test status
Simulation time	61755030 ps
CPU time	1.25 seconds
Started	Mar 14 01:10:31 PM PDT 24
Finished	Mar 14 01:10:34 PM PDT 24
Peak memory	215452 kb
Host	smart-b2c55ed2-61e0-47f6-b968-e574272b05e7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934687777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.1934687777 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2683274622
Short name	T3
Test name
Test status
Simulation time	188419547 ps
CPU time	2.98 seconds
Started	Mar 14 01:10:28 PM PDT 24
Finished	Mar 14 01:10:32 PM PDT 24
Peak memory	215412 kb
Host	smart-526bcbbc-454b-4fe6-8de8-0d21968b9773
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683274622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.2683274622 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.1724663934
Short name	T66
Test name
Test status
Simulation time	190831238 ps
CPU time	1.81 seconds
Started	Mar 14 01:10:31 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	214980 kb
Host	smart-c2d9f00a-5433-42ed-b3f1-12fe6610f917
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724663934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1724663934 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.513751308
Short name	T80
Test name
Test status
Simulation time	808651731 ps
CPU time	4.91 seconds
Started	Mar 14 01:10:30 PM PDT 24
Finished	Mar 14 01:10:38 PM PDT 24
Peak memory	214884 kb
Host	smart-99f0853f-cd1f-4a32-b791-5ddbbf5ed15d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513751308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.513751 308 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.994252139
Short name	T146
Test name
Test status
Simulation time	100758645 ps
CPU time	2.21 seconds
Started	Mar 14 01:10:35 PM PDT 24
Finished	Mar 14 01:10:38 PM PDT 24
Peak memory	223196 kb
Host	smart-b39e1f24-cbd4-4ab1-a400-58154ef45e95
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994252139 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.994252139 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.1673171222
Short name	T172
Test name
Test status
Simulation time	75581340 ps
CPU time	0.94 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	206540 kb
Host	smart-a15410d8-e01a-4660-9eb2-0725a373939c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673171222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1673171222 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.1792619804
Short name	T7
Test name
Test status
Simulation time	50671957 ps
CPU time	0.79 seconds
Started	Mar 14 01:10:35 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	206572 kb
Host	smart-0395f27d-b28b-46db-8fa5-2b99ce20a303
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792619804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1792619804 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2375109116
Short name	T28
Test name
Test status
Simulation time	622608684 ps
CPU time	2.91 seconds
Started	Mar 14 01:10:35 PM PDT 24
Finished	Mar 14 01:10:38 PM PDT 24
Peak memory	215092 kb
Host	smart-811aeb63-e6d9-4634-a4bc-7bc37d553c3a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375109116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr _outstanding.2375109116 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.542799733
Short name	T163
Test name
Test status
Simulation time	55045387 ps
CPU time	1.36 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	207224 kb
Host	smart-e9351414-4287-4262-971f-43292589e300
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542799733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_e rrors.542799733 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.977110832
Short name	T170
Test name
Test status
Simulation time	126123562 ps
CPU time	1.76 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	214956 kb
Host	smart-5ccf6d27-b15d-4f66-936b-dbfab467d650
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977110832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_ shadow_reg_errors_with_csr_rw.977110832 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.3186633051
Short name	T44
Test name
Test status
Simulation time	186892489 ps
CPU time	1.67 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	215016 kb
Host	smart-adfe115e-2744-4e2a-88f1-b925187cdf80
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186633051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3186633051 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2545820495
Short name	T83
Test name
Test status
Simulation time	99418087 ps
CPU time	2.83 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	206712 kb
Host	smart-862fcf6d-7a6a-4db8-b030-3f554ae35d04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545820495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.25458 20495 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2945227057
Short name	T20
Test name
Test status
Simulation time	31322925 ps
CPU time	1.71 seconds
Started	Mar 14 01:10:35 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	215056 kb
Host	smart-83641bd1-33e0-4e3f-b127-6cbc48193f9d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945227057 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2945227057 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.1119158352
Short name	T186
Test name
Test status
Simulation time	27649692 ps
CPU time	0.96 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	206608 kb
Host	smart-2df30c38-ba6f-456e-a89a-02f4fb5293dc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119158352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1119158352 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.24285191
Short name	T73
Test name
Test status
Simulation time	101503875 ps
CPU time	0.77 seconds
Started	Mar 14 01:10:33 PM PDT 24
Finished	Mar 14 01:10:35 PM PDT 24
Peak memory	206672 kb
Host	smart-5e915a90-72eb-4668-a6bf-c189be9f0cd4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24285191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.24285191 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3498748387
Short name	T204
Test name
Test status
Simulation time	128369512 ps
CPU time	2.16 seconds
Started	Mar 14 01:10:35 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	215008 kb
Host	smart-5e35e088-b5b6-4557-859f-4d4d931520c5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498748387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr _outstanding.3498748387 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.4103761770
Short name	T131
Test name
Test status
Simulation time	212991508 ps
CPU time	1.19 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:36 PM PDT 24
Peak memory	215420 kb
Host	smart-913e415e-62d1-4786-9662-9bb67a95f61c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103761770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.4103761770 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3069051434
Short name	T176
Test name
Test status
Simulation time	194962561 ps
CPU time	2.54 seconds
Started	Mar 14 01:10:34 PM PDT 24
Finished	Mar 14 01:10:38 PM PDT 24
Peak memory	215352 kb
Host	smart-20eb1794-49e5-41eb-9f7b-9c6450cbf560
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069051434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.3069051434 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.691125827
Short name	T173
Test name
Test status
Simulation time	41066466 ps
CPU time	2.58 seconds
Started	Mar 14 01:10:32 PM PDT 24
Finished	Mar 14 01:10:37 PM PDT 24
Peak memory	215064 kb
Host	smart-f6cb954f-0c4a-4214-b0d1-8c5573312558
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691125827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.691125827 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest