Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 278 1 T6 7 T7 7 T9 4
all_values[1] 278 1 T6 7 T7 7 T9 4
all_values[2] 278 1 T6 7 T7 7 T9 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 437 1 T6 12 T7 11 T9 7
auto[1] 397 1 T6 9 T7 10 T9 5


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 357 1 T6 11 T7 5 T9 9
auto[1] 477 1 T6 10 T7 16 T9 3


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 472 1 T6 13 T7 9 T9 9
auto[1] 362 1 T6 8 T7 12 T9 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 55 1 T6 2 T9 2 T8 1
all_values[0] auto[0] auto[0] auto[1] 26 1 T7 1 T8 1 T72 2
all_values[0] auto[0] auto[1] auto[0] 50 1 T6 1 T8 1 T33 3
all_values[0] auto[0] auto[1] auto[1] 27 1 T7 2 T8 1 T72 1
all_values[0] auto[1] auto[0] auto[1] 75 1 T6 3 T7 3 T9 2
all_values[0] auto[1] auto[1] auto[1] 45 1 T6 1 T7 1 T8 2
all_values[1] auto[0] auto[0] auto[0] 86 1 T6 3 T7 3 T9 2
all_values[1] auto[0] auto[1] auto[0] 73 1 T6 2 T7 1 T9 1
all_values[1] auto[1] auto[0] auto[1] 52 1 T7 1 T8 2 T33 1
all_values[1] auto[1] auto[1] auto[1] 67 1 T6 2 T7 2 T9 1
all_values[2] auto[0] auto[0] auto[0] 43 1 T6 2 T9 1 T33 2
all_values[2] auto[0] auto[0] auto[1] 28 1 T6 1 T73 1 T74 1
all_values[2] auto[0] auto[1] auto[0] 50 1 T6 1 T7 1 T9 3
all_values[2] auto[0] auto[1] auto[1] 34 1 T6 1 T7 1 T8 1
all_values[2] auto[1] auto[0] auto[1] 72 1 T6 1 T7 3 T8 5
all_values[2] auto[1] auto[1] auto[1] 51 1 T6 1 T7 2 T33 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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