Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.19	96.27	93.33	63.67	100.00	93.85	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	97.24	96.27	93.33	100.00	100.00	93.85	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.24	96.27	93.33	100.00	100.00	93.85	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.09	96.18	92.38	100.00	88.64	94.52	98.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	86.94	90.00	77.78			80.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	93.01	94.07	89.80		88.24	92.94	100.00
u_errchk	95.99	97.14	96.67		90.00	96.15	100.00
u_kmac_core	95.80	98.75	92.86	100.00	100.00	92.31	90.91
u_msgfifo	97.55	100.00	94.00		100.00	93.75	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.86	99.21	96.48	100.00		98.63	100.00
u_sha3	92.16	91.91	88.51	100.00	80.56	92.00	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.69	89.64	80.83			88.30	100.00
u_tlul_adapter_msgfifo	79.67	86.78	73.83			76.83	81.25

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	0	0
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
ALWAYS	558	5	5	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
ALWAYS	649	5	5	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
ALWAYS	686	7	5	71.43
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	727	1	0	0.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
ALWAYS	764	3	3	100.00
ALWAYS	768	28	28	100.00
CONT_ASSIGN	918	1	1	100.00
CONT_ASSIGN	921	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1027	1	1	100.00
CONT_ASSIGN	1028	1	1	100.00
CONT_ASSIGN	1030	1	1	100.00
CONT_ASSIGN	1033	0	0
ALWAYS	1151	0	0
ALWAYS	1151	2	2	100.00
CONT_ASSIGN	1304	1	0	0.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1338	1	1	100.00
CONT_ASSIGN	1380	1	1	100.00
CONT_ASSIGN	1394	1	1	100.00
CONT_ASSIGN	1401	1	1	100.00
CONT_ASSIGN	1406	1	1	100.00
ALWAYS	1412	6	5	83.33
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1423	1	1	100.00
ALWAYS	1435	4	4	100.00
CONT_ASSIGN	1441	1	1	100.00
ALWAYS	1464	4	4	100.00
ALWAYS	1474	3	3	100.00
CONT_ASSIGN	1485	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
510	1	1
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534		unreachable
536	1	1
540	1	1
542	1	1
543	1	1
546	1	1
547	1	1
550	1	1
558	1	1
559	1	1
560	1	1
561	1	1
563	1	1
568	1	1
575	1	1
576	1	1
577	1	1
585	1	1
627	1	1
633	1	1
641	1	1
646	1	1
649	1	1
650	1	1
651	1	1
653	1	1
654	1	1
678	1	1
683	1	1
686	1	1
688	1	1
693	1	1
697	1	1
701	1	1
705	0	1
709	0	1
722	1	1
727	0	1
734	1	1
744	1	1
764	3	3
768	1	1
770	1	1
771	1	1
773	1	1
775	1	1
777	1	1
778	1	1
781	1	1
784	1	1
790	1	1
791	1	1
793	1	1
798	1	1
799	1	1
800	1	1
802	1	1
808	1	1
813	1	1
814	1	1
816	1	1
818	1	1
824	1	1
825	1	1
827	1	1
833	1	1
834	1	1
846	1	1
847	1	1
			MISSING_ELSE
918	1	1
921	1	1
990	1	1
992	1	1
1022	1	1
1027	1	1
1028	1	1
1030	1	1
1033		unreachable
1151	1	1
1152	1	1
1304	0	1
1305	1	1
1306	1	1
1316	1	1
1317	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1329	1	1
1338	1	1
1380	1	1
1394	1	1
1401	1	1
1406	1	1
1412	1	1
1413	1	1
1414	1	1
1415	0	1
1416	1	1
1417	1	1
			MISSING_ELSE
1421	1	1
1423	1	1
1435	1	1
1436	1	1
1437	1	1
1438	1	1
			MISSING_ELSE
1441	1	1
1464	1	1
1465	1	1
1466	1	1
1468	1	1
			MISSING_ELSE
1474	1	1
1475	1	1
1478	1	1
1485	1	1
1489	1	1
1491	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T49,T31

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T49,T31

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T13
1	1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       627
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       633
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T45,T50

 LINE       633
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       633
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T4,T20

 LINE       641
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       646
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T18,T45,T50
1	Covered	T1,T2,T3

 LINE       678
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T22,T34,T35
0	0	1	0	Not Covered
0	1	0	0	Covered	T19,T4,T20
1	0	0	0	Covered	T27,T28,T29

 LINE       722
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T10,T11,T12

 LINE       734
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T10,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T10,T11,T12
0	0	1	0	0	0	Covered	T10,T11,T12
0	1	0	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	0	Covered	T10,T11,T12

 LINE       775
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       777
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T4,T18

 LINE       791
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T4,T22,T23
1	Covered	T15,T4,T18

 LINE       1022
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1152
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T44,T52,T53

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T44,T52,T53

 LINE       1423
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T10,T11,T12
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	64	90.14
Total Bits	6534	4160	63.67
Total Bits 0->1	3267	2080	63.67
Total Bits 1->0	3267	2080	63.67

Ports	71	64	90.14
Port Bits	6534	4160	63.67
Port Bits 0->1	3267	2080	63.67
Port Bits 1->0	3267	2080	63.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T43,T5	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T4,T43,T5	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T4,T43,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T15	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T13,T16,T19	Yes	T13,T16,T19	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T44,T52,T53	Yes	T44,T52,T53	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T44,T52	Yes	T4,T44,T52	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T44,T52,T53	Yes	T44,T52,T53	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T44,T52	Yes	T4,T44,T52	OUTPUT
keymgr_key_i.key[0][1:0]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][13:2]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][14]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][19:15]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][20]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][25:21]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][26]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][28:27]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][29]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][33:30]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][34]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][38:35]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][39]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][40]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][41]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][46:42]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][47]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[0][52:48]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][53]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][56:54]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][57]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][58]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][65:59]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][66]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][67]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][68]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[0][69]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][71:70]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][76:72]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][77]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][78]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][79]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][91:80]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][95:92]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][98:96]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][99]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][105:100]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][106]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][109:107]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][110]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][112:111]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][113]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][114]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][117:115]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][119:118]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][124:120]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][125]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][126]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][128:127]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][129]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][131:130]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][132]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][137:133]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][139:138]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][140]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][141]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[0][143:142]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][144]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][145]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][146]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][147]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][148]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][149]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][150]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][154:151]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][155]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][156]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][157]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][158]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][159]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][160]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][163:161]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][164]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][167:165]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][168]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][174:169]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][176:175]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][185:177]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][186]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][196:187]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][197]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][198]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][205:199]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][206]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][207]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][208]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][209]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][210]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][211]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][212]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][213]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][214]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][215]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][216]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][217]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][218]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][222:219]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][223]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][225:224]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][229:226]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][230]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][234:231]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][237:235]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][239:238]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][242:240]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][243]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][246:244]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][247]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][251:248]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][252]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[0][253]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][254]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][255]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][1:0]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][3:2]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][6:4]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][7]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][10:8]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][11]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][12]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][13]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][17:14]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][18]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][21:19]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][22]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][27:23]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][29:28]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][32:30]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][33]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][34]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][35]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][39:36]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][40]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][44:41]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][45]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][47:46]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][48]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][50:49]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][51]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[1][52]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][59:53]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][60]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][64:61]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][66:65]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][69:67]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][70]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][72:71]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][76:73]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][77]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][79:78]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][81:80]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][82]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][83]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][84]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][85]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][86]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][87]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][88]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][89]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][90]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][91]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][94:92]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][95]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][101:96]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][102]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][106:103]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][107]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][116:108]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][118:117]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][119]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][127:120]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][128]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][129]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][131:130]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][134:132]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][137:135]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][142:138]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][143]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][146:144]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][148:147]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][153:149]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][154]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][156:155]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][157]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][158]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][159]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][161:160]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][162]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][167:163]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][168]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][172:169]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][173]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][174]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][175]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][176]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][177]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][178]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][184:179]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][185]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[1][186]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][188:187]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][189]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][191:190]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][192]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][193]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][194]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][197:195]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][199:198]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][203:200]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][204]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][205]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][206]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][207]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][208]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][209]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][210]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][211]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][212]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][213]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][214]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][224:215]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][225]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][226]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][229:227]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][230]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][231]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][234:232]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][237:235]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][238]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][239]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][240]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][246:241]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][247]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][250:248]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][251]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][255:252]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.valid	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
app_i[0].last	Yes	Yes	T4,T22,T23	Yes	T4,T22,T23	INPUT
app_i[0].strb[7:0]	Yes	Yes	T23,T30,T33	Yes	T23,T30,T33	INPUT
app_i[0].data[63:0]	Yes	Yes	T19,T4,T20	Yes	T19,T4,T20	INPUT
app_i[0].valid	Yes	Yes	T19,T4,T20	Yes	T19,T4,T20	INPUT
app_i[1].last	Yes	Yes	T23,T30,T33	Yes	T22,T23,T30	INPUT
app_i[1].strb[7:0]	Yes	Yes	T23,T30,T33	Yes	T23,T30,T33	INPUT
app_i[1].data[63:0]	Yes	Yes	T22,T23,T30	Yes	T22,T23,T30	INPUT
app_i[1].valid	Yes	Yes	T4,T22,T23	Yes	T4,T22,T23	INPUT
app_i[2].last	Yes	Yes	T4,T30,T33	Yes	T4,T23,T30	INPUT
app_i[2].strb[7:0]	Yes	Yes	T23,T30,T33	Yes	T23,T30,T33	INPUT
app_i[2].data[63:0]	Yes	Yes	T4,T23,T30	Yes	T4,T23,T30	INPUT
app_i[2].valid	Yes	Yes	T4,T23,T30	Yes	T4,T23,T30	INPUT
app_o[0].error	Yes	Yes	T4,T5,T27	Yes	T4,T5,T27	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T4,T22,T23	Yes	T4,T22,T23	OUTPUT
app_o[0].done	Yes	Yes	T4,T22,T23	Yes	T4,T22,T23	OUTPUT
app_o[0].ready	Yes	Yes	T19,T4,T20	Yes	T19,T4,T20	OUTPUT
app_o[1].error	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T22,T23,T30	Yes	T22,T23,T30	OUTPUT
app_o[1].done	Yes	Yes	T22,T23,T30	Yes	T22,T23,T30	OUTPUT
app_o[1].ready	Yes	Yes	T22,T23,T30	Yes	T22,T23,T30	OUTPUT
app_o[2].error	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T23,T30,T33	Yes	T23,T30,T33	OUTPUT
app_o[2].done	Yes	Yes	T4,T23,T30	Yes	T4,T23,T30	OUTPUT
app_o[2].ready	Yes	Yes	T4,T23,T30	Yes	T4,T23,T30	OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
intr_kmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T18,T45,T50	Yes	T18,T45,T50	OUTPUT
intr_kmac_err_o	Yes	Yes	T19,T4,T20	Yes	T19,T4,T20	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	816	Covered	T1,T2,T3
KmacIdle	784	Covered	T1,T2,T3
KmacKeyBlock	791	Covered	T15,T4,T18
KmacMsgFeed	781	Covered	T1,T2,T3
KmacPrefix	778	Covered	T15,T4,T18
KmacTerminalError	833	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	825	Covered	T1,T2,T3
KmacDigest->KmacTerminalError	847	Covered	T6,T57,T58
KmacIdle->KmacMsgFeed	781	Covered	T1,T2,T3
KmacIdle->KmacPrefix	778	Covered	T15,T4,T18
KmacIdle->KmacTerminalError	847	Covered	T4,T40,T10
KmacKeyBlock->KmacMsgFeed	800	Covered	T15,T4,T18
KmacKeyBlock->KmacTerminalError	847	Covered	T7,T37,T8
KmacMsgFeed->KmacDigest	816	Covered	T1,T2,T3
KmacMsgFeed->KmacIdle	813	Covered	T4,T22,T23
KmacMsgFeed->KmacTerminalError	847	Covered	T41,T59,T60
KmacPrefix->KmacKeyBlock	791	Covered	T15,T4,T18
KmacPrefix->KmacMsgFeed	791	Covered	T4,T22,T23
KmacPrefix->KmacTerminalError	847	Covered	T5,T61,T62

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	423	2	2	100.00
TERNARY	633	4	4	100.00
TERNARY	641	4	4	100.00
TERNARY	646	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	558	3	3	100.00
IF	649	2	2	100.00
CASE	688	6	4	66.67
IF	764	2	2	100.00
CASE	773	15	15	100.00
IF	846	2	2	100.00
TERNARY	1152	2	2	100.00
IF	1412	4	3	75.00
IF	1435	3	3	100.00
IF	1464	3	3	100.00
IF	1474	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	633	(msgfifo_full) ? 
-2-:	633	(msgfifo_empty_negedge) ? 
-3-:	633	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T18,T45,T50
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	641	(app_active) ? 
-2-:	641	((sha3_fsm != StAbsorb)) ? 
-3-:	641	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T4,T20
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	646	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T18,T45,T50

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T15,T4,T18
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	688	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T19,T4,T20
errchecker_err.valid	Covered	T22,T34,T35
sha3_err.valid	Covered	T27,T28,T29
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	764	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	773	case (kmac_st)
-2-:	775	if ((kmac_cmd == CmdStart))
-3-:	777	if ((CShake == app_sha3_mode))
-4-:	790	if (sha3_block_processed)
-5-:	791	(app_kmac_en) ? 
-6-:	799	if (sha3_block_processed)
-7-:	808	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	814	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	824	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T15,T4,T18
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T15,T4,T18
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T4,T22,T23
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T15,T4,T18
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T15,T4,T18
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T15,T4,T18
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T4,T22,T23
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	846	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1152	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1412	if ((!rst_ni))
-2-:	1414	if (alert_recov_operation)
-3-:	1416	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1435	if ((!rst_ni))
-2-:	1437	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1464	if ((!rst_ni))
-2-:	1466	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1474	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1287435	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	339236	0	0
EntrySizeRegSameToEntrySizePkg_A	1026	1026	0	0
ErrProcessedLatched_A	2147483647	504	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1026	1026	0	0
NumEntriesRegSameToNumEntriesPkg_A	1026	1026	0	0
PrefixRegSameToPrefixPkg_A	1026	1026	0	0
SecretKeyDivideBy32_A	1026	1026	0	0
Sha3AbsorbedPulse_A	2147483647	348736	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1287435	0	0
T1	602687	1213	0	0
T2	134606	990	0	0
T3	633950	1248	0	0
T4	52942	32	0	0
T13	192054	1245	0	0
T14	174765	1187	0	0
T15	635127	328	0	0
T16	477617	992	0	0
T17	942438	785	0	0
T19	32523	1	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	339236	0	0
T1	602687	362	0	0
T2	134606	301	0	0
T3	633950	378	0	0
T4	52942	9	0	0
T13	192054	381	0	0
T14	174765	363	0	0
T15	635127	48	0	0
T16	477617	301	0	0
T17	942438	237	0	0
T19	32523	5	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	504	0	0
T4	52942	0	0	0
T17	942438	0	0	0
T18	56635	0	0	0
T19	32523	5	0	0
T20	0	9	0	0
T21	0	15	0	0
T24	0	7	0	0
T43	12988	0	0	0
T44	1204	0	0	0
T45	630758	0	0	0
T46	180397	0	0	0
T47	647174	0	0	0
T48	332133	0	0	0
T63	0	12	0	0
T64	0	14	0	0
T65	0	1	0	0
T66	0	17	0	0
T67	0	18	0	0
T68	0	3	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348736	0	0
T1	602687	374	0	0
T2	134606	310	0	0
T3	633950	390	0	0
T4	52942	9	0	0
T13	192054	390	0	0
T14	174765	374	0	0
T15	635127	48	0	0
T16	477617	310	0	0
T17	942438	246	0	0
T18	0	12	0	0
T19	32523	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	0	0
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
ALWAYS	558	5	5	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
ALWAYS	649	5	5	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
ALWAYS	686	7	5	71.43
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	727	1	0	0.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
ALWAYS	764	3	3	100.00
ALWAYS	768	28	28	100.00
CONT_ASSIGN	918	1	1	100.00
CONT_ASSIGN	921	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1027	1	1	100.00
CONT_ASSIGN	1028	1	1	100.00
CONT_ASSIGN	1030	1	1	100.00
CONT_ASSIGN	1033	0	0
ALWAYS	1151	0	0
ALWAYS	1151	2	2	100.00
CONT_ASSIGN	1304	1	0	0.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1338	1	1	100.00
CONT_ASSIGN	1380	1	1	100.00
CONT_ASSIGN	1394	1	1	100.00
CONT_ASSIGN	1401	1	1	100.00
CONT_ASSIGN	1406	1	1	100.00
ALWAYS	1412	6	5	83.33
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1423	1	1	100.00
ALWAYS	1435	4	4	100.00
CONT_ASSIGN	1441	1	1	100.00
ALWAYS	1464	4	4	100.00
ALWAYS	1474	3	3	100.00
CONT_ASSIGN	1485	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
510	1	1
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534		unreachable
536	1	1
540	1	1
542	1	1
543	1	1
546	1	1
547	1	1
550	1	1
558	1	1
559	1	1
560	1	1
561	1	1
563	1	1
568	1	1
575	1	1
576	1	1
577	1	1
585	1	1
627	1	1
633	1	1
641	1	1
646	1	1
649	1	1
650	1	1
651	1	1
653	1	1
654	1	1
678	1	1
683	1	1
686	1	1
688	1	1
693	1	1
697	1	1
701	1	1
705	0	1
709	0	1
722	1	1
727	0	1
734	1	1
744	1	1
764	3	3
768	1	1
770	1	1
771	1	1
773	1	1
775	1	1
777	1	1
778	1	1
781	1	1
784	1	1
790	1	1
791	1	1
793	1	1
798	1	1
799	1	1
800	1	1
802	1	1
808	1	1
813	1	1
814	1	1
816	1	1
818	1	1
824	1	1
825	1	1
827	1	1
833	1	1
834	1	1
846	1	1
847	1	1
			MISSING_ELSE
918	1	1
921	1	1
990	1	1
992	1	1
1022	1	1
1027	1	1
1028	1	1
1030	1	1
1033		unreachable
1151	1	1
1152	1	1
1304	0	1
1305	1	1
1306	1	1
1316	1	1
1317	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1329	1	1
1338	1	1
1380	1	1
1394	1	1
1401	1	1
1406	1	1
1412	1	1
1413	1	1
1414	1	1
1415	0	1
1416	1	1
1417	1	1
			MISSING_ELSE
1421	1	1
1423	1	1
1435	1	1
1436	1	1
1437	1	1
1438	1	1
			MISSING_ELSE
1441	1	1
1464	1	1
1465	1	1
1466	1	1
1468	1	1
			MISSING_ELSE
1474	1	1
1475	1	1
1478	1	1
1485	1	1
1489	1	1
1491	6	6

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T49,T31

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T49,T31

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T13
1	1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       627
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       633
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T45,T50

 LINE       633
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       633
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T4,T20

 LINE       641
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       646
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T18,T45,T50
1	Covered	T1,T2,T3

 LINE       678
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T22,T34,T35
0	0	1	0	Not Covered
0	1	0	0	Covered	T19,T4,T20
1	0	0	0	Covered	T27,T28,T29

 LINE       722
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T10,T11,T12

 LINE       734
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T10,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T10,T11,T12
0	0	1	0	0	0	Covered	T10,T11,T12
0	1	0	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	0	Covered	T10,T11,T12

 LINE       775
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       777
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T4,T18

 LINE       791
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T4,T22,T23
1	Covered	T15,T4,T18

 LINE       1022
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1152
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T44,T52,T53

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T44,T52,T53

 LINE       1423
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T10,T11,T12
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	64	100.00
Total Bits	4160	4160	100.00
Total Bits 0->1	2080	2080	100.00
Total Bits 1->0	2080	2080	100.00

Ports	64	64	100.00
Port Bits	4160	4160	100.00
Port Bits 0->1	2080	2080	100.00
Port Bits 1->0	2080	2080	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T43,T5	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T4,T43,T5	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T4,T43,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T15	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T13,T16,T19	Yes	T13,T16,T19	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T44,T52,T53	Yes	T44,T52,T53	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T44,T52	Yes	T4,T44,T52	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T44,T52,T53	Yes	T44,T52,T53	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T44,T52	Yes	T4,T44,T52	OUTPUT
keymgr_key_i.key[0][1:0]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][13:2]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][14]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][19:15]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][20]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][25:21]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][26]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][28:27]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][29]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][33:30]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][34]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][38:35]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][39]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][40]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][41]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][46:42]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][47]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[0][52:48]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][53]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][56:54]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][57]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][58]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][65:59]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][66]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][67]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][68]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[0][69]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][71:70]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][76:72]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][77]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][78]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][79]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][91:80]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][95:92]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][98:96]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][99]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][105:100]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][106]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][109:107]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][110]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][112:111]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][113]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][114]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][117:115]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][119:118]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][124:120]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][125]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][126]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][128:127]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][129]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][131:130]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][132]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][137:133]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][139:138]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][140]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][141]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[0][143:142]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][144]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][145]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][146]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][147]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][148]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][149]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][150]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][154:151]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][155]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][156]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][157]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][158]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][159]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][160]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][163:161]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][164]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][167:165]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][168]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][174:169]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][176:175]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][185:177]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][186]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][196:187]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][197]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][198]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][205:199]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][206]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][207]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][208]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][209]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][210]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][211]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][212]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][213]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][214]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][215]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][216]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][217]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][218]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][222:219]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][223]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][225:224]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][229:226]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][230]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][234:231]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][237:235]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][239:238]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[0][242:240]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][243]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][246:244]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][247]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][251:248]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][252]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[0][253]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[0][254]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[0][255]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][1:0]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][3:2]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][6:4]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][7]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][10:8]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][11]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][12]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][13]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][17:14]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][18]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][21:19]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][22]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][27:23]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][29:28]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][32:30]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][33]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][34]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][35]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][39:36]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][40]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][44:41]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][45]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][47:46]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][48]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][50:49]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][51]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[1][52]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][59:53]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][60]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][64:61]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][66:65]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][69:67]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][70]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][72:71]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][76:73]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][77]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][79:78]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][81:80]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][82]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][83]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][84]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][85]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][86]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][87]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][88]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][89]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][90]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][91]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][94:92]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][95]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][101:96]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][102]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][106:103]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][107]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][116:108]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][118:117]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][119]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][127:120]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][128]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][129]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][131:130]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][134:132]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][137:135]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][142:138]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][143]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][146:144]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][148:147]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][153:149]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][154]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][156:155]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][157]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][158]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][159]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][161:160]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][162]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][167:163]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][168]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][172:169]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][173]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][174]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][175]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][176]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][177]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][178]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][184:179]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][185]	Yes	Yes	T15,T45,T46	Yes	T15,T45,T46	INPUT
keymgr_key_i.key[1][186]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][188:187]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][189]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][191:190]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][192]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][193]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][194]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][197:195]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][199:198]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][203:200]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][204]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][205]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][206]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][207]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][208]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][209]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][210]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][211]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][212]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][213]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][214]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][224:215]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][225]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][226]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][229:227]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][230]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][231]	Yes	Yes	T15,T4,T45	Yes	T15,T4,T45	INPUT
keymgr_key_i.key[1][234:232]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][237:235]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][238]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][239]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][240]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][246:241]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][247]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][250:248]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.key[1][251]	Yes	Yes	T15,T18,T45	Yes	T15,T18,T45	INPUT
keymgr_key_i.key[1][255:252]	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
keymgr_key_i.valid	Yes	Yes	T15,T4,T18	Yes	T15,T4,T18	INPUT
app_i[0].last	Yes	Yes	T4,T22,T23	Yes	T4,T22,T23	INPUT
app_i[0].strb[7:0]	Yes	Yes	T23,T30,T33	Yes	T23,T30,T33	INPUT
app_i[0].data[63:0]	Yes	Yes	T19,T4,T20	Yes	T19,T4,T20	INPUT
app_i[0].valid	Yes	Yes	T19,T4,T20	Yes	T19,T4,T20	INPUT
app_i[1].last	Yes	Yes	T23,T30,T33	Yes	T22,T23,T30	INPUT
app_i[1].strb[7:0]	Yes	Yes	T23,T30,T33	Yes	T23,T30,T33	INPUT
app_i[1].data[63:0]	Yes	Yes	T22,T23,T30	Yes	T22,T23,T30	INPUT
app_i[1].valid	Yes	Yes	T4,T22,T23	Yes	T4,T22,T23	INPUT
app_i[2].last	Yes	Yes	T4,T30,T33	Yes	T4,T23,T30	INPUT
app_i[2].strb[7:0]	Yes	Yes	T23,T30,T33	Yes	T23,T30,T33	INPUT
app_i[2].data[63:0]	Yes	Yes	T4,T23,T30	Yes	T4,T23,T30	INPUT
app_i[2].valid	Yes	Yes	T4,T23,T30	Yes	T4,T23,T30	INPUT
app_o[0].error	Yes	Yes	T4,T5,T27	Yes	T4,T5,T27	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	Yes	Yes	T4,T22,T23	Yes	T4,T22,T23	OUTPUT
app_o[0].done	Yes	Yes	T4,T22,T23	Yes	T4,T22,T23	OUTPUT
app_o[0].ready	Yes	Yes	T19,T4,T20	Yes	T19,T4,T20	OUTPUT
app_o[1].error	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	Yes	Yes	T22,T23,T30	Yes	T22,T23,T30	OUTPUT
app_o[1].done	Yes	Yes	T22,T23,T30	Yes	T22,T23,T30	OUTPUT
app_o[1].ready	Yes	Yes	T22,T23,T30	Yes	T22,T23,T30	OUTPUT
app_o[2].error	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	Yes	Yes	T23,T30,T33	Yes	T23,T30,T33	OUTPUT
app_o[2].done	Yes	Yes	T4,T23,T30	Yes	T4,T23,T30	OUTPUT
app_o[2].ready	Yes	Yes	T4,T23,T30	Yes	T4,T23,T30	OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
intr_kmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T18,T45,T50	Yes	T18,T45,T50	OUTPUT
intr_kmac_err_o	Yes	Yes	T19,T4,T20	Yes	T19,T4,T20	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	816	Covered	T1,T2,T3
KmacIdle	784	Covered	T1,T2,T3
KmacKeyBlock	791	Covered	T15,T4,T18
KmacMsgFeed	781	Covered	T1,T2,T3
KmacPrefix	778	Covered	T15,T4,T18
KmacTerminalError	833	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	825	Covered	T1,T2,T3
KmacDigest->KmacTerminalError	847	Covered	T6,T57,T58
KmacIdle->KmacMsgFeed	781	Covered	T1,T2,T3
KmacIdle->KmacPrefix	778	Covered	T15,T4,T18
KmacIdle->KmacTerminalError	847	Covered	T4,T40,T10
KmacKeyBlock->KmacMsgFeed	800	Covered	T15,T4,T18
KmacKeyBlock->KmacTerminalError	847	Covered	T7,T37,T8
KmacMsgFeed->KmacDigest	816	Covered	T1,T2,T3
KmacMsgFeed->KmacIdle	813	Covered	T4,T22,T23
KmacMsgFeed->KmacTerminalError	847	Covered	T41,T59,T60
KmacPrefix->KmacKeyBlock	791	Covered	T15,T4,T18
KmacPrefix->KmacMsgFeed	791	Covered	T4,T22,T23
KmacPrefix->KmacTerminalError	847	Covered	T5,T61,T62

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	423	2	2	100.00
TERNARY	633	4	4	100.00
TERNARY	641	4	4	100.00
TERNARY	646	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	558	3	3	100.00
IF	649	2	2	100.00
CASE	688	6	4	66.67
IF	764	2	2	100.00
CASE	773	15	15	100.00
IF	846	2	2	100.00
TERNARY	1152	2	2	100.00
IF	1412	4	3	75.00
IF	1435	3	3	100.00
IF	1464	3	3	100.00
IF	1474	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	633	(msgfifo_full) ? 
-2-:	633	(msgfifo_empty_negedge) ? 
-3-:	633	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T18,T45,T50
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	641	(app_active) ? 
-2-:	641	((sha3_fsm != StAbsorb)) ? 
-3-:	641	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T4,T20
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	646	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T18,T45,T50

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T15,T4,T18
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	688	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T19,T4,T20
errchecker_err.valid	Covered	T22,T34,T35
sha3_err.valid	Covered	T27,T28,T29
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	764	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	773	case (kmac_st)
-2-:	775	if ((kmac_cmd == CmdStart))
-3-:	777	if ((CShake == app_sha3_mode))
-4-:	790	if (sha3_block_processed)
-5-:	791	(app_kmac_en) ? 
-6-:	799	if (sha3_block_processed)
-7-:	808	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	814	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	824	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T15,T4,T18
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T15,T4,T18
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T4,T22,T23
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T15,T4,T18
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T15,T4,T18
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T15,T4,T18
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T4,T22,T23
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	846	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1152	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1412	if ((!rst_ni))
-2-:	1414	if (alert_recov_operation)
-3-:	1416	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1435	if ((!rst_ni))
-2-:	1437	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1464	if ((!rst_ni))
-2-:	1466	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1474	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1287435	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	339236	0	0
EntrySizeRegSameToEntrySizePkg_A	1026	1026	0	0
ErrProcessedLatched_A	2147483647	504	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1026	1026	0	0
NumEntriesRegSameToNumEntriesPkg_A	1026	1026	0	0
PrefixRegSameToPrefixPkg_A	1026	1026	0	0
SecretKeyDivideBy32_A	1026	1026	0	0
Sha3AbsorbedPulse_A	2147483647	348736	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1287435	0	0
T1	602687	1213	0	0
T2	134606	990	0	0
T3	633950	1248	0	0
T4	52942	32	0	0
T13	192054	1245	0	0
T14	174765	1187	0	0
T15	635127	328	0	0
T16	477617	992	0	0
T17	942438	785	0	0
T19	32523	1	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	339236	0	0
T1	602687	362	0	0
T2	134606	301	0	0
T3	633950	378	0	0
T4	52942	9	0	0
T13	192054	381	0	0
T14	174765	363	0	0
T15	635127	48	0	0
T16	477617	301	0	0
T17	942438	237	0	0
T19	32523	5	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	504	0	0
T4	52942	0	0	0
T17	942438	0	0	0
T18	56635	0	0	0
T19	32523	5	0	0
T20	0	9	0	0
T21	0	15	0	0
T24	0	7	0	0
T43	12988	0	0	0
T44	1204	0	0	0
T45	630758	0	0	0
T46	180397	0	0	0
T47	647174	0	0	0
T48	332133	0	0	0
T63	0	12	0	0
T64	0	14	0	0
T65	0	1	0	0
T66	0	17	0	0
T67	0	18	0	0
T68	0	3	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	472050	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T69	0	10	0	0
T70	0	20	0	0
T71	92070	0	0	0
T72	207847	0	0	0
T73	437786	0	0	0
T74	543601	0	0	0
T75	522688	0	0	0
T76	45314	0	0	0
T77	455998	0	0	0
T78	432233	0	0	0
T79	701863	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348736	0	0
T1	602687	374	0	0
T2	134606	310	0	0
T3	633950	390	0	0
T4	52942	9	0	0
T13	192054	390	0	0
T14	174765	374	0	0
T15	635127	48	0	0
T16	477617	310	0	0
T17	942438	246	0	0
T18	0	12	0	0
T19	32523	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	602687	602681	0	0
T2	134606	134597	0	0
T3	633950	633941	0	0
T4	52942	52786	0	0
T13	192054	192047	0	0
T14	174765	174756	0	0
T15	635127	635042	0	0
T16	477617	477607	0	0
T17	942438	942372	0	0
T19	32523	32463	0	0