Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	301616	0	0
entropy_period_rd_A	2147483647	2133	0	0
intr_enable_rd_A	2147483647	2829	0	0
prefix_0_rd_A	2147483647	2095	0	0
prefix_10_rd_A	2147483647	1945	0	0
prefix_1_rd_A	2147483647	2008	0	0
prefix_2_rd_A	2147483647	2072	0	0
prefix_3_rd_A	2147483647	1940	0	0
prefix_4_rd_A	2147483647	2109	0	0
prefix_5_rd_A	2147483647	1917	0	0
prefix_6_rd_A	2147483647	1895	0	0
prefix_7_rd_A	2147483647	1991	0	0
prefix_8_rd_A	2147483647	1990	0	0
prefix_9_rd_A	2147483647	1923	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	301616	0	0
T54	159301	23935	0	0
T55	816233	92851	0	0
T56	0	33914	0	0
T142	0	28049	0	0
T143	0	50305	0	0
T144	0	52701	0	0
T145	0	16405	0	0
T146	0	3	0	0
T147	0	1	0	0
T148	0	3	0	0
T149	193027	0	0	0
T150	395799	0	0	0
T151	396630	0	0	0
T152	5975	0	0	0
T153	147779	0	0	0
T154	569864	0	0	0
T155	175456	0	0	0
T156	187937	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2133	0	0
T145	202783	26	0	0
T146	0	7	0	0
T147	0	12	0	0
T163	0	126	0	0
T164	0	102	0	0
T165	0	48	0	0
T166	0	14	0	0
T167	0	24	0	0
T168	0	1	0	0
T169	0	24	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2829	0	0
T139	0	14	0	0
T145	202783	65	0	0
T146	0	5	0	0
T147	0	11	0	0
T163	0	169	0	0
T164	0	174	0	0
T165	0	52	0	0
T166	0	19	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0
T179	0	1	0	0
T180	0	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2095	0	0
T145	202783	38	0	0
T146	0	3	0	0
T147	0	8	0	0
T163	0	58	0	0
T164	0	73	0	0
T165	0	54	0	0
T166	0	19	0	0
T167	0	9	0	0
T168	0	5	0	0
T169	0	35	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1945	0	0
T145	202783	62	0	0
T146	0	2	0	0
T147	0	6	0	0
T163	0	87	0	0
T164	0	94	0	0
T165	0	50	0	0
T166	0	14	0	0
T167	0	15	0	0
T169	0	29	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0
T181	0	66	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2008	0	0
T145	202783	57	0	0
T146	0	5	0	0
T147	0	4	0	0
T163	0	82	0	0
T164	0	76	0	0
T165	0	53	0	0
T166	0	23	0	0
T167	0	16	0	0
T168	0	7	0	0
T169	0	42	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2072	0	0
T145	202783	59	0	0
T146	0	7	0	0
T147	0	9	0	0
T163	0	85	0	0
T164	0	83	0	0
T165	0	48	0	0
T166	0	23	0	0
T167	0	11	0	0
T168	0	2	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0
T182	0	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1940	0	0
T145	202783	61	0	0
T146	0	13	0	0
T147	0	9	0	0
T163	0	91	0	0
T164	0	63	0	0
T165	0	36	0	0
T166	0	18	0	0
T167	0	24	0	0
T168	0	10	0	0
T169	0	24	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2109	0	0
T145	202783	32	0	0
T146	0	10	0	0
T147	0	13	0	0
T163	0	87	0	0
T164	0	84	0	0
T165	0	48	0	0
T166	0	21	0	0
T167	0	15	0	0
T168	0	3	0	0
T169	0	30	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1917	0	0
T145	202783	57	0	0
T146	0	8	0	0
T147	0	9	0	0
T163	0	60	0	0
T164	0	66	0	0
T165	0	39	0	0
T166	0	8	0	0
T167	0	11	0	0
T169	0	28	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0
T181	0	21	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1895	0	0
T145	202783	38	0	0
T146	0	12	0	0
T147	0	10	0	0
T163	0	85	0	0
T164	0	83	0	0
T165	0	40	0	0
T166	0	10	0	0
T167	0	14	0	0
T168	0	9	0	0
T169	0	33	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1991	0	0
T145	202783	39	0	0
T146	0	15	0	0
T147	0	10	0	0
T163	0	85	0	0
T164	0	84	0	0
T165	0	51	0	0
T166	0	28	0	0
T167	0	11	0	0
T168	0	2	0	0
T169	0	33	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1990	0	0
T145	202783	36	0	0
T146	0	3	0	0
T147	0	5	0	0
T163	0	99	0	0
T164	0	63	0	0
T165	0	23	0	0
T166	0	26	0	0
T167	0	8	0	0
T168	0	3	0	0
T169	0	45	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1923	0	0
T145	202783	37	0	0
T146	0	1	0	0
T147	0	8	0	0
T163	0	84	0	0
T164	0	98	0	0
T165	0	32	0	0
T166	0	22	0	0
T167	0	15	0	0
T168	0	5	0	0
T169	0	33	0	0
T170	606960	0	0	0
T171	13338	0	0	0
T172	69559	0	0	0
T173	431543	0	0	0
T174	69528	0	0	0
T175	606224	0	0	0
T176	555138	0	0	0
T177	22933	0	0	0
T178	145227	0	0	0