Design subhierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

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NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
intr_fifo_empty 86.94 90.00 77.78 80.00 100.00
intr_kmac_done 93.75 100.00 75.00 100.00 100.00
intr_kmac_err 93.75 100.00 75.00 100.00 100.00
kmac_csr_assert 100.00 100.00
sha3pad_assert_cov_if 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
 u_app_intf 93.01 94.07 89.80 88.24 92.94 100.00
 u_errchk 95.99 97.14 96.67 90.00 96.15 100.00
 u_kmac_core 95.80 98.75 92.86 100.00 100.00 92.31 90.91
 u_msgfifo 97.75 100.00 95.00 100.00 93.75 100.00
 u_prim_lc_sync 100.00 100.00 100.00 100.00
 u_reg 98.86 99.21 96.48 100.00 98.63 100.00
 u_sha3 92.16 91.91 88.51 100.00 80.56 92.00 100.00
 u_sha3_done_sender 100.00 100.00 100.00 100.00
 u_state_regs 100.00 100.00 100.00 100.00
 u_staterd 89.67 89.64 80.74 88.30 100.00
 u_tlul_adapter_msgfifo 79.76 86.78 74.17 76.83 81.25