Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	315759	0	0
entropy_period_rd_A	2147483647	2184	0	0
intr_enable_rd_A	2147483647	2526	0	0
prefix_0_rd_A	2147483647	1832	0	0
prefix_10_rd_A	2147483647	1888	0	0
prefix_1_rd_A	2147483647	1994	0	0
prefix_2_rd_A	2147483647	1908	0	0
prefix_3_rd_A	2147483647	2115	0	0
prefix_4_rd_A	2147483647	1810	0	0
prefix_5_rd_A	2147483647	1994	0	0
prefix_6_rd_A	2147483647	1795	0	0
prefix_7_rd_A	2147483647	1801	0	0
prefix_8_rd_A	2147483647	1868	0	0
prefix_9_rd_A	2147483647	1833	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	315759	0	0
T6	243597	0	0	0
T9	59156	0	0	0
T26	3136	0	0	0
T30	227776	29416	0	0
T38	29407	0	0	0
T45	0	96854	0	0
T46	0	68490	0	0
T61	21400	0	0	0
T62	608953	0	0	0
T63	967359	0	0	0
T64	169581	0	0	0
T65	9651	0	0	0
T68	0	48081	0	0
T93	0	1	0	0
T95	0	3	0	0
T100	0	31096	0	0
T101	0	7530	0	0
T102	0	31222	0	0
T103	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2184	0	0
T78	0	4	0	0
T87	0	9	0	0
T94	0	19	0	0
T95	0	64	0	0
T101	806844	52	0	0
T105	0	24	0	0
T113	0	7	0	0
T114	0	17	0	0
T115	0	9	0	0
T116	0	2	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2526	0	0
T78	0	2	0	0
T94	0	51	0	0
T95	0	70	0	0
T97	0	22	0	0
T98	0	3	0	0
T101	806844	33	0	0
T113	0	12	0	0
T114	0	11	0	0
T115	0	8	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0
T126	0	19	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1832	0	0
T78	0	14	0	0
T87	0	8	0	0
T94	0	17	0	0
T95	0	27	0	0
T101	806844	25	0	0
T105	0	16	0	0
T113	0	1	0	0
T114	0	4	0	0
T115	0	8	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0
T127	0	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1888	0	0
T78	0	1	0	0
T87	0	22	0	0
T94	0	32	0	0
T95	0	32	0	0
T101	806844	30	0	0
T105	0	19	0	0
T113	0	12	0	0
T114	0	16	0	0
T115	0	5	0	0
T116	0	5	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1994	0	0
T87	0	11	0	0
T94	0	14	0	0
T95	0	47	0	0
T99	0	3	0	0
T101	806844	61	0	0
T105	0	20	0	0
T113	0	5	0	0
T114	0	9	0	0
T115	0	6	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0
T128	0	453	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1908	0	0
T78	0	10	0	0
T94	0	18	0	0
T95	0	20	0	0
T101	806844	36	0	0
T105	0	21	0	0
T113	0	10	0	0
T114	0	7	0	0
T115	0	6	0	0
T116	0	3	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0
T127	0	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2115	0	0
T78	0	7	0	0
T87	0	17	0	0
T94	0	20	0	0
T95	0	53	0	0
T101	806844	22	0	0
T105	0	24	0	0
T113	0	7	0	0
T114	0	9	0	0
T115	0	5	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0
T127	0	12	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1810	0	0
T78	0	5	0	0
T94	0	16	0	0
T95	0	37	0	0
T101	806844	29	0	0
T105	0	21	0	0
T113	0	3	0	0
T114	0	9	0	0
T115	0	4	0	0
T116	0	6	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0
T127	0	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1994	0	0
T78	0	6	0	0
T87	0	6	0	0
T94	0	16	0	0
T95	0	39	0	0
T101	806844	54	0	0
T105	0	17	0	0
T113	0	4	0	0
T114	0	6	0	0
T115	0	7	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0
T127	0	2	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1795	0	0
T78	0	7	0	0
T87	0	14	0	0
T94	0	28	0	0
T95	0	36	0	0
T101	806844	16	0	0
T105	0	21	0	0
T113	0	2	0	0
T114	0	10	0	0
T115	0	5	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0
T127	0	8	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1801	0	0
T78	0	1	0	0
T87	0	15	0	0
T94	0	13	0	0
T95	0	37	0	0
T99	0	6	0	0
T101	806844	20	0	0
T105	0	20	0	0
T114	0	12	0	0
T115	0	2	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0
T129	0	48	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1868	0	0
T78	0	5	0	0
T94	0	33	0	0
T95	0	39	0	0
T101	806844	24	0	0
T105	0	11	0	0
T113	0	6	0	0
T114	0	6	0	0
T115	0	7	0	0
T116	0	2	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0
T127	0	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1833	0	0
T87	0	14	0	0
T94	0	10	0	0
T95	0	43	0	0
T101	806844	33	0	0
T105	0	25	0	0
T113	0	3	0	0
T114	0	11	0	0
T115	0	2	0	0
T116	0	3	0	0
T117	1320	0	0	0
T118	396111	0	0	0
T119	735466	0	0	0
T120	54567	0	0	0
T121	136982	0	0	0
T122	1301	0	0	0
T123	66769	0	0	0
T124	218230	0	0	0
T125	187662	0	0	0
T127	0	7	0	0