Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256247584

1

T1

585131

T2

40422

T3

561657

full_word

200126759

1

T1

359060

T2

65732

T3

359261

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	456374053	1			T1	944191		T2	106154		T3	920918
auto[TlIntgErrCmd]	104	1			T103	5		T104	8		T105	4
auto[TlIntgErrData]	85	1			T103	3		T104	6		T151	3
auto[TlIntgErrBoth]	101	1			T103	2		T104	6		T105	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240102939

1

T1

481513

T2

70680

T3

469879

auto[1]

216271404

1

T1

462678

T2

35474

T3

451039

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152783885	1			T1	344201		T2	24590		T3	335183
auto[TlIntgErrNone]	partial	auto[1]	103463439	1			T1	240930		T2	15832		T3	226474
auto[TlIntgErrNone]	full_word	auto[0]	87318933	1			T1	137312		T2	46090		T3	134696
auto[TlIntgErrNone]	full_word	auto[1]	112807796	1			T1	221748		T2	19642		T3	224565
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T103	2		T104	3		T105	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T103	3		T104	4		T105	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T104	1		T152	1		T153	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T151	1		T125	1		T152	1
auto[TlIntgErrData]	partial	auto[0]	32	1			T103	2		T104	1		T151	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T103	1		T104	4		T151	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T154	1		T155	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T104	1		T156	1		T157	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T103	1		T104	2		T105	4
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T103	1		T104	3		T105	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T125	1		T152	1		T156	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T104	1		T152	1		T154	1