Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	824557	0	0
entropy_period_rd_A	2147483647	1440	0	0
intr_enable_rd_A	2147483647	2061	0	0
prefix_0_rd_A	2147483647	1163	0	0
prefix_10_rd_A	2147483647	1208	0	0
prefix_1_rd_A	2147483647	1220	0	0
prefix_2_rd_A	2147483647	1113	0	0
prefix_3_rd_A	2147483647	1201	0	0
prefix_4_rd_A	2147483647	1228	0	0
prefix_5_rd_A	2147483647	1140	0	0
prefix_6_rd_A	2147483647	1183	0	0
prefix_7_rd_A	2147483647	1308	0	0
prefix_8_rd_A	2147483647	1192	0	0
prefix_9_rd_A	2147483647	1195	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	824557	0	0
T49	742707	106956	0	0
T56	0	28858	0	0
T57	0	19594	0	0
T63	24256	0	0	0
T76	0	29270	0	0
T118	0	45438	0	0
T119	0	50920	0	0
T120	0	198174	0	0
T121	0	28505	0	0
T122	0	50189	0	0
T123	0	56845	0	0
T124	456749	0	0	0
T125	198101	0	0	0
T126	607050	0	0	0
T127	410829	0	0	0
T128	176705	0	0	0
T129	185582	0	0	0
T130	7062	0	0	0
T131	162393	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1440	0	0
T57	230359	28	0	0
T76	0	99	0	0
T97	0	20	0	0
T104	0	17	0	0
T142	0	31	0	0
T143	0	34	0	0
T144	0	5	0	0
T145	0	14	0	0
T146	0	72	0	0
T147	0	4	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
T151	175367	0	0	0
T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2061	0	0
T57	230359	50	0	0
T76	0	95	0	0
T97	0	14	0	0
T104	0	47	0	0
T142	0	23	0	0
T143	0	32	0	0
T144	0	17	0	0
T145	0	8	0	0
T146	0	85	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
T151	175367	0	0	0
T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0
T157	0	34	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1163	0	0
T57	230359	12	0	0
T76	0	89	0	0
T97	0	13	0	0
T104	0	9	0	0
T142	0	96	0	0
T143	0	40	0	0
T144	0	8	0	0
T145	0	1	0	0
T146	0	45	0	0
T147	0	12	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
T151	175367	0	0	0
T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1208	0	0
T57	230359	36	0	0
T76	0	60	0	0
T97	0	14	0	0
T104	0	21	0	0
T142	0	56	0	0
T143	0	42	0	0
T144	0	6	0	0
T145	0	4	0	0
T146	0	37	0	0
T147	0	9	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
T151	175367	0	0	0
T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1220	0	0
T57	230359	26	0	0
T76	0	80	0	0
T97	0	23	0	0
T104	0	18	0	0
T142	0	36	0	0
T143	0	22	0	0
T144	0	2	0	0
T145	0	14	0	0
T146	0	32	0	0
T147	0	4	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
T151	175367	0	0	0
T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1113	0	0
T57	230359	26	0	0
T76	0	50	0	0
T97	0	12	0	0
T104	0	29	0	0
T142	0	7	0	0
T143	0	37	0	0
T144	0	10	0	0
T145	0	9	0	0
T146	0	36	0	0
T147	0	7	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
T151	175367	0	0	0
T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1201	0	0
T57	230359	35	0	0
T76	0	119	0	0
T97	0	15	0	0
T102	0	4	0	0
T104	0	27	0	0
T142	0	10	0	0
T143	0	31	0	0
T145	0	7	0	0
T146	0	38	0	0
T147	0	6	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
T151	175367	0	0	0
T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1228	0	0
T57	230359	43	0	0
T76	0	68	0	0
T97	0	11	0	0
T104	0	22	0	0
T142	0	29	0	0
T143	0	77	0	0
T144	0	4	0	0
T145	0	8	0	0
T146	0	39	0	0
T147	0	7	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
T151	175367	0	0	0
T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1140	0	0
T57	230359	36	0	0
T76	0	134	0	0
T97	0	9	0	0
T104	0	24	0	0
T142	0	18	0	0
T143	0	46	0	0
T144	0	2	0	0
T145	0	10	0	0
T146	0	47	0	0
T147	0	4	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
T151	175367	0	0	0
T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1183	0	0
T57	230359	38	0	0
T76	0	76	0	0
T97	0	23	0	0
T104	0	14	0	0
T142	0	12	0	0
T143	0	58	0	0
T144	0	2	0	0
T145	0	6	0	0
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T147	0	11	0	0
T148	511644	0	0	0
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T150	785134	0	0	0
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T152	6775	0	0	0
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T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1308	0	0
T57	230359	46	0	0
T76	0	68	0	0
T97	0	19	0	0
T104	0	20	0	0
T142	0	97	0	0
T143	0	21	0	0
T144	0	14	0	0
T145	0	10	0	0
T146	0	38	0	0
T147	0	5	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
T151	175367	0	0	0
T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1192	0	0
T57	230359	29	0	0
T76	0	81	0	0
T97	0	17	0	0
T104	0	23	0	0
T142	0	41	0	0
T143	0	29	0	0
T144	0	9	0	0
T145	0	18	0	0
T146	0	36	0	0
T147	0	11	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
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T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1195	0	0
T57	230359	35	0	0
T76	0	151	0	0
T97	0	14	0	0
T104	0	25	0	0
T142	0	34	0	0
T143	0	32	0	0
T144	0	6	0	0
T145	0	11	0	0
T146	0	35	0	0
T147	0	14	0	0
T148	511644	0	0	0
T149	316015	0	0	0
T150	785134	0	0	0
T151	175367	0	0	0
T152	6775	0	0	0
T153	6990	0	0	0
T154	145053	0	0	0
T155	266863	0	0	0
T156	184374	0	0	0