Module Definition
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Module : sha3pad_assert_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sha3pad_assert_cov_if 100.00 100.00



Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sha3pad_assert_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ProcessToRun_A 2147483647 349854 0 0
RunThenComplete_M 2147483647 3093886 0 0


ProcessToRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 349854 0 0
T1 216070 2265 0 0
T2 218171 2265 0 0
T3 649052 390 0 0
T12 176295 35 0 0
T13 695637 310 0 0
T14 892523 112 0 0
T15 927456 374 0 0
T16 186649 390 0 0
T17 0 390 0 0
T18 0 562 0 0
T19 1417 0 0 0
T20 855 0 0 0

RunThenComplete_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 3093886 0 0
T1 216070 12979 0 0
T2 218171 12979 0 0
T3 649052 5542 0 0
T12 176295 197 0 0
T13 695637 5462 0 0
T14 892523 609 0 0
T15 927456 5526 0 0
T16 186649 5542 0 0
T17 0 5542 0 0
T18 0 9945 0 0
T19 1417 0 0 0
T20 855 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%