Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : kmac
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.19 96.27 93.33 63.67 100.00 93.85 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 97.24 96.27 93.33 100.00 100.00 93.85 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.24 96.27 93.33 100.00 100.00 93.85 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.93 96.18 92.44 100.00 87.50 94.60 98.84


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
intr_fifo_empty 86.94 90.00 77.78 80.00 100.00
intr_kmac_done 93.75 100.00 75.00 100.00 100.00
intr_kmac_err 93.75 100.00 75.00 100.00 100.00
kmac_csr_assert 100.00 100.00
sha3pad_assert_cov_if 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_app_intf 93.01 94.07 89.80 88.24 92.94 100.00
u_errchk 95.99 97.14 96.67 90.00 96.15 100.00
u_kmac_core 95.80 98.75 92.86 100.00 100.00 92.31 90.91
u_msgfifo 97.75 100.00 95.00 100.00 93.75 100.00
u_prim_lc_sync 100.00 100.00 100.00 100.00
u_reg 98.98 99.21 96.90 100.00 98.78 100.00
u_sha3 91.70 91.91 88.51 100.00 77.78 92.00 100.00
u_sha3_done_sender 100.00 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_staterd 89.93 89.80 81.39 88.54 100.00
u_tlul_adapter_msgfifo 79.91 87.01 74.59 77.38 80.65

Line Coverage for Module : kmac
Line No.TotalCoveredPercent
TOTAL16115596.27
ALWAYS34300
ALWAYS34322100.00
ALWAYS349100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN42311100.00
ALWAYS42699100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN46611100.00
CONT_ASSIGN47011100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47811100.00
ALWAYS48566100.00
CONT_ASSIGN51011100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN52211100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52611100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53400
CONT_ASSIGN53611100.00
CONT_ASSIGN54011100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54311100.00
CONT_ASSIGN54611100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN55011100.00
ALWAYS55855100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN57511100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN57711100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN62711100.00
CONT_ASSIGN63311100.00
CONT_ASSIGN64111100.00
CONT_ASSIGN64611100.00
ALWAYS64955100.00
CONT_ASSIGN67811100.00
CONT_ASSIGN68311100.00
ALWAYS6867571.43
CONT_ASSIGN72211100.00
CONT_ASSIGN727100.00
CONT_ASSIGN73411100.00
CONT_ASSIGN74411100.00
ALWAYS76433100.00
ALWAYS7682828100.00
CONT_ASSIGN91811100.00
CONT_ASSIGN92111100.00
CONT_ASSIGN99011100.00
CONT_ASSIGN99211100.00
CONT_ASSIGN102311100.00
CONT_ASSIGN102811100.00
CONT_ASSIGN102911100.00
CONT_ASSIGN103111100.00
CONT_ASSIGN103400
ALWAYS115200
ALWAYS115222100.00
CONT_ASSIGN1305100.00
CONT_ASSIGN130611100.00
CONT_ASSIGN130711100.00
CONT_ASSIGN131711100.00
CONT_ASSIGN131811100.00
CONT_ASSIGN132411100.00
CONT_ASSIGN132511100.00
CONT_ASSIGN132611100.00
CONT_ASSIGN132711100.00
CONT_ASSIGN133011100.00
CONT_ASSIGN133911100.00
CONT_ASSIGN138111100.00
CONT_ASSIGN139511100.00
CONT_ASSIGN140211100.00
CONT_ASSIGN140711100.00
ALWAYS14136583.33
CONT_ASSIGN142211100.00
CONT_ASSIGN142411100.00
ALWAYS143644100.00
CONT_ASSIGN144211100.00
ALWAYS146544100.00
ALWAYS147533100.00
CONT_ASSIGN148611100.00
CONT_ASSIGN149011100.00
CONT_ASSIGN149211100.00
CONT_ASSIGN149211100.00
CONT_ASSIGN149211100.00
CONT_ASSIGN149211100.00
CONT_ASSIGN149211100.00
CONT_ASSIGN149211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
343 1 1
344 1 1
349 0 1
418 1 1
419 1 1
423 1 1
426 1 1
427 1 1
428 1 1
429 1 1
431 1 1
433 1 1
437 1 1
441 1 1
445 1 1
461 1 1
462 1 1
463 1 1
466 1 1
470 1 1
471 1 1
475 1 1
478 1 1
485 1 1
486 1 1
487 1 1
488 1 1
489 1 1
490 1 1
MISSING_ELSE
MISSING_ELSE
510 1 1
515 1 1
522 1 1
525 1 1
526 1 1
527 1 1
529 1 1
530 1 1
532 1 1
534 unreachable
536 1 1
540 1 1
542 1 1
543 1 1
546 1 1
547 1 1
550 1 1
558 1 1
559 1 1
560 1 1
561 1 1
563 1 1
568 1 1
575 1 1
576 1 1
577 1 1
585 1 1
627 1 1
633 1 1
641 1 1
646 1 1
649 1 1
650 1 1
651 1 1
653 1 1
654 1 1
678 1 1
683 1 1
686 1 1
688 1 1
693 1 1
697 1 1
701 1 1
705 0 1
709 0 1
722 1 1
727 0 1
734 1 1
744 1 1
764 3 3
768 1 1
770 1 1
771 1 1
773 1 1
775 1 1
777 1 1
778 1 1
781 1 1
784 1 1
790 1 1
791 1 1
793 1 1
798 1 1
799 1 1
800 1 1
802 1 1
808 1 1
813 1 1
814 1 1
816 1 1
818 1 1
824 1 1
825 1 1
827 1 1
833 1 1
834 1 1
846 1 1
847 1 1
MISSING_ELSE
918 1 1
921 1 1
990 1 1
992 1 1
1023 1 1
1028 1 1
1029 1 1
1031 1 1
1034 unreachable
1152 1 1
1153 1 1
1305 0 1
1306 1 1
1307 1 1
1317 1 1
1318 1 1
1324 1 1
1325 1 1
1326 1 1
1327 1 1
1330 1 1
1339 1 1
1381 1 1
1395 1 1
1402 1 1
1407 1 1
1413 1 1
1414 1 1
1415 1 1
1416 0 1
1417 1 1
1418 1 1
MISSING_ELSE
1422 1 1
1424 1 1
1436 1 1
1437 1 1
1438 1 1
1439 1 1
MISSING_ELSE
1442 1 1
1465 1 1
1466 1 1
1467 1 1
1469 1 1
MISSING_ELSE
1475 1 1
1476 1 1
1479 1 1
1486 1 1
1490 1 1
1492 6 6


Cond Coverage for Module : kmac
TotalCoveredPercent
Conditions908493.33
Logical908493.33
Non-Logical00
Event00

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T18,T33

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T18,T33

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------
-1--2-StatusTests
01CoveredT47,T21,T22
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT12,T14,T16
111CoveredT1,T2,T3

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T22,T23
11CoveredT21,T22,T23

 LINE       627
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------
-1--2-StatusTests
01CoveredT3,T12,T14
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       633
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T31,T50

 LINE       633
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       633
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       641
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T18,T24

 LINE       641
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       641
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       641
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       646
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------
-1-StatusTests
0CoveredT32,T49,T28
1CoveredT1,T2,T3

 LINE       678
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT14,T24,T35
0010Not Covered
0100CoveredT14,T24,T4
1000CoveredT28,T29,T30

 LINE       722
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010CoveredT9,T10,T11
0100Unreachable
1000CoveredT9,T10,T11

 LINE       734
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001CoveredT9,T10,T11
000010Unreachable
000100CoveredT9,T10,T11
001000CoveredT9,T10,T11
010000CoveredT9,T10,T11
100000CoveredT9,T10,T11

 LINE       775
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       777
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T14,T18

 LINE       791
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----
-1-StatusTests
0CoveredT12,T18,T24
1CoveredT12,T14,T18

 LINE       1023
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       1153
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1395
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------
-1--2-StatusTests
01CoveredT19,T20,T45
10CoveredT1,T2,T3
11CoveredT19,T20,T45

 LINE       1395
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------
-1--2-StatusTests
01CoveredT19,T20,T45
10CoveredT1,T2,T3
11CoveredT19,T20,T45

 LINE       1424
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010CoveredT9,T10,T11
00100CoveredT4,T5,T6
01000CoveredT9,T10,T11
10000Not Covered

Toggle Coverage for Module : kmac
TotalCoveredPercent
Totals 71 64 90.14
Total Bits 6534 4160 63.67
Total Bits 0->1 3267 2080 63.67
Total Bits 1->0 3267 2080 63.67

Ports 71 64 90.14
Port Bits 6534 4160 63.67
Port Bits 0->1 3267 2080 63.67
Port Bits 1->0 3267 2080 63.67

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T18,T4,T5 Yes T1,T2,T3 INPUT
rst_shadowed_ni Yes Yes T18,T4,T5 Yes T1,T2,T3 INPUT
clk_edn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_edn_ni Yes Yes T18,T4,T5 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T24,T35,T51 Yes T24,T35,T51 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T52,T53,T54 Yes T52,T53,T54 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T19,T20,T45 Yes T19,T20,T45 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T19,T20,T45 Yes T19,T20,T45 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T19,T20,T45 Yes T19,T20,T45 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T19,T20,T45 Yes T19,T20,T45 OUTPUT
keymgr_key_i.key[0][255:0] Yes Yes T12,T14,T18 Yes T12,T14,T18 INPUT
keymgr_key_i.key[1][39:0] Yes Yes T12,T14,T18 Yes T12,T14,T18 INPUT
keymgr_key_i.key[1][40] Yes Yes T14,T18,T24 Yes T14,T18,T24 INPUT
keymgr_key_i.key[1][255:41] Yes Yes T12,T14,T18 Yes T12,T14,T18 INPUT
keymgr_key_i.valid Yes Yes T12,T14,T18 Yes T12,T14,T18 INPUT
app_i[0].last Yes Yes T18,T24,T33 Yes T12,T18,T24 INPUT
app_i[0].strb[7:0] Yes Yes T12,T18,T33 Yes T12,T18,T33 INPUT
app_i[0].data[63:0] Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_i[0].valid Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_i[1].last Yes Yes T12,T18,T33 Yes T12,T18,T24 INPUT
app_i[1].strb[7:0] Yes Yes T12,T18,T33 Yes T12,T18,T33 INPUT
app_i[1].data[63:0] Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_i[1].valid Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_i[2].last Yes Yes T12,T18,T33 Yes T12,T18,T24 INPUT
app_i[2].strb[7:0] Yes Yes T12,T18,T33 Yes T12,T18,T33 INPUT
app_i[2].data[63:0] Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_i[2].valid Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_o[0].error Yes Yes T4,T6,T8 Yes T4,T6,T8 OUTPUT
app_o[0].digest_share1[383:0] No No No OUTPUT
app_o[0].digest_share0[383:0] Yes Yes T18,T33,T35 Yes T18,T33,T35 OUTPUT
app_o[0].done Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[0].ready Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[1].error Yes Yes T37,T28,T29 Yes T37,T28,T29 OUTPUT
app_o[1].digest_share1[383:0] No No No OUTPUT
app_o[1].digest_share0[383:0] Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[1].done Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[1].ready Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[2].error Yes Yes T5,T28,T29 Yes T5,T28,T29 OUTPUT
app_o[2].digest_share1[383:0] No No No OUTPUT
app_o[2].digest_share0[383:0] Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[2].done Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[2].ready Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
entropy_o.edn_req No No No OUTPUT
entropy_i.edn_bus[31:0] No No No INPUT
entropy_i.edn_fips No No No INPUT
entropy_i.edn_ack No No No INPUT
lc_escalate_en_i[3:0] Yes Yes T4,T5,T40 Yes T4,T5,T40 INPUT
intr_kmac_done_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_fifo_empty_o Yes Yes T32,T49,T28 Yes T32,T49,T28 OUTPUT
intr_kmac_err_o Yes Yes T14,T24,T4 Yes T14,T24,T4 OUTPUT
en_masking_o Unreachable Unreachable Unreachable OUTPUT
idle_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

FSM Coverage for Module : kmac
Summary for FSM :: kmac_st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 13 13 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: kmac_st
statesLine No.CoveredTests
KmacDigest 816 Covered T1,T2,T3
KmacIdle 784 Covered T1,T2,T3
KmacKeyBlock 791 Covered T12,T14,T18
KmacMsgFeed 781 Covered T1,T2,T3
KmacPrefix 778 Covered T12,T14,T18
KmacTerminalError 833 Covered T4,T5,T6


transitionsLine No.CoveredTests
KmacDigest->KmacIdle 825 Covered T1,T2,T3
KmacDigest->KmacTerminalError 847 Covered T55,T56,T57
KmacIdle->KmacMsgFeed 781 Covered T1,T2,T3
KmacIdle->KmacPrefix 778 Covered T12,T14,T18
KmacIdle->KmacTerminalError 847 Covered T9,T38,T39
KmacKeyBlock->KmacMsgFeed 800 Covered T12,T14,T18
KmacKeyBlock->KmacTerminalError 847 Covered T6,T58,T59
KmacMsgFeed->KmacDigest 816 Covered T1,T2,T3
KmacMsgFeed->KmacIdle 813 Covered T12,T18,T24
KmacMsgFeed->KmacTerminalError 847 Covered T4,T8,T37
KmacPrefix->KmacKeyBlock 791 Covered T12,T14,T18
KmacPrefix->KmacMsgFeed 791 Covered T12,T18,T24
KmacPrefix->KmacTerminalError 847 Covered T5,T60,T7



Branch Coverage for Module : kmac
Line No.TotalCoveredPercent
Branches 65 61 93.85
TERNARY 423 2 2 100.00
TERNARY 633 4 4 100.00
TERNARY 641 4 4 100.00
TERNARY 646 2 2 100.00
CASE 431 6 5 83.33
IF 485 3 3 100.00
IF 558 3 3 100.00
IF 649 2 2 100.00
CASE 688 6 4 66.67
IF 764 2 2 100.00
CASE 773 15 15 100.00
IF 846 2 2 100.00
TERNARY 1153 2 2 100.00
IF 1413 4 3 75.00
IF 1436 3 3 100.00
IF 1465 3 3 100.00
IF 1475 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 423 (cmd_update) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 633 (msgfifo_full) ? -2-: 633 (msgfifo_empty_negedge) ? -3-: 633 (msgfifo2kmac_process) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T18,T31,T50
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 641 (app_active) ? -2-: 641 ((sha3_fsm != StAbsorb)) ? -3-: 641 (msgfifo2kmac_process) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T12,T18,T24
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 646 (msgfifo_empty_gate) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T32,T49,T28


LineNo. Expression -1-: 431 case (kmac_cmd)

Branches:
-1-StatusTests
CmdStart Covered T1,T2,T3
CmdProcess Covered T1,T2,T3
CmdManualRun Covered T1,T2,T12
CmdDone Covered T1,T2,T3
CmdNone Covered T1,T2,T3
default Not Covered


LineNo. Expression -1-: 485 if ((!rst_ni)) -2-: 487 if (engine_stable)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 558 if ((!rst_ni)) -2-: 560 if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 649 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 688 case (1'b1)

Branches:
-1-StatusTests
app_err.valid Covered T14,T24,T4
errchecker_err.valid Covered T14,T24,T35
sha3_err.valid Covered T28,T29,T30
entropy_err.valid Not Covered
msgfifo_err.valid Not Covered
default Covered T1,T2,T3


LineNo. Expression -1-: 764 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 773 case (kmac_st) -2-: 775 if ((kmac_cmd == CmdStart)) -3-: 777 if ((CShake == app_sha3_mode)) -4-: 790 if (sha3_block_processed) -5-: 791 (app_kmac_en) ? -6-: 799 if (sha3_block_processed) -7-: 808 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done))) -8-: 814 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done))) -9-: 824 if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
KmacIdle 1 1 - - - - - - Covered T12,T14,T18
KmacIdle 1 0 - - - - - - Covered T1,T2,T3
KmacIdle 0 - - - - - - - Covered T1,T2,T3
KmacPrefix - - 1 1 - - - - Covered T12,T14,T18
KmacPrefix - - 1 0 - - - - Covered T12,T18,T24
KmacPrefix - - 0 - - - - - Covered T12,T14,T18
KmacKeyBlock - - - - 1 - - - Covered T12,T14,T18
KmacKeyBlock - - - - 0 - - - Covered T12,T14,T18
KmacMsgFeed - - - - - 1 - - Covered T12,T18,T24
KmacMsgFeed - - - - - 0 1 - Covered T1,T2,T3
KmacMsgFeed - - - - - 0 0 - Covered T1,T2,T3
KmacDigest - - - - - - - 1 Covered T1,T2,T3
KmacDigest - - - - - - - 0 Covered T1,T2,T3
KmacTerminalError - - - - - - - - Covered T4,T5,T6
default - - - - - - - - Covered T9,T10,T11


LineNo. Expression -1-: 846 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 1153 (reg_state_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 1413 if ((!rst_ni)) -2-: 1415 if (alert_recov_operation) -3-: 1417 if (err_processed)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Covered T21,T22,T23
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1436 if ((!rst_ni)) -2-: 1438 if (alert_fatal)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T5,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1465 if ((!rst_ni)) -2-: 1467 if (alerts[1])

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T5,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1475 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : kmac
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 30 30 100.00 30 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 30 30 100.00 30 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 2147483647 2147483647 0 0
CmdSparse_M 2147483647 1290995 0 0
EnMaskingKnown_A 2147483647 2147483647 0 0
EntropyReadyLatched_A 2147483647 340157 0 0
EntrySizeRegSameToEntrySizePkg_A 1031 1031 0 0
ErrProcessedLatched_A 2147483647 517 0 0
FifoEmpty_A 2147483647 2147483647 0 0
FpvSecCmErrorCheckFsmCheck_A 2147483647 70 0 0
FpvSecCmKeccackFsmCheck_A 2147483647 70 0 0
FpvSecCmKeyIndexCountCheck_A 2147483647 70 0 0
FpvSecCmKmacAppFsmCheck_A 2147483647 70 0 0
FpvSecCmKmacCoreFsmCheck_A 2147483647 70 0 0
FpvSecCmKmacFsmCheck_A 2147483647 70 0 0
FpvSecCmRegWeOnehotCheck_A 2147483647 70 0 0
FpvSecCmRoundCountCheck_A 2147483647 70 0 0
FpvSecCmSHA3FsmCheck_A 2147483647 70 0 0
FpvSecCmSHA3padFsmCheck_A 2147483647 70 0 0
FpvSecCmSentMsgCountCheck_A 2147483647 70 0 0
KmacCmd_A 2147483647 2147483647 0 0
KmacDone_A 2147483647 2147483647 0 0
KmacErr_A 2147483647 2147483647 0 0
KmacStKnown_A 2147483647 2147483647 0 0
NumAlerts2_A 1031 1031 0 0
NumEntriesRegSameToNumEntriesPkg_A 1031 1031 0 0
PrefixRegSameToPrefixPkg_A 1031 1031 0 0
SecretKeyDivideBy32_A 1031 1031 0 0
Sha3AbsorbedPulse_A 2147483647 349853 0 0
TlOAReadyKnown_A 2147483647 2147483647 0 0
TlODValidKnown_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

CmdSparse_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1290995 0 0
T1 216070 7944 0 0
T2 218171 7927 0 0
T3 649052 1243 0 0
T12 176295 156 0 0
T13 695637 987 0 0
T14 892523 857 0 0
T15 927456 1201 0 0
T16 186649 1255 0 0
T17 0 1248 0 0
T18 0 3296 0 0
T19 1417 0 0 0
T20 855 0 0 0

EnMaskingKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

EntropyReadyLatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 340157 0 0
T1 216070 2184 0 0
T2 218171 2185 0 0
T3 649052 381 0 0
T12 176295 35 0 0
T13 695637 301 0 0
T14 892523 124 0 0
T15 927456 364 0 0
T16 186649 377 0 0
T17 0 377 0 0
T18 0 558 0 0
T19 1417 0 0 0
T20 855 0 0 0

EntrySizeRegSameToEntrySizePkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

ErrProcessedLatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 517 0 0
T21 16201 4 0 0
T22 0 14 0 0
T23 0 13 0 0
T29 561594 0 0 0
T52 373572 0 0 0
T61 0 7 0 0
T62 0 17 0 0
T63 0 2 0 0
T64 0 1 0 0
T65 0 15 0 0
T66 0 7 0 0
T67 0 17 0 0
T68 190818 0 0 0
T69 123183 0 0 0
T70 132630 0 0 0
T71 968375 0 0 0
T72 226512 0 0 0
T73 590843 0 0 0
T74 195850 0 0 0

FifoEmpty_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

FpvSecCmErrorCheckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmKeccackFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmKeyIndexCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmKmacAppFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmKmacCoreFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmKmacFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmRoundCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmSHA3FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmSHA3padFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmSentMsgCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

KmacCmd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

KmacDone_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

KmacErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

KmacStKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

NumAlerts2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

NumEntriesRegSameToNumEntriesPkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PrefixRegSameToPrefixPkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

SecretKeyDivideBy32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Sha3AbsorbedPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 349853 0 0
T1 216070 2265 0 0
T2 218171 2265 0 0
T3 649052 390 0 0
T12 176295 35 0 0
T13 695637 310 0 0
T14 892523 112 0 0
T15 927456 374 0 0
T16 186649 390 0 0
T17 0 390 0 0
T18 0 562 0 0
T19 1417 0 0 0
T20 855 0 0 0

TlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

TlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL16115596.27
ALWAYS34300
ALWAYS34322100.00
ALWAYS349100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN42311100.00
ALWAYS42699100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN46611100.00
CONT_ASSIGN47011100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47811100.00
ALWAYS48566100.00
CONT_ASSIGN51011100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN52211100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52611100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53400
CONT_ASSIGN53611100.00
CONT_ASSIGN54011100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54311100.00
CONT_ASSIGN54611100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN55011100.00
ALWAYS55855100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN57511100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN57711100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN62711100.00
CONT_ASSIGN63311100.00
CONT_ASSIGN64111100.00
CONT_ASSIGN64611100.00
ALWAYS64955100.00
CONT_ASSIGN67811100.00
CONT_ASSIGN68311100.00
ALWAYS6867571.43
CONT_ASSIGN72211100.00
CONT_ASSIGN727100.00
CONT_ASSIGN73411100.00
CONT_ASSIGN74411100.00
ALWAYS76433100.00
ALWAYS7682828100.00
CONT_ASSIGN91811100.00
CONT_ASSIGN92111100.00
CONT_ASSIGN99011100.00
CONT_ASSIGN99211100.00
CONT_ASSIGN102311100.00
CONT_ASSIGN102811100.00
CONT_ASSIGN102911100.00
CONT_ASSIGN103111100.00
CONT_ASSIGN103400
ALWAYS115200
ALWAYS115222100.00
CONT_ASSIGN1305100.00
CONT_ASSIGN130611100.00
CONT_ASSIGN130711100.00
CONT_ASSIGN131711100.00
CONT_ASSIGN131811100.00
CONT_ASSIGN132411100.00
CONT_ASSIGN132511100.00
CONT_ASSIGN132611100.00
CONT_ASSIGN132711100.00
CONT_ASSIGN133011100.00
CONT_ASSIGN133911100.00
CONT_ASSIGN138111100.00
CONT_ASSIGN139511100.00
CONT_ASSIGN140211100.00
CONT_ASSIGN140711100.00
ALWAYS14136583.33
CONT_ASSIGN142211100.00
CONT_ASSIGN142411100.00
ALWAYS143644100.00
CONT_ASSIGN144211100.00
ALWAYS146544100.00
ALWAYS147533100.00
CONT_ASSIGN148611100.00
CONT_ASSIGN149011100.00
CONT_ASSIGN149211100.00
CONT_ASSIGN149211100.00
CONT_ASSIGN149211100.00
CONT_ASSIGN149211100.00
CONT_ASSIGN149211100.00
CONT_ASSIGN149211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
343 1 1
344 1 1
349 0 1
418 1 1
419 1 1
423 1 1
426 1 1
427 1 1
428 1 1
429 1 1
431 1 1
433 1 1
437 1 1
441 1 1
445 1 1
461 1 1
462 1 1
463 1 1
466 1 1
470 1 1
471 1 1
475 1 1
478 1 1
485 1 1
486 1 1
487 1 1
488 1 1
489 1 1
490 1 1
MISSING_ELSE
MISSING_ELSE
510 1 1
515 1 1
522 1 1
525 1 1
526 1 1
527 1 1
529 1 1
530 1 1
532 1 1
534 unreachable
536 1 1
540 1 1
542 1 1
543 1 1
546 1 1
547 1 1
550 1 1
558 1 1
559 1 1
560 1 1
561 1 1
563 1 1
568 1 1
575 1 1
576 1 1
577 1 1
585 1 1
627 1 1
633 1 1
641 1 1
646 1 1
649 1 1
650 1 1
651 1 1
653 1 1
654 1 1
678 1 1
683 1 1
686 1 1
688 1 1
693 1 1
697 1 1
701 1 1
705 0 1
709 0 1
722 1 1
727 0 1
734 1 1
744 1 1
764 3 3
768 1 1
770 1 1
771 1 1
773 1 1
775 1 1
777 1 1
778 1 1
781 1 1
784 1 1
790 1 1
791 1 1
793 1 1
798 1 1
799 1 1
800 1 1
802 1 1
808 1 1
813 1 1
814 1 1
816 1 1
818 1 1
824 1 1
825 1 1
827 1 1
833 1 1
834 1 1
846 1 1
847 1 1
MISSING_ELSE
918 1 1
921 1 1
990 1 1
992 1 1
1023 1 1
1028 1 1
1029 1 1
1031 1 1
1034 unreachable
1152 1 1
1153 1 1
1305 0 1
1306 1 1
1307 1 1
1317 1 1
1318 1 1
1324 1 1
1325 1 1
1326 1 1
1327 1 1
1330 1 1
1339 1 1
1381 1 1
1395 1 1
1402 1 1
1407 1 1
1413 1 1
1414 1 1
1415 1 1
1416 0 1
1417 1 1
1418 1 1
MISSING_ELSE
1422 1 1
1424 1 1
1436 1 1
1437 1 1
1438 1 1
1439 1 1
MISSING_ELSE
1442 1 1
1465 1 1
1466 1 1
1467 1 1
1469 1 1
MISSING_ELSE
1475 1 1
1476 1 1
1479 1 1
1486 1 1
1490 1 1
1492 6 6


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions908493.33
Logical908493.33
Non-Logical00
Event00

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T18,T33

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T18,T33

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------
-1--2-StatusTests
01CoveredT47,T21,T22
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT12,T14,T16
111CoveredT1,T2,T3

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T22,T23
11CoveredT21,T22,T23

 LINE       627
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------
-1--2-StatusTests
01CoveredT3,T12,T14
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       633
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T31,T50

 LINE       633
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       633
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       641
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T18,T24

 LINE       641
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       641
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       641
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       646
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------
-1-StatusTests
0CoveredT32,T49,T28
1CoveredT1,T2,T3

 LINE       678
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT14,T24,T35
0010Not Covered
0100CoveredT14,T24,T4
1000CoveredT28,T29,T30

 LINE       722
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010CoveredT9,T10,T11
0100Unreachable
1000CoveredT9,T10,T11

 LINE       734
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001CoveredT9,T10,T11
000010Unreachable
000100CoveredT9,T10,T11
001000CoveredT9,T10,T11
010000CoveredT9,T10,T11
100000CoveredT9,T10,T11

 LINE       775
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       777
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T14,T18

 LINE       791
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----
-1-StatusTests
0CoveredT12,T18,T24
1CoveredT12,T14,T18

 LINE       1023
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       1153
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1395
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------
-1--2-StatusTests
01CoveredT19,T20,T45
10CoveredT1,T2,T3
11CoveredT19,T20,T45

 LINE       1395
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------
-1--2-StatusTests
01CoveredT19,T20,T45
10CoveredT1,T2,T3
11CoveredT19,T20,T45

 LINE       1424
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010CoveredT9,T10,T11
00100CoveredT4,T5,T6
01000CoveredT9,T10,T11
10000Not Covered

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 64 64 100.00
Total Bits 4160 4160 100.00
Total Bits 0->1 2080 2080 100.00
Total Bits 1->0 2080 2080 100.00

Ports 64 64 100.00
Port Bits 4160 4160 100.00
Port Bits 0->1 2080 2080 100.00
Port Bits 1->0 2080 2080 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T18,T4,T5 Yes T1,T2,T3 INPUT
rst_shadowed_ni Yes Yes T18,T4,T5 Yes T1,T2,T3 INPUT
clk_edn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_edn_ni Yes Yes T18,T4,T5 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T24,T35,T51 Yes T24,T35,T51 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T52,T53,T54 Yes T52,T53,T54 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T19,T20,T45 Yes T19,T20,T45 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T19,T20,T45 Yes T19,T20,T45 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T19,T20,T45 Yes T19,T20,T45 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T19,T20,T45 Yes T19,T20,T45 OUTPUT
keymgr_key_i.key[0][255:0] Yes Yes T12,T14,T18 Yes T12,T14,T18 INPUT
keymgr_key_i.key[1][39:0] Yes Yes T12,T14,T18 Yes T12,T14,T18 INPUT
keymgr_key_i.key[1][40] Yes Yes T14,T18,T24 Yes T14,T18,T24 INPUT
keymgr_key_i.key[1][255:41] Yes Yes T12,T14,T18 Yes T12,T14,T18 INPUT
keymgr_key_i.valid Yes Yes T12,T14,T18 Yes T12,T14,T18 INPUT
app_i[0].last Yes Yes T18,T24,T33 Yes T12,T18,T24 INPUT
app_i[0].strb[7:0] Yes Yes T12,T18,T33 Yes T12,T18,T33 INPUT
app_i[0].data[63:0] Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_i[0].valid Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_i[1].last Yes Yes T12,T18,T33 Yes T12,T18,T24 INPUT
app_i[1].strb[7:0] Yes Yes T12,T18,T33 Yes T12,T18,T33 INPUT
app_i[1].data[63:0] Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_i[1].valid Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_i[2].last Yes Yes T12,T18,T33 Yes T12,T18,T24 INPUT
app_i[2].strb[7:0] Yes Yes T12,T18,T33 Yes T12,T18,T33 INPUT
app_i[2].data[63:0] Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_i[2].valid Yes Yes T12,T18,T24 Yes T12,T18,T24 INPUT
app_o[0].error Yes Yes T4,T6,T8 Yes T4,T6,T8 OUTPUT
app_o[0].digest_share1[383:0] Excluded Excluded Excluded OUTPUT [UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0] Yes Yes T18,T33,T35 Yes T18,T33,T35 OUTPUT
app_o[0].done Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[0].ready Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[1].error Yes Yes T37,T28,T29 Yes T37,T28,T29 OUTPUT
app_o[1].digest_share1[383:0] Excluded Excluded Excluded OUTPUT [UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0] Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[1].done Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[1].ready Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[2].error Yes Yes T5,T28,T29 Yes T5,T28,T29 OUTPUT
app_o[2].digest_share1[383:0] Excluded Excluded Excluded OUTPUT [UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0] Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[2].done Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
app_o[2].ready Yes Yes T12,T18,T24 Yes T12,T18,T24 OUTPUT
entropy_o.edn_req[0:0] Excluded Excluded Excluded OUTPUT [UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0] Excluded Excluded Excluded INPUT [UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0] Excluded Excluded Excluded INPUT [UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0] Excluded Excluded Excluded INPUT [UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0] Yes Yes T4,T5,T40 Yes T4,T5,T40 INPUT
intr_kmac_done_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_fifo_empty_o Yes Yes T32,T49,T28 Yes T32,T49,T28 OUTPUT
intr_kmac_err_o Yes Yes T14,T24,T4 Yes T14,T24,T4 OUTPUT
en_masking_o Unreachable Unreachable Unreachable OUTPUT
idle_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

FSM Coverage for Instance : tb.dut
Summary for FSM :: kmac_st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 13 13 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: kmac_st
statesLine No.CoveredTests
KmacDigest 816 Covered T1,T2,T3
KmacIdle 784 Covered T1,T2,T3
KmacKeyBlock 791 Covered T12,T14,T18
KmacMsgFeed 781 Covered T1,T2,T3
KmacPrefix 778 Covered T12,T14,T18
KmacTerminalError 833 Covered T4,T5,T6


transitionsLine No.CoveredTests
KmacDigest->KmacIdle 825 Covered T1,T2,T3
KmacDigest->KmacTerminalError 847 Covered T55,T56,T57
KmacIdle->KmacMsgFeed 781 Covered T1,T2,T3
KmacIdle->KmacPrefix 778 Covered T12,T14,T18
KmacIdle->KmacTerminalError 847 Covered T9,T38,T39
KmacKeyBlock->KmacMsgFeed 800 Covered T12,T14,T18
KmacKeyBlock->KmacTerminalError 847 Covered T6,T58,T59
KmacMsgFeed->KmacDigest 816 Covered T1,T2,T3
KmacMsgFeed->KmacIdle 813 Covered T12,T18,T24
KmacMsgFeed->KmacTerminalError 847 Covered T4,T8,T37
KmacPrefix->KmacKeyBlock 791 Covered T12,T14,T18
KmacPrefix->KmacMsgFeed 791 Covered T12,T18,T24
KmacPrefix->KmacTerminalError 847 Covered T5,T60,T7



Branch Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
Branches 65 61 93.85
TERNARY 423 2 2 100.00
TERNARY 633 4 4 100.00
TERNARY 641 4 4 100.00
TERNARY 646 2 2 100.00
CASE 431 6 5 83.33
IF 485 3 3 100.00
IF 558 3 3 100.00
IF 649 2 2 100.00
CASE 688 6 4 66.67
IF 764 2 2 100.00
CASE 773 15 15 100.00
IF 846 2 2 100.00
TERNARY 1153 2 2 100.00
IF 1413 4 3 75.00
IF 1436 3 3 100.00
IF 1465 3 3 100.00
IF 1475 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 423 (cmd_update) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 633 (msgfifo_full) ? -2-: 633 (msgfifo_empty_negedge) ? -3-: 633 (msgfifo2kmac_process) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T18,T31,T50
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 641 (app_active) ? -2-: 641 ((sha3_fsm != StAbsorb)) ? -3-: 641 (msgfifo2kmac_process) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T12,T18,T24
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 646 (msgfifo_empty_gate) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T32,T49,T28


LineNo. Expression -1-: 431 case (kmac_cmd)

Branches:
-1-StatusTests
CmdStart Covered T1,T2,T3
CmdProcess Covered T1,T2,T3
CmdManualRun Covered T1,T2,T12
CmdDone Covered T1,T2,T3
CmdNone Covered T1,T2,T3
default Not Covered


LineNo. Expression -1-: 485 if ((!rst_ni)) -2-: 487 if (engine_stable)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 558 if ((!rst_ni)) -2-: 560 if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 649 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 688 case (1'b1)

Branches:
-1-StatusTests
app_err.valid Covered T14,T24,T4
errchecker_err.valid Covered T14,T24,T35
sha3_err.valid Covered T28,T29,T30
entropy_err.valid Not Covered
msgfifo_err.valid Not Covered
default Covered T1,T2,T3


LineNo. Expression -1-: 764 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 773 case (kmac_st) -2-: 775 if ((kmac_cmd == CmdStart)) -3-: 777 if ((CShake == app_sha3_mode)) -4-: 790 if (sha3_block_processed) -5-: 791 (app_kmac_en) ? -6-: 799 if (sha3_block_processed) -7-: 808 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done))) -8-: 814 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done))) -9-: 824 if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
KmacIdle 1 1 - - - - - - Covered T12,T14,T18
KmacIdle 1 0 - - - - - - Covered T1,T2,T3
KmacIdle 0 - - - - - - - Covered T1,T2,T3
KmacPrefix - - 1 1 - - - - Covered T12,T14,T18
KmacPrefix - - 1 0 - - - - Covered T12,T18,T24
KmacPrefix - - 0 - - - - - Covered T12,T14,T18
KmacKeyBlock - - - - 1 - - - Covered T12,T14,T18
KmacKeyBlock - - - - 0 - - - Covered T12,T14,T18
KmacMsgFeed - - - - - 1 - - Covered T12,T18,T24
KmacMsgFeed - - - - - 0 1 - Covered T1,T2,T3
KmacMsgFeed - - - - - 0 0 - Covered T1,T2,T3
KmacDigest - - - - - - - 1 Covered T1,T2,T3
KmacDigest - - - - - - - 0 Covered T1,T2,T3
KmacTerminalError - - - - - - - - Covered T4,T5,T6
default - - - - - - - - Covered T9,T10,T11


LineNo. Expression -1-: 846 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 1153 (reg_state_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 1413 if ((!rst_ni)) -2-: 1415 if (alert_recov_operation) -3-: 1417 if (err_processed)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Covered T21,T22,T23
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1436 if ((!rst_ni)) -2-: 1438 if (alert_fatal)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T5,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1465 if ((!rst_ni)) -2-: 1467 if (alerts[1])

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T5,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1475 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 30 30 100.00 30 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 30 30 100.00 30 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 2147483647 2147483647 0 0
CmdSparse_M 2147483647 1290995 0 0
EnMaskingKnown_A 2147483647 2147483647 0 0
EntropyReadyLatched_A 2147483647 340157 0 0
EntrySizeRegSameToEntrySizePkg_A 1031 1031 0 0
ErrProcessedLatched_A 2147483647 517 0 0
FifoEmpty_A 2147483647 2147483647 0 0
FpvSecCmErrorCheckFsmCheck_A 2147483647 70 0 0
FpvSecCmKeccackFsmCheck_A 2147483647 70 0 0
FpvSecCmKeyIndexCountCheck_A 2147483647 70 0 0
FpvSecCmKmacAppFsmCheck_A 2147483647 70 0 0
FpvSecCmKmacCoreFsmCheck_A 2147483647 70 0 0
FpvSecCmKmacFsmCheck_A 2147483647 70 0 0
FpvSecCmRegWeOnehotCheck_A 2147483647 70 0 0
FpvSecCmRoundCountCheck_A 2147483647 70 0 0
FpvSecCmSHA3FsmCheck_A 2147483647 70 0 0
FpvSecCmSHA3padFsmCheck_A 2147483647 70 0 0
FpvSecCmSentMsgCountCheck_A 2147483647 70 0 0
KmacCmd_A 2147483647 2147483647 0 0
KmacDone_A 2147483647 2147483647 0 0
KmacErr_A 2147483647 2147483647 0 0
KmacStKnown_A 2147483647 2147483647 0 0
NumAlerts2_A 1031 1031 0 0
NumEntriesRegSameToNumEntriesPkg_A 1031 1031 0 0
PrefixRegSameToPrefixPkg_A 1031 1031 0 0
SecretKeyDivideBy32_A 1031 1031 0 0
Sha3AbsorbedPulse_A 2147483647 349853 0 0
TlOAReadyKnown_A 2147483647 2147483647 0 0
TlODValidKnown_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

CmdSparse_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1290995 0 0
T1 216070 7944 0 0
T2 218171 7927 0 0
T3 649052 1243 0 0
T12 176295 156 0 0
T13 695637 987 0 0
T14 892523 857 0 0
T15 927456 1201 0 0
T16 186649 1255 0 0
T17 0 1248 0 0
T18 0 3296 0 0
T19 1417 0 0 0
T20 855 0 0 0

EnMaskingKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

EntropyReadyLatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 340157 0 0
T1 216070 2184 0 0
T2 218171 2185 0 0
T3 649052 381 0 0
T12 176295 35 0 0
T13 695637 301 0 0
T14 892523 124 0 0
T15 927456 364 0 0
T16 186649 377 0 0
T17 0 377 0 0
T18 0 558 0 0
T19 1417 0 0 0
T20 855 0 0 0

EntrySizeRegSameToEntrySizePkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

ErrProcessedLatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 517 0 0
T21 16201 4 0 0
T22 0 14 0 0
T23 0 13 0 0
T29 561594 0 0 0
T52 373572 0 0 0
T61 0 7 0 0
T62 0 17 0 0
T63 0 2 0 0
T64 0 1 0 0
T65 0 15 0 0
T66 0 7 0 0
T67 0 17 0 0
T68 190818 0 0 0
T69 123183 0 0 0
T70 132630 0 0 0
T71 968375 0 0 0
T72 226512 0 0 0
T73 590843 0 0 0
T74 195850 0 0 0

FifoEmpty_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

FpvSecCmErrorCheckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmKeccackFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmKeyIndexCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmKmacAppFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmKmacCoreFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmKmacFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmRoundCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmSHA3FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmSHA3padFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

FpvSecCmSentMsgCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T9 460287 20 0 0
T10 0 10 0 0
T11 0 20 0 0
T22 81655 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T77 427940 0 0 0
T78 889 0 0 0
T79 42305 0 0 0
T80 636429 0 0 0
T81 549457 0 0 0
T82 1357 0 0 0
T83 20158 0 0 0
T84 745442 0 0 0

KmacCmd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

KmacDone_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

KmacErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

KmacStKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

NumAlerts2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

NumEntriesRegSameToNumEntriesPkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PrefixRegSameToPrefixPkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

SecretKeyDivideBy32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1031 1031 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Sha3AbsorbedPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 349853 0 0
T1 216070 2265 0 0
T2 218171 2265 0 0
T3 649052 390 0 0
T12 176295 35 0 0
T13 695637 310 0 0
T14 892523 112 0 0
T15 927456 374 0 0
T16 186649 390 0 0
T17 0 390 0 0
T18 0 562 0 0
T19 1417 0 0 0
T20 855 0 0 0

TlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

TlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 216070 216069 0 0
T2 218171 218170 0 0
T3 649052 649044 0 0
T12 176295 176215 0 0
T13 695637 695627 0 0
T14 892523 892433 0 0
T15 927456 927446 0 0
T16 186649 186641 0 0
T19 1417 1350 0 0
T20 855 778 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%