Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	479658	0	0
entropy_period_rd_A	2147483647	1569	0	0
intr_enable_rd_A	2147483647	2097	0	0
prefix_0_rd_A	2147483647	1483	0	0
prefix_10_rd_A	2147483647	1644	0	0
prefix_1_rd_A	2147483647	1649	0	0
prefix_2_rd_A	2147483647	1663	0	0
prefix_3_rd_A	2147483647	1772	0	0
prefix_4_rd_A	2147483647	1762	0	0
prefix_5_rd_A	2147483647	1782	0	0
prefix_6_rd_A	2147483647	1790	0	0
prefix_7_rd_A	2147483647	1706	0	0
prefix_8_rd_A	2147483647	1539	0	0
prefix_9_rd_A	2147483647	1660	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	479658	0	0
T52	373572	56455	0	0
T53	0	49243	0	0
T54	0	54710	0	0
T71	968375	0	0	0
T72	226512	0	0	0
T73	590843	0	0	0
T74	195850	0	0	0
T94	0	27865	0	0
T95	0	16360	0	0
T120	0	75356	0	0
T121	0	79114	0	0
T122	0	34604	0	0
T123	0	83031	0	0
T124	0	7	0	0
T125	504535	0	0	0
T126	3260	0	0	0
T127	222828	0	0	0
T128	123393	0	0	0
T129	954613	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1569	0	0
T25	119133	0	0	0
T94	313293	122	0	0
T95	0	52	0	0
T103	0	16	0	0
T105	0	23	0	0
T109	0	18	0	0
T110	0	28	0	0
T115	0	122	0	0
T139	0	12	0	0
T140	0	11	0	0
T141	0	35	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2097	0	0
T25	119133	0	0	0
T94	313293	96	0	0
T95	0	38	0	0
T103	0	8	0	0
T105	0	21	0	0
T110	0	21	0	0
T115	0	164	0	0
T139	0	2	0	0
T140	0	17	0	0
T141	0	9	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0
T150	0	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1483	0	0
T25	119133	0	0	0
T94	313293	66	0	0
T95	0	34	0	0
T103	0	11	0	0
T105	0	14	0	0
T109	0	8	0	0
T110	0	16	0	0
T115	0	89	0	0
T139	0	8	0	0
T140	0	21	0	0
T141	0	15	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1644	0	0
T25	119133	0	0	0
T94	313293	75	0	0
T95	0	61	0	0
T103	0	14	0	0
T105	0	10	0	0
T109	0	10	0	0
T110	0	21	0	0
T115	0	78	0	0
T139	0	4	0	0
T140	0	36	0	0
T141	0	13	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1649	0	0
T25	119133	0	0	0
T94	313293	125	0	0
T95	0	60	0	0
T103	0	14	0	0
T105	0	15	0	0
T109	0	14	0	0
T110	0	39	0	0
T115	0	85	0	0
T139	0	7	0	0
T140	0	23	0	0
T141	0	30	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1663	0	0
T25	119133	0	0	0
T94	313293	92	0	0
T95	0	24	0	0
T103	0	13	0	0
T105	0	16	0	0
T109	0	4	0	0
T110	0	22	0	0
T115	0	71	0	0
T139	0	9	0	0
T140	0	15	0	0
T141	0	20	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1772	0	0
T25	119133	0	0	0
T94	313293	109	0	0
T95	0	68	0	0
T103	0	13	0	0
T105	0	14	0	0
T109	0	19	0	0
T110	0	36	0	0
T115	0	69	0	0
T139	0	9	0	0
T140	0	40	0	0
T141	0	33	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1762	0	0
T25	119133	0	0	0
T94	313293	139	0	0
T95	0	58	0	0
T103	0	20	0	0
T105	0	20	0	0
T109	0	15	0	0
T110	0	31	0	0
T115	0	85	0	0
T139	0	13	0	0
T140	0	2	0	0
T141	0	20	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1782	0	0
T25	119133	0	0	0
T94	313293	142	0	0
T95	0	57	0	0
T103	0	20	0	0
T105	0	16	0	0
T109	0	4	0	0
T110	0	22	0	0
T115	0	81	0	0
T139	0	10	0	0
T140	0	19	0	0
T141	0	10	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1790	0	0
T25	119133	0	0	0
T94	313293	88	0	0
T95	0	42	0	0
T103	0	24	0	0
T105	0	3	0	0
T109	0	10	0	0
T110	0	15	0	0
T115	0	48	0	0
T139	0	11	0	0
T140	0	12	0	0
T141	0	12	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1706	0	0
T25	119133	0	0	0
T94	313293	93	0	0
T95	0	53	0	0
T103	0	18	0	0
T105	0	5	0	0
T109	0	11	0	0
T110	0	23	0	0
T115	0	83	0	0
T139	0	10	0	0
T140	0	34	0	0
T141	0	32	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1539	0	0
T25	119133	0	0	0
T94	313293	111	0	0
T95	0	24	0	0
T103	0	8	0	0
T105	0	16	0	0
T109	0	2	0	0
T110	0	29	0	0
T115	0	77	0	0
T139	0	11	0	0
T140	0	10	0	0
T141	0	28	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1660	0	0
T25	119133	0	0	0
T94	313293	92	0	0
T95	0	76	0	0
T103	0	16	0	0
T105	0	10	0	0
T109	0	1	0	0
T110	0	19	0	0
T115	0	75	0	0
T139	0	7	0	0
T140	0	13	0	0
T141	0	12	0	0
T142	365981	0	0	0
T143	302563	0	0	0
T144	833445	0	0	0
T145	694962	0	0	0
T146	29159	0	0	0
T147	108901	0	0	0
T148	65634	0	0	0
T149	112349	0	0	0