Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	583925	0	0
entropy_period_rd_A	2147483647	2161	0	0
intr_enable_rd_A	2147483647	2641	0	0
prefix_0_rd_A	2147483647	1881	0	0
prefix_10_rd_A	2147483647	1847	0	0
prefix_1_rd_A	2147483647	1758	0	0
prefix_2_rd_A	2147483647	1917	0	0
prefix_3_rd_A	2147483647	1982	0	0
prefix_4_rd_A	2147483647	1928	0	0
prefix_5_rd_A	2147483647	1943	0	0
prefix_6_rd_A	2147483647	1884	0	0
prefix_7_rd_A	2147483647	1988	0	0
prefix_8_rd_A	2147483647	1895	0	0
prefix_9_rd_A	2147483647	1820	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	583925	0	0
T29	375981	55710	0	0
T31	0	37011	0	0
T34	4233	0	0	0
T51	0	77190	0	0
T90	0	67690	0	0
T91	0	67392	0	0
T133	0	47173	0	0
T134	0	84268	0	0
T135	0	15850	0	0
T136	0	128389	0	0
T137	0	2	0	0
T138	5925	0	0	0
T139	48167	0	0	0
T140	171387	0	0	0
T141	37613	0	0	0
T142	599691	0	0	0
T143	218859	0	0	0
T144	140049	0	0	0
T145	914589	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2161	0	0
T97	6477	37	0	0
T126	12077	11	0	0
T128	23316	56	0	0
T137	4407	12	0	0
T153	5441	47	0	0
T154	11112	17	0	0
T155	23155	141	0	0
T156	52293	434	0	0
T157	7887	8	0	0
T158	23953	112	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2641	0	0
T97	6477	47	0	0
T126	12077	29	0	0
T128	23316	77	0	0
T130	1193	3	0	0
T131	1220	26	0	0
T137	4407	5	0	0
T153	5441	10	0	0
T154	11112	58	0	0
T155	23155	154	0	0
T159	10517	7	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1881	0	0
T97	6477	33	0	0
T126	12077	4	0	0
T128	23316	32	0	0
T137	4407	12	0	0
T153	5441	9	0	0
T154	11112	20	0	0
T155	23155	70	0	0
T156	52293	482	0	0
T157	7887	3	0	0
T158	23953	83	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1847	0	0
T97	6477	17	0	0
T126	12077	26	0	0
T128	23316	37	0	0
T137	4407	16	0	0
T153	5441	8	0	0
T154	11112	61	0	0
T155	23155	95	0	0
T156	52293	429	0	0
T157	7887	7	0	0
T158	23953	68	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1758	0	0
T97	6477	30	0	0
T126	12077	20	0	0
T128	23316	30	0	0
T137	4407	5	0	0
T153	5441	9	0	0
T154	11112	12	0	0
T155	23155	72	0	0
T156	52293	395	0	0
T157	7887	11	0	0
T158	23953	96	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1917	0	0
T97	6477	51	0	0
T126	12077	38	0	0
T128	23316	40	0	0
T137	4407	4	0	0
T153	5441	43	0	0
T154	11112	32	0	0
T155	23155	81	0	0
T156	52293	423	0	0
T157	7887	7	0	0
T159	10517	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1982	0	0
T97	6477	23	0	0
T126	12077	21	0	0
T128	23316	63	0	0
T137	4407	9	0	0
T153	5441	30	0	0
T154	11112	45	0	0
T155	23155	101	0	0
T156	52293	440	0	0
T157	7887	14	0	0
T158	23953	92	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1928	0	0
T97	6477	31	0	0
T126	12077	29	0	0
T128	23316	39	0	0
T137	4407	14	0	0
T153	5441	32	0	0
T154	11112	80	0	0
T155	23155	77	0	0
T156	52293	410	0	0
T157	7887	15	0	0
T158	23953	93	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1943	0	0
T97	6477	20	0	0
T126	12077	23	0	0
T128	23316	49	0	0
T137	4407	13	0	0
T153	5441	4	0	0
T154	11112	32	0	0
T155	23155	97	0	0
T156	52293	479	0	0
T157	7887	15	0	0
T158	23953	96	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1884	0	0
T97	6477	25	0	0
T126	12077	42	0	0
T128	23316	46	0	0
T137	4407	8	0	0
T153	5441	13	0	0
T154	11112	10	0	0
T155	23155	76	0	0
T156	52293	399	0	0
T157	7887	14	0	0
T158	23953	92	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1988	0	0
T97	6477	28	0	0
T126	12077	36	0	0
T128	23316	54	0	0
T137	4407	14	0	0
T153	5441	41	0	0
T154	11112	66	0	0
T155	23155	107	0	0
T156	52293	452	0	0
T157	7887	6	0	0
T158	23953	83	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1895	0	0
T97	6477	20	0	0
T126	12077	23	0	0
T128	23316	35	0	0
T137	4407	15	0	0
T153	5441	12	0	0
T154	11112	20	0	0
T155	23155	99	0	0
T156	52293	444	0	0
T157	7887	9	0	0
T158	23953	94	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1820	0	0
T97	6477	23	0	0
T126	12077	13	0	0
T128	23316	46	0	0
T137	4407	10	0	0
T153	5441	26	0	0
T154	11112	20	0	0
T155	23155	89	0	0
T156	52293	412	0	0
T157	7887	9	0	0
T158	23953	83	0	0