Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.19	96.27	93.33	63.67	100.00	93.85	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	97.24	96.27	93.33	100.00	100.00	93.85	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.24	96.27	93.33	100.00	100.00	93.85	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.75	95.88	92.26	100.00	69.42	94.11	98.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	86.94	90.00	77.78			80.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	81.44	91.14	87.72		40.00	88.35	100.00
u_errchk	92.70	97.22	96.67		73.33	96.30	100.00
u_kmac_core	95.80	98.75	92.86	100.00	100.00	92.31	90.91
u_msgfifo	97.75	100.00	95.00		100.00	93.75	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.98	99.19	96.97	100.00		98.72	100.00
u_sha3	92.62	91.91	88.51	100.00	83.33	92.00	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.84	89.80	81.02			88.54	100.00
u_tlul_adapter_msgfifo	79.91	87.01	74.59			77.38	80.65

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	346	0	0
ALWAYS	346	2	2	100.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
ALWAYS	429	9	9	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
ALWAYS	488	6	6	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	537	0	0
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
ALWAYS	561	5	5	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
ALWAYS	651	5	5	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	687	7	5	71.43
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	728	1	0	0.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
ALWAYS	765	3	3	100.00
ALWAYS	769	28	28	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	923	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	1025	1	1	100.00
CONT_ASSIGN	1030	1	1	100.00
CONT_ASSIGN	1031	1	1	100.00
CONT_ASSIGN	1033	1	1	100.00
CONT_ASSIGN	1036	0	0
ALWAYS	1157	0	0
ALWAYS	1157	2	2	100.00
CONT_ASSIGN	1311	1	0	0.00
CONT_ASSIGN	1312	1	1	100.00
CONT_ASSIGN	1313	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1330	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1332	1	1	100.00
CONT_ASSIGN	1333	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1387	1	1	100.00
CONT_ASSIGN	1401	1	1	100.00
CONT_ASSIGN	1408	1	1	100.00
CONT_ASSIGN	1413	1	1	100.00
ALWAYS	1419	6	5	83.33
CONT_ASSIGN	1428	1	1	100.00
CONT_ASSIGN	1430	1	1	100.00
ALWAYS	1442	4	4	100.00
CONT_ASSIGN	1448	1	1	100.00
ALWAYS	1471	4	4	100.00
ALWAYS	1481	3	3	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1496	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	1	1
347	1	1
352	0	1
421	1	1
422	1	1
426	1	1
429	1	1
430	1	1
431	1	1
432	1	1
434	1	1
436	1	1
440	1	1
444	1	1
448	1	1
464	1	1
465	1	1
466	1	1
469	1	1
473	1	1
474	1	1
478	1	1
481	1	1
488	1	1
489	1	1
490	1	1
491	1	1
492	1	1
493	1	1
			MISSING_ELSE
			MISSING_ELSE
513	1	1
518	1	1
525	1	1
528	1	1
529	1	1
530	1	1
532	1	1
533	1	1
535	1	1
537		unreachable
539	1	1
543	1	1
545	1	1
546	1	1
549	1	1
550	1	1
553	1	1
561	1	1
562	1	1
563	1	1
564	1	1
566	1	1
571	1	1
577	1	1
578	1	1
579	1	1
587	1	1
629	1	1
635	1	1
643	1	1
648	1	1
651	1	1
652	1	1
653	1	1
655	1	1
656	1	1
679	1	1
684	1	1
687	1	1
689	1	1
694	1	1
698	1	1
702	1	1
706	0	1
710	0	1
723	1	1
728	0	1
735	1	1
745	1	1
765	3	3
769	1	1
771	1	1
772	1	1
774	1	1
776	1	1
778	1	1
779	1	1
782	1	1
785	1	1
791	1	1
792	1	1
794	1	1
799	1	1
800	1	1
801	1	1
803	1	1
809	1	1
814	1	1
815	1	1
817	1	1
819	1	1
825	1	1
826	1	1
828	1	1
834	1	1
835	1	1
847	1	1
848	1	1
			MISSING_ELSE
920	1	1
923	1	1
992	1	1
994	1	1
1025	1	1
1030	1	1
1031	1	1
1033	1	1
1036		unreachable
1157	1	1
1158	1	1
1311	0	1
1312	1	1
1313	1	1
1323	1	1
1324	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1336	1	1
1345	1	1
1387	1	1
1401	1	1
1408	1	1
1413	1	1
1419	1	1
1420	1	1
1421	1	1
1422	0	1
1423	1	1
1424	1	1
			MISSING_ELSE
1428	1	1
1430	1	1
1442	1	1
1443	1	1
1444	1	1
1445	1	1
			MISSING_ELSE
1448	1	1
1471	1	1
1472	1	1
1473	1	1
1475	1	1
			MISSING_ELSE
1481	1	1
1482	1	1
1485	1	1
1492	1	1
1496	1	1
1498	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T25

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T25

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T26,T45,T46
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T4,T13
1	1	1	Covered	T1,T2,T4

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T21,T22

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T25,T36

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T39,T29
1	Covered	T1,T2,T3

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T19,T43,T47
0	0	1	0	Not Covered
0	1	0	0	Covered	T3,T5,T6
1	0	0	0	Covered	T1,T23,T24

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T10,T11,T12

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T10,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T10,T11,T12
0	0	1	0	0	0	Covered	T10,T11,T12
0	1	0	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	0	Covered	T10,T11,T12

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T13

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T4,T15
1	Covered	T1,T4,T13

 LINE       1025
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1158
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       1401
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T49,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T48,T49,T50

 LINE       1401
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T49,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T48,T49,T50

 LINE       1430
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T10,T11,T12
0	0	1	0	0	Covered	T3,T5,T6
0	1	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	64	90.14
Total Bits	6534	4160	63.67
Total Bits 0->1	3267	2080	63.67
Total Bits 1->0	3267	2080	63.67

Ports	71	64	90.14
Port Bits	6534	4160	63.67
Port Bits 0->1	3267	2080	63.67
Port Bits 1->0	3267	2080	63.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T29,T51,T31	Yes	T29,T51,T31	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
keymgr_key_i.key[0][0]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][1]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][2]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][3]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][4]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][6:5]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][7]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][8]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][13:9]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][14]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][17:15]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][18]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][20:19]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][21]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][22]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][23]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][24]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][25]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][26]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][27]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][28]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][29]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][32:30]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][34:33]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][35]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][36]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][37]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][39:38]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][42:40]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][44:43]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][45]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][46]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][47]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][48]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][52:49]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][53]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][54]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][56:55]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][57]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][58]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][60:59]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][61]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][63:62]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][64]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][65]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][66]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][68:67]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][73:69]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][74]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][75]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][76]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][77]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][78]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][80:79]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][84:81]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][85]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][86]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][87]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][88]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][89]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][90]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][92:91]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][94:93]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][96:95]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][98:97]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][99]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][100]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][101]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][103:102]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][104]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][109:105]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][110]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][111]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][112]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][113]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][118:114]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][120:119]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][121]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][122]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][123]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][124]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][125]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][128:126]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][129]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][130]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][134:131]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][135]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][136]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][138:137]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][141:139]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][142]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][143]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][144]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][145]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][149:146]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][150]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][156:151]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][157]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][158]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][159]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][160]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][161]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][162]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][164:163]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][166:165]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][168:167]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][170:169]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][172:171]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][173]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][177:174]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][178]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][179]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][180]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][181]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][182]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][183]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][185:184]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][186]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][187]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][191:188]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][192]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][194:193]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][195]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][196]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][200:197]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][201]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][202]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][203]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][204]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][213:205]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][214]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][215]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][216]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][217]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][218]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][220:219]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][221]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][222]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][223]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][225:224]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][226]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][227]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][230:228]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][231]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][235:232]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][236]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][237]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][238]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][239]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][240]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][241]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][247:242]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][248]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][249]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][250]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][251]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][252]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][253]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][255:254]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][0]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][1]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][2]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][3]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][5:4]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][6]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][8:7]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][9]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][10]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][14:11]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][15]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][16]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][19:17]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][20]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][23:21]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][24]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][26:25]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][28:27]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][29]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][33:30]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][34]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][35]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][41:36]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][42]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][44:43]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][45]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][47:46]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][48]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][49]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][50]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][52:51]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][53]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][55:54]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][56]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][57]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][58]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][59]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][61:60]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][62]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][63]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][64]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][66:65]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][67]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][68]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][69]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][70]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][71]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][77:72]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][79:78]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][80]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][81]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][82]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][84:83]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][87:85]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][88]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][89]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][90]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][91]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][93:92]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][94]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][95]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][96]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][97]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][99:98]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][100]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][106:101]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][107]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][108]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][109]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][110]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][111]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][112]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][113]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][116:114]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][117]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][118]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][119]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][120]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][121]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][122]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][124:123]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][126:125]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][134:127]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][135]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][136]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][137]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][139:138]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][140]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][141]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][142]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][144:143]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][145]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][146]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][148:147]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][149]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][150]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][151]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][152]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][154:153]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][155]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][156]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][159:157]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][160]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][161]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][163:162]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][164]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][165]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][166]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][168:167]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][169]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][170]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][172:171]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][173]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][174]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][176:175]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][177]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][178]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][179]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][180]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][181]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][183:182]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][184]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][188:185]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][189]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][190]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][191]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][192]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][194:193]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][198:195]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][199]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][200]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][201]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][203:202]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][204]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][206:205]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][209:207]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][210]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][211]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][212]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][213]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][216:214]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][217]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][218]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][220:219]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][221]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][225:222]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][226]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][230:227]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][231]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][232]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][233]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][234]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][235]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][241:236]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][242]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][243]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][248:244]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][250:249]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][252:251]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][253]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][254]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][255]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.valid	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
app_i[0].last	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	INPUT
app_i[0].strb[7:0]	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	INPUT
app_i[0].data[63:0]	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	INPUT
app_i[0].valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
app_i[1].last	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	INPUT
app_i[1].strb[7:0]	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	INPUT
app_i[1].data[63:0]	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	INPUT
app_i[1].valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
app_i[2].last	Yes	Yes	T1,T4,T19	Yes	T1,T4,T15	INPUT
app_i[2].strb[7:0]	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	INPUT
app_i[2].data[63:0]	Yes	Yes	T1,T4,T15	Yes	T1,T4,T15	INPUT
app_i[2].valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
app_o[0].error	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[0].done	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[0].ready	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[1].error	Yes	Yes	T1,T23,T32	Yes	T1,T23,T32	OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[1].done	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[1].ready	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[2].error	Yes	Yes	T1,T23,T24	Yes	T1,T23,T24	OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T1,T4,T15	Yes	T1,T4,T15	OUTPUT
app_o[2].done	Yes	Yes	T1,T4,T15	Yes	T1,T4,T15	OUTPUT
app_o[2].ready	Yes	Yes	T1,T4,T15	Yes	T1,T4,T15	OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
intr_kmac_done_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T39,T29	Yes	T1,T39,T29	OUTPUT
intr_kmac_err_o	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	817	Covered	T1,T2,T4
KmacIdle	785	Covered	T1,T2,T3
KmacKeyBlock	792	Covered	T1,T4,T13
KmacMsgFeed	782	Covered	T1,T2,T3
KmacPrefix	779	Covered	T1,T4,T13
KmacTerminalError	834	Covered	T3,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	826	Covered	T1,T2,T4
KmacDigest->KmacTerminalError	848	Covered	T52,T53,T54
KmacIdle->KmacMsgFeed	782	Covered	T1,T2,T3
KmacIdle->KmacPrefix	779	Covered	T1,T4,T13
KmacIdle->KmacTerminalError	848	Covered	T36,T10,T11
KmacKeyBlock->KmacMsgFeed	801	Covered	T1,T4,T13
KmacKeyBlock->KmacTerminalError	848	Covered	T5,T55,T56
KmacMsgFeed->KmacDigest	817	Covered	T1,T2,T4
KmacMsgFeed->KmacIdle	814	Covered	T1,T4,T15
KmacMsgFeed->KmacTerminalError	848	Covered	T3,T6,T44
KmacPrefix->KmacKeyBlock	792	Covered	T1,T4,T13
KmacPrefix->KmacMsgFeed	792	Covered	T1,T4,T15
KmacPrefix->KmacTerminalError	848	Covered	T7,T57,T58

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	426	2	2	100.00
TERNARY	635	4	4	100.00
TERNARY	643	4	4	100.00
TERNARY	648	2	2	100.00
CASE	434	6	5	83.33
IF	488	3	3	100.00
IF	561	3	3	100.00
IF	651	2	2	100.00
CASE	689	6	4	66.67
IF	765	2	2	100.00
CASE	774	15	15	100.00
IF	847	2	2	100.00
TERNARY	1158	2	2	100.00
IF	1419	4	3	75.00
IF	1442	3	3	100.00
IF	1471	3	3	100.00
IF	1481	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	635	(msgfifo_full) ? 
-2-:	635	(msgfifo_empty_negedge) ? 
-3-:	635	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T25,T36
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	643	(app_active) ? 
-2-:	643	((sha3_fsm != StAbsorb)) ? 
-3-:	643	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T15
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	648	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T39,T29

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T4
CmdManualRun	Covered	T1,T4,T13
CmdDone	Covered	T1,T2,T4
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	if ((!rst_ni))
-2-:	563	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	651	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	689	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T3,T5,T6
errchecker_err.valid	Covered	T19,T43,T47
sha3_err.valid	Covered	T1,T23,T24
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	765	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	774	case (kmac_st)
-2-:	776	if ((kmac_cmd == CmdStart))
-3-:	778	if ((CShake == app_sha3_mode))
-4-:	791	if (sha3_block_processed)
-5-:	792	(app_kmac_en) ? 
-6-:	800	if (sha3_block_processed)
-7-:	809	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	815	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	825	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T4,T13
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T4,T13
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T1,T4,T15
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T4,T13
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T4,T13
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T4,T13
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T1,T4,T15
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	847	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1158	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1419	if ((!rst_ni))
-2-:	1421	if (alert_recov_operation)
-3-:	1423	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1442	if ((!rst_ni))
-2-:	1444	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1471	if ((!rst_ni))
-2-:	1473	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1481	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1282978	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	338178	0	0
EntrySizeRegSameToEntrySizePkg_A	1028	1028	0	0
ErrProcessedLatched_A	2147483647	433	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	90	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	90	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	90	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacFsmCheck_A	2147483647	90	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	90	0	0
FpvSecCmRoundCountCheck_A	2147483647	90	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	90	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	90	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	90	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1028	1028	0	0
NumEntriesRegSameToNumEntriesPkg_A	1028	1028	0	0
PrefixRegSameToPrefixPkg_A	1028	1028	0	0
SecretKeyDivideBy32_A	1028	1028	0	0
Sha3AbsorbedPulse_A	2147483647	348638	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1282978	0	0
T1	193936	2026	0	0
T2	644072	1238	0	0
T3	4803	2	0	0
T4	190252	1057	0	0
T5	4099	3	0	0
T13	138747	418	0	0
T14	174037	7474	0	0
T15	39907	112	0	0
T16	827342	1247	0	0
T17	78108	71	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	338178	0	0
T1	193936	347	0	0
T2	644072	382	0	0
T3	4803	1	0	0
T4	190252	193	0	0
T5	4099	1	0	0
T13	138747	58	0	0
T14	174037	2267	0	0
T15	39907	18	0	0
T16	827342	381	0	0
T17	78108	10	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	433	0	0
T20	65594	7	0	0
T21	0	16	0	0
T22	0	7	0	0
T26	470304	0	0	0
T48	958	0	0	0
T59	0	3	0	0
T60	0	5	0	0
T61	0	5	0	0
T62	0	1	0	0
T63	0	17	0	0
T64	0	5	0	0
T65	0	6	0	0
T66	146120	0	0	0
T67	16393	0	0	0
T68	388442	0	0	0
T69	145503	0	0	0
T70	649193	0	0	0
T71	249376	0	0	0
T72	114406	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348638	0	0
T1	193936	353	0	0
T2	644072	390	0	0
T3	4803	0	0	0
T4	190252	193	0	0
T5	4099	0	0	0
T13	138747	58	0	0
T14	174037	2337	0	0
T15	39907	18	0	0
T16	827342	390	0	0
T17	78108	10	0	0
T18	0	12	0	0
T19	0	115	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	346	0	0
ALWAYS	346	2	2	100.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
ALWAYS	429	9	9	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
ALWAYS	488	6	6	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	537	0	0
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
ALWAYS	561	5	5	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
ALWAYS	651	5	5	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	687	7	5	71.43
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	728	1	0	0.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
ALWAYS	765	3	3	100.00
ALWAYS	769	28	28	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	923	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	1025	1	1	100.00
CONT_ASSIGN	1030	1	1	100.00
CONT_ASSIGN	1031	1	1	100.00
CONT_ASSIGN	1033	1	1	100.00
CONT_ASSIGN	1036	0	0
ALWAYS	1157	0	0
ALWAYS	1157	2	2	100.00
CONT_ASSIGN	1311	1	0	0.00
CONT_ASSIGN	1312	1	1	100.00
CONT_ASSIGN	1313	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1330	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1332	1	1	100.00
CONT_ASSIGN	1333	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1387	1	1	100.00
CONT_ASSIGN	1401	1	1	100.00
CONT_ASSIGN	1408	1	1	100.00
CONT_ASSIGN	1413	1	1	100.00
ALWAYS	1419	6	5	83.33
CONT_ASSIGN	1428	1	1	100.00
CONT_ASSIGN	1430	1	1	100.00
ALWAYS	1442	4	4	100.00
CONT_ASSIGN	1448	1	1	100.00
ALWAYS	1471	4	4	100.00
ALWAYS	1481	3	3	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1496	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	1	1
347	1	1
352	0	1
421	1	1
422	1	1
426	1	1
429	1	1
430	1	1
431	1	1
432	1	1
434	1	1
436	1	1
440	1	1
444	1	1
448	1	1
464	1	1
465	1	1
466	1	1
469	1	1
473	1	1
474	1	1
478	1	1
481	1	1
488	1	1
489	1	1
490	1	1
491	1	1
492	1	1
493	1	1
			MISSING_ELSE
			MISSING_ELSE
513	1	1
518	1	1
525	1	1
528	1	1
529	1	1
530	1	1
532	1	1
533	1	1
535	1	1
537		unreachable
539	1	1
543	1	1
545	1	1
546	1	1
549	1	1
550	1	1
553	1	1
561	1	1
562	1	1
563	1	1
564	1	1
566	1	1
571	1	1
577	1	1
578	1	1
579	1	1
587	1	1
629	1	1
635	1	1
643	1	1
648	1	1
651	1	1
652	1	1
653	1	1
655	1	1
656	1	1
679	1	1
684	1	1
687	1	1
689	1	1
694	1	1
698	1	1
702	1	1
706	0	1
710	0	1
723	1	1
728	0	1
735	1	1
745	1	1
765	3	3
769	1	1
771	1	1
772	1	1
774	1	1
776	1	1
778	1	1
779	1	1
782	1	1
785	1	1
791	1	1
792	1	1
794	1	1
799	1	1
800	1	1
801	1	1
803	1	1
809	1	1
814	1	1
815	1	1
817	1	1
819	1	1
825	1	1
826	1	1
828	1	1
834	1	1
835	1	1
847	1	1
848	1	1
			MISSING_ELSE
920	1	1
923	1	1
992	1	1
994	1	1
1025	1	1
1030	1	1
1031	1	1
1033	1	1
1036		unreachable
1157	1	1
1158	1	1
1311	0	1
1312	1	1
1313	1	1
1323	1	1
1324	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1336	1	1
1345	1	1
1387	1	1
1401	1	1
1408	1	1
1413	1	1
1419	1	1
1420	1	1
1421	1	1
1422	0	1
1423	1	1
1424	1	1
			MISSING_ELSE
1428	1	1
1430	1	1
1442	1	1
1443	1	1
1444	1	1
1445	1	1
			MISSING_ELSE
1448	1	1
1471	1	1
1472	1	1
1473	1	1
1475	1	1
			MISSING_ELSE
1481	1	1
1482	1	1
1485	1	1
1492	1	1
1496	1	1
1498	6	6

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T25

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T25

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T26,T45,T46
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T4,T13
1	1	1	Covered	T1,T2,T4

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T21,T22

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T25,T36

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T39,T29
1	Covered	T1,T2,T3

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T19,T43,T47
0	0	1	0	Not Covered
0	1	0	0	Covered	T3,T5,T6
1	0	0	0	Covered	T1,T23,T24

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T10,T11,T12

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T10,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T10,T11,T12
0	0	1	0	0	0	Covered	T10,T11,T12
0	1	0	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	0	Covered	T10,T11,T12

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T13

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T4,T15
1	Covered	T1,T4,T13

 LINE       1025
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1158
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       1401
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T49,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T48,T49,T50

 LINE       1401
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T49,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T48,T49,T50

 LINE       1430
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T10,T11,T12
0	0	1	0	0	Covered	T3,T5,T6
0	1	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	64	100.00
Total Bits	4160	4160	100.00
Total Bits 0->1	2080	2080	100.00
Total Bits 1->0	2080	2080	100.00

Ports	64	64	100.00
Port Bits	4160	4160	100.00
Port Bits 0->1	2080	2080	100.00
Port Bits 1->0	2080	2080	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T29,T51,T31	Yes	T29,T51,T31	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
keymgr_key_i.key[0][0]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][1]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][2]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][3]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][4]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][6:5]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][7]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][8]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][13:9]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][14]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][17:15]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][18]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][20:19]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][21]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][22]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][23]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][24]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][25]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][26]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][27]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][28]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][29]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][32:30]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][34:33]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][35]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][36]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][37]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][39:38]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][42:40]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][44:43]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][45]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][46]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][47]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][48]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][52:49]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][53]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][54]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][56:55]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][57]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][58]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][60:59]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][61]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][63:62]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][64]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][65]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][66]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][68:67]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][73:69]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][74]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][75]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][76]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][77]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][78]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][80:79]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][84:81]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][85]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][86]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][87]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][88]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][89]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][90]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][92:91]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][94:93]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][96:95]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][98:97]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][99]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][100]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][101]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][103:102]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][104]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][109:105]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][110]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][111]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][112]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][113]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][118:114]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][120:119]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][121]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][122]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][123]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][124]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][125]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][128:126]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][129]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][130]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][134:131]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][135]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][136]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][138:137]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][141:139]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][142]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][143]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][144]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][145]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][149:146]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][150]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][156:151]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][157]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][158]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][159]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][160]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][161]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][162]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][164:163]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][166:165]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][168:167]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][170:169]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][172:171]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][173]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][177:174]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][178]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][179]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][180]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][181]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][182]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][183]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][185:184]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][186]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][187]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][191:188]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][192]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][194:193]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][195]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][196]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][200:197]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][201]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][202]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][203]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][204]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][213:205]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][214]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][215]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][216]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][217]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][218]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][220:219]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][221]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][222]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][223]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][225:224]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][226]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][227]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][230:228]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][231]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][235:232]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][236]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][237]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][238]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][239]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][240]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][241]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][247:242]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][248]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][249]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][250]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][251]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][252]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][253]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][255:254]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][0]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][1]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][2]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][3]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][5:4]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][6]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][8:7]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][9]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][10]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][14:11]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][15]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][16]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][19:17]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][20]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][23:21]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][24]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][26:25]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][28:27]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][29]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][33:30]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][34]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][35]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][41:36]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][42]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][44:43]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][45]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][47:46]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][48]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][49]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][50]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][52:51]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][53]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][55:54]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][56]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][57]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][58]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][59]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][61:60]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][62]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][63]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][64]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][66:65]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][67]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][68]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][69]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][70]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][71]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][77:72]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][79:78]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][80]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][81]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][82]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][84:83]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][87:85]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][88]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][89]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][90]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][91]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][93:92]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][94]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][95]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][96]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][97]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][99:98]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][100]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][106:101]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][107]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][108]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][109]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][110]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][111]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][112]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][113]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][116:114]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][117]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][118]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][119]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][120]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][121]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][122]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][124:123]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][126:125]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][134:127]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][135]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][136]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][137]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][139:138]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][140]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][141]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][142]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][144:143]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][145]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][146]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][148:147]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][149]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][150]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][151]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][152]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][154:153]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][155]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][156]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][159:157]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][160]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][161]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][163:162]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][164]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][165]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][166]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][168:167]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][169]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][170]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][172:171]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][173]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][174]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][176:175]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][177]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][178]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][179]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][180]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][181]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][183:182]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][184]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][188:185]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][189]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][190]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][191]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][192]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][194:193]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][198:195]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][199]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][200]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][201]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][203:202]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][204]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][206:205]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][209:207]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][210]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][211]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][212]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][213]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][216:214]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][217]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][218]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][220:219]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][221]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][225:222]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][226]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][230:227]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][231]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][232]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][233]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][234]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][235]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][241:236]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][242]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][243]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][248:244]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][250:249]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][252:251]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][253]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][254]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][255]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.valid	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
app_i[0].last	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	INPUT
app_i[0].strb[7:0]	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	INPUT
app_i[0].data[63:0]	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	INPUT
app_i[0].valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
app_i[1].last	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	INPUT
app_i[1].strb[7:0]	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	INPUT
app_i[1].data[63:0]	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	INPUT
app_i[1].valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
app_i[2].last	Yes	Yes	T1,T4,T19	Yes	T1,T4,T15	INPUT
app_i[2].strb[7:0]	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	INPUT
app_i[2].data[63:0]	Yes	Yes	T1,T4,T15	Yes	T1,T4,T15	INPUT
app_i[2].valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
app_o[0].error	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[0].done	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[0].ready	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[1].error	Yes	Yes	T1,T23,T32	Yes	T1,T23,T32	OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[1].done	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[1].ready	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
app_o[2].error	Yes	Yes	T1,T23,T24	Yes	T1,T23,T24	OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	Yes	Yes	T1,T4,T15	Yes	T1,T4,T15	OUTPUT
app_o[2].done	Yes	Yes	T1,T4,T15	Yes	T1,T4,T15	OUTPUT
app_o[2].ready	Yes	Yes	T1,T4,T15	Yes	T1,T4,T15	OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
intr_kmac_done_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T39,T29	Yes	T1,T39,T29	OUTPUT
intr_kmac_err_o	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	817	Covered	T1,T2,T4
KmacIdle	785	Covered	T1,T2,T3
KmacKeyBlock	792	Covered	T1,T4,T13
KmacMsgFeed	782	Covered	T1,T2,T3
KmacPrefix	779	Covered	T1,T4,T13
KmacTerminalError	834	Covered	T3,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	826	Covered	T1,T2,T4
KmacDigest->KmacTerminalError	848	Covered	T52,T53,T54
KmacIdle->KmacMsgFeed	782	Covered	T1,T2,T3
KmacIdle->KmacPrefix	779	Covered	T1,T4,T13
KmacIdle->KmacTerminalError	848	Covered	T36,T10,T11
KmacKeyBlock->KmacMsgFeed	801	Covered	T1,T4,T13
KmacKeyBlock->KmacTerminalError	848	Covered	T5,T55,T56
KmacMsgFeed->KmacDigest	817	Covered	T1,T2,T4
KmacMsgFeed->KmacIdle	814	Covered	T1,T4,T15
KmacMsgFeed->KmacTerminalError	848	Covered	T3,T6,T44
KmacPrefix->KmacKeyBlock	792	Covered	T1,T4,T13
KmacPrefix->KmacMsgFeed	792	Covered	T1,T4,T15
KmacPrefix->KmacTerminalError	848	Covered	T7,T57,T58

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	426	2	2	100.00
TERNARY	635	4	4	100.00
TERNARY	643	4	4	100.00
TERNARY	648	2	2	100.00
CASE	434	6	5	83.33
IF	488	3	3	100.00
IF	561	3	3	100.00
IF	651	2	2	100.00
CASE	689	6	4	66.67
IF	765	2	2	100.00
CASE	774	15	15	100.00
IF	847	2	2	100.00
TERNARY	1158	2	2	100.00
IF	1419	4	3	75.00
IF	1442	3	3	100.00
IF	1471	3	3	100.00
IF	1481	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	635	(msgfifo_full) ? 
-2-:	635	(msgfifo_empty_negedge) ? 
-3-:	635	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T25,T36
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	643	(app_active) ? 
-2-:	643	((sha3_fsm != StAbsorb)) ? 
-3-:	643	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T15
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	648	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T39,T29

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T4
CmdManualRun	Covered	T1,T4,T13
CmdDone	Covered	T1,T2,T4
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	if ((!rst_ni))
-2-:	563	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	651	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	689	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T3,T5,T6
errchecker_err.valid	Covered	T19,T43,T47
sha3_err.valid	Covered	T1,T23,T24
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	765	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	774	case (kmac_st)
-2-:	776	if ((kmac_cmd == CmdStart))
-3-:	778	if ((CShake == app_sha3_mode))
-4-:	791	if (sha3_block_processed)
-5-:	792	(app_kmac_en) ? 
-6-:	800	if (sha3_block_processed)
-7-:	809	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	815	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	825	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T4,T13
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T4,T13
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T1,T4,T15
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T4,T13
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T4,T13
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T4,T13
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T1,T4,T15
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T3,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	847	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1158	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1419	if ((!rst_ni))
-2-:	1421	if (alert_recov_operation)
-3-:	1423	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1442	if ((!rst_ni))
-2-:	1444	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1471	if ((!rst_ni))
-2-:	1473	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1481	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1282978	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	338178	0	0
EntrySizeRegSameToEntrySizePkg_A	1028	1028	0	0
ErrProcessedLatched_A	2147483647	433	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	90	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	90	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	90	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacFsmCheck_A	2147483647	90	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	90	0	0
FpvSecCmRoundCountCheck_A	2147483647	90	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	90	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	90	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	90	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1028	1028	0	0
NumEntriesRegSameToNumEntriesPkg_A	1028	1028	0	0
PrefixRegSameToPrefixPkg_A	1028	1028	0	0
SecretKeyDivideBy32_A	1028	1028	0	0
Sha3AbsorbedPulse_A	2147483647	348638	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1282978	0	0
T1	193936	2026	0	0
T2	644072	1238	0	0
T3	4803	2	0	0
T4	190252	1057	0	0
T5	4099	3	0	0
T13	138747	418	0	0
T14	174037	7474	0	0
T15	39907	112	0	0
T16	827342	1247	0	0
T17	78108	71	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	338178	0	0
T1	193936	347	0	0
T2	644072	382	0	0
T3	4803	1	0	0
T4	190252	193	0	0
T5	4099	1	0	0
T13	138747	58	0	0
T14	174037	2267	0	0
T15	39907	18	0	0
T16	827342	381	0	0
T17	78108	10	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	433	0	0
T20	65594	7	0	0
T21	0	16	0	0
T22	0	7	0	0
T26	470304	0	0	0
T48	958	0	0	0
T59	0	3	0	0
T60	0	5	0	0
T61	0	5	0	0
T62	0	1	0	0
T63	0	17	0	0
T64	0	5	0	0
T65	0	6	0	0
T66	146120	0	0	0
T67	16393	0	0	0
T68	388442	0	0	0
T69	145503	0	0	0
T70	649193	0	0	0
T71	249376	0	0	0
T72	114406	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T10	300728	20	0	0
T11	0	20	0	0
T12	0	20	0	0
T22	57485	0	0	0
T59	19891	0	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	179936	0	0	0
T76	805997	0	0	0
T77	16540	0	0	0
T78	609972	0	0	0
T79	678320	0	0	0
T80	489163	0	0	0
T81	1016	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348638	0	0
T1	193936	353	0	0
T2	644072	390	0	0
T3	4803	0	0	0
T4	190252	193	0	0
T5	4099	0	0	0
T13	138747	58	0	0
T14	174037	2337	0	0
T15	39907	18	0	0
T16	827342	390	0	0
T17	78108	10	0	0
T18	0	12	0	0
T19	0	115	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	193936	193896	0	0
T2	644072	644064	0	0
T3	4803	4642	0	0
T4	190252	190245	0	0
T5	4099	3910	0	0
T13	138747	138648	0	0
T14	174037	174036	0	0
T15	39907	39854	0	0
T16	827342	827333	0	0
T17	78108	78045	0	0