Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

255548898

1

T1

23716

T2

1385

T3

50519

full_word

201033264

1

T1

38420

T2

8939

T3

80125

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	456581892	1			T1	62136		T2	10324		T3	130644
auto[TlIntgErrCmd]	89	1			T121	7		T122	5		T123	3
auto[TlIntgErrData]	85	1			T121	2		T122	8		T123	3
auto[TlIntgErrBoth]	96	1			T121	1		T122	7		T123	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240492007

1

T1

43432

T2

6935

T3

86343

auto[1]

216090155

1

T1

18704

T2

3389

T3

44301

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152903546	1			T1	14955		T2	782		T3	30259
auto[TlIntgErrNone]	partial	auto[1]	102645099	1			T1	8761		T2	603		T3	20260
auto[TlIntgErrNone]	full_word	auto[0]	87588341	1			T1	28477		T2	6153		T3	56084
auto[TlIntgErrNone]	full_word	auto[1]	113444906	1			T1	9943		T2	2786		T3	24041
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T121	2		T122	3		T123	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T121	5		T122	1		T123	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T122	1		T181	1		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T186	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T121	1		T122	4		T123	1
auto[TlIntgErrData]	partial	auto[1]	35	1			T121	1		T122	3		T123	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T184	1		T187	1		T188	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T122	1		T181	1		T189	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T121	1		T122	2		T123	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T122	5		T123	3		T180	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T190	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T182	1		T191	1		-	-