Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	263645	0	0
entropy_period_rd_A	2147483647	1788	0	0
intr_enable_rd_A	2147483647	2256	0	0
prefix_0_rd_A	2147483647	1711	0	0
prefix_10_rd_A	2147483647	1497	0	0
prefix_1_rd_A	2147483647	1501	0	0
prefix_2_rd_A	2147483647	1565	0	0
prefix_3_rd_A	2147483647	1740	0	0
prefix_4_rd_A	2147483647	1524	0	0
prefix_5_rd_A	2147483647	1531	0	0
prefix_6_rd_A	2147483647	1579	0	0
prefix_7_rd_A	2147483647	1589	0	0
prefix_8_rd_A	2147483647	1577	0	0
prefix_9_rd_A	2147483647	1534	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	263645	0	0
T48	211691	29886	0	0
T49	0	20305	0	0
T50	0	52343	0	0
T91	0	24199	0	0
T92	0	66418	0	0
T93	3217	0	0	0
T96	0	16856	0	0
T128	0	31601	0	0
T129	0	19043	0	0
T130	0	86	0	0
T131	0	122	0	0
T132	88187	0	0	0
T133	613550	0	0	0
T134	174029	0	0	0
T135	511554	0	0	0
T136	114873	0	0	0
T137	193266	0	0	0
T138	988926	0	0	0
T139	187154	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1788	0	0
T49	198897	32	0	0
T96	0	58	0	0
T102	0	17	0	0
T103	0	29	0	0
T113	0	7	0	0
T122	0	123	0	0
T148	0	371	0	0
T149	0	9	0	0
T150	0	23	0	0
T151	0	43	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2256	0	0
T49	198897	41	0	0
T96	0	31	0	0
T103	0	23	0	0
T122	0	149	0	0
T124	0	5	0	0
T148	0	416	0	0
T149	0	26	0	0
T150	0	12	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0
T161	0	5	0	0
T162	0	22	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1711	0	0
T49	198897	58	0	0
T96	0	62	0	0
T102	0	10	0	0
T103	0	19	0	0
T113	0	6	0	0
T122	0	75	0	0
T148	0	448	0	0
T149	0	9	0	0
T150	0	7	0	0
T151	0	19	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1497	0	0
T49	198897	19	0	0
T96	0	54	0	0
T102	0	7	0	0
T103	0	31	0	0
T113	0	2	0	0
T122	0	55	0	0
T148	0	396	0	0
T149	0	11	0	0
T150	0	20	0	0
T151	0	13	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1501	0	0
T49	198897	54	0	0
T96	0	20	0	0
T102	0	14	0	0
T103	0	29	0	0
T113	0	13	0	0
T122	0	86	0	0
T148	0	368	0	0
T149	0	13	0	0
T150	0	27	0	0
T151	0	22	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T49	198897	30	0	0
T96	0	60	0	0
T102	0	4	0	0
T103	0	22	0	0
T113	0	4	0	0
T122	0	85	0	0
T148	0	438	0	0
T149	0	9	0	0
T150	0	25	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0
T163	0	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1740	0	0
T49	198897	36	0	0
T96	0	73	0	0
T102	0	16	0	0
T103	0	14	0	0
T113	0	7	0	0
T122	0	63	0	0
T148	0	475	0	0
T149	0	7	0	0
T150	0	23	0	0
T151	0	21	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1524	0	0
T49	198897	38	0	0
T96	0	42	0	0
T102	0	11	0	0
T103	0	28	0	0
T113	0	8	0	0
T122	0	66	0	0
T148	0	465	0	0
T149	0	9	0	0
T150	0	15	0	0
T151	0	20	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1531	0	0
T49	198897	33	0	0
T96	0	55	0	0
T102	0	16	0	0
T103	0	15	0	0
T113	0	9	0	0
T122	0	84	0	0
T148	0	396	0	0
T149	0	3	0	0
T150	0	8	0	0
T151	0	23	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1579	0	0
T49	198897	25	0	0
T96	0	31	0	0
T102	0	11	0	0
T103	0	18	0	0
T113	0	8	0	0
T122	0	70	0	0
T148	0	436	0	0
T149	0	8	0	0
T150	0	10	0	0
T151	0	16	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1589	0	0
T49	198897	46	0	0
T96	0	52	0	0
T102	0	3	0	0
T103	0	27	0	0
T113	0	5	0	0
T122	0	99	0	0
T148	0	433	0	0
T149	0	6	0	0
T150	0	23	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0
T164	0	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1577	0	0
T49	198897	23	0	0
T96	0	23	0	0
T102	0	8	0	0
T103	0	33	0	0
T113	0	12	0	0
T122	0	95	0	0
T148	0	460	0	0
T149	0	3	0	0
T150	0	23	0	0
T151	0	24	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1534	0	0
T49	198897	32	0	0
T96	0	57	0	0
T102	0	14	0	0
T103	0	22	0	0
T113	0	3	0	0
T122	0	83	0	0
T148	0	424	0	0
T149	0	2	0	0
T150	0	20	0	0
T151	0	15	0	0
T152	308356	0	0	0
T153	8925	0	0	0
T154	372230	0	0	0
T155	708007	0	0	0
T156	137108	0	0	0
T157	638673	0	0	0
T158	25535	0	0	0
T159	177898	0	0	0
T160	17015	0	0	0