Module Definition
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Module Instance : tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.46 98.55 92.86 100.00 92.00 88.89 u_kmac_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sha3.u_pad.u_prefix_slicer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 99.38 88.37 100.00 95.70 100.00 u_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_staterd.gen_slicer[0].u_state_slice

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.00 100.00 70.00 100.00 u_staterd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_slicer
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN2711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
27 1 1


Assert Coverage for Module : prim_slicer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ValidWidth_A 3123 3123 0 0


ValidWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3123 3123 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T12 3 3 0 0
T13 3 3 0 0
T14 3 3 0 0
T15 3 3 0 0
T16 3 3 0 0
T19 3 3 0 0

Line Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN2711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
27 1 1


Assert Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ValidWidth_A 1041 1041 0 0


ValidWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_pad.u_prefix_slicer
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN2711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
27 1 1


Assert Coverage for Instance : tb.dut.u_sha3.u_pad.u_prefix_slicer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ValidWidth_A 1041 1041 0 0


ValidWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_staterd.gen_slicer[0].u_state_slice
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN2711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
27 1 1


Assert Coverage for Instance : tb.dut.u_staterd.gen_slicer[0].u_state_slice
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ValidWidth_A 1041 1041 0 0


ValidWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%