Module Definition
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Module : kmac_staterd
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 100.00 70.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_staterd.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_staterd 90.00 100.00 70.00 100.00



Module Instance : tb.dut.u_staterd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 100.00 70.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.87 89.84 81.09 88.54 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_slicer[0].u_state_slice 100.00 100.00 100.00
u_tlul_adapter 89.66 89.34 81.51 87.78 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : kmac_staterd
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS8744100.00
CONT_ASSIGN9511100.00
ALWAYS10133100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_staterd.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_staterd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
87 1 1
88 1 1
89 1 1
90 1 1
MISSING_ELSE
95 1 1
101 2 2
102 1 1
121 1 1
123 1 1


Cond Coverage for Module : kmac_staterd
TotalCoveredPercent
Conditions10770.00
Logical10770.00
Non-Logical00
Event00

 LINE       89
 EXPRESSION (tlram_req & ((~tlram_we)))
             ----1----   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       95
 EXPRESSION (tlram_req & ((~tlram_we)))
             ----1----   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       102
 EXPRESSION (tlram_req & ((!tlram_we)))
             ----1----   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       123
 EXPRESSION ((int'(addr_sel) < Share) ? muxed_state[addr_sel] : 0)
             ------------1-----------
-1-StatusTests
0UnreachableT1,T2,T4
1CoveredT1,T2,T3

Branch Coverage for Module : kmac_staterd
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 123 1 1 100.00
IF 87 3 3 100.00
IF 101 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_staterd.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_staterd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 123 ((int'(addr_sel) < Share)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable T1,T2,T4


LineNo. Expression -1-: 87 if ((!rst_ni)) -2-: 89 if ((tlram_req & (~tlram_we)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%