Module Definition
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Module : kmac_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.46 98.55 92.86 100.00 92.00 88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_kmac_core 94.46 98.55 92.86 100.00 92.00 88.89



Module Instance : tb.dut.u_kmac_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.46 98.55 92.86 100.00 92.00 88.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.80 98.75 92.86 100.00 100.00 92.31 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_key_slicer[0].u_key_slicer 100.00 100.00 100.00
u_key_index_count 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : kmac_core
Line No.TotalCoveredPercent
TOTAL696898.55
CONT_ASSIGN15311100.00
ALWAYS16133100.00
ALWAYS1663030100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26511100.00
ALWAYS2686583.33
CONT_ASSIGN28711100.00
ALWAYS30766100.00
ALWAYS33866100.00
CONT_ASSIGN37211100.00
CONT_ASSIGN39411100.00
ALWAYS42066100.00
CONT_ASSIGN43111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
153 1 1
161 3 3
166 1 1
168 1 1
169 1 1
171 1 1
173 1 1
174 1 1
176 1 1
178 1 1
180 1 1
181 1 1
183 1 1
190 1 1
191 1 1
193 1 1
194 1 1
196 1 1
197 1 1
199 1 1
201 1 1
207 1 1
208 1 1
210 1 1
212 1 1
217 1 1
218 1 1
220 1 1
226 1 1
227 1 1
240 1 1
241 1 1
MISSING_ELSE
251 1 1
252 1 1
253 1 1
254 1 1
258 1 1
260 1 1
265 1 1
268 1 1
269 1 1
270 1 1
271 0 1
272 1 1
274 1 1
MISSING_ELSE
287 1 1
307 1 1
317 1 1
318 1 1
319 1 1
320 1 1
321 1 1
338 1 1
341 1 1
345 1 1
349 1 1
353 1 1
358 1 1
372 1 1
394 1 1
420 1 1
421 1 1
422 1 1
423 1 1
424 1 1
425 1 1
431 1 1


Cond Coverage for Module : kmac_core
TotalCoveredPercent
Conditions282692.86
Logical282692.86
Non-Logical00
Event00

 LINE       180
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---
-1--2-StatusTests
01CoveredT2,T3,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       207
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT2,T3,T9

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       252
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       253
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       254
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       258
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       260
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       265
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       270
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T9
11Not Covered

 LINE       394
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       431
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Module : kmac_core
Summary for FSM :: st
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 8 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StKey 181 Covered T1,T2,T3
StKmacFlush 208 Covered T2,T3,T9
StKmacIdle 183 Covered T1,T2,T3
StKmacMsg 194 Covered T1,T2,T3
StTerminalError 241 Covered T1,T4,T5


transitionsLine No.CoveredTests
StKey->StKmacMsg 194 Covered T1,T2,T3
StKey->StTerminalError 241 Covered T7,T57,T56
StKmacFlush->StKmacIdle 218 Covered T2,T3,T9
StKmacFlush->StTerminalError 241 Covered T52,T53,T93
StKmacIdle->StKey 181 Covered T1,T2,T3
StKmacIdle->StTerminalError 241 Covered T4,T5,T6
StKmacMsg->StKmacFlush 208 Covered T2,T3,T9
StKmacMsg->StTerminalError 241 Covered T1,T8,T32



Branch Coverage for Module : kmac_core
Line No.TotalCoveredPercent
Branches 50 46 92.00
TERNARY 251 2 2 100.00
TERNARY 252 2 2 100.00
TERNARY 253 2 2 100.00
TERNARY 254 2 2 100.00
TERNARY 258 2 2 100.00
TERNARY 260 2 2 100.00
TERNARY 265 2 2 100.00
IF 161 2 2 100.00
CASE 178 10 10 100.00
IF 240 2 2 100.00
IF 268 4 3 75.00
CASE 307 6 5 83.33
CASE 420 6 5 83.33
CASE 338 6 5 83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 251 (en_kmac_datapath) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 252 (en_kmac_datapath) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 253 (en_kmac_datapath) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 254 (en_kmac_datapath) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 258 (en_key_write) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 260 (en_key_write) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 265 (kmac_en_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 161 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 178 case (st) -2-: 180 if ((kmac_en_i && start_i)) -3-: 193 if (sent_blocksize) -4-: 207 if ((process_i || process_latched)) -5-: 217 if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:
-1--2--3--4--5-StatusTests
StKmacIdle 1 - - - Covered T1,T2,T3
StKmacIdle 0 - - - Covered T1,T2,T3
StKey - 1 - - Covered T1,T2,T3
StKey - 0 - - Covered T1,T2,T3
StKmacMsg - - 1 - Covered T2,T3,T9
StKmacMsg - - 0 - Covered T1,T2,T3
StKmacFlush - - - 1 Covered T2,T3,T9
StKmacFlush - - - 0 Covered T2,T3,T9
StTerminalError - - - - Covered T1,T4,T5
default - - - - Covered T10,T11,T12


LineNo. Expression -1-: 240 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 268 if ((!rst_ni)) -2-: 270 if ((process_i && (!process_o))) -3-: 272 if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Covered T2,T3,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 case (key_len_i)

Branches:
-1-StatusTests
Key128 Covered T1,T2,T3
Key192 Covered T2,T3,T9
Key256 Covered T2,T3,T9
Key384 Covered T2,T3,T9
Key512 Covered T1,T2,T3
default Not Covered


LineNo. Expression -1-: 420 case (strength_i)

Branches:
-1-StatusTests
L128 Covered T1,T2,T3
L224 Covered T14,T87,T88
L256 Covered T1,T2,T3
L384 Covered T3,T9,T14
L512 Covered T2,T13,T14
default Not Covered


LineNo. Expression -1-: 338 case (key_len_i)

Branches:
-1-StatusTests
Key128 Covered T1,T2,T3
Key192 Covered T2,T3,T9
Key256 Covered T2,T3,T9
Key384 Covered T2,T3,T9
Key512 Covered T1,T2,T3
default Not Covered


Assert Coverage for Module : kmac_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 8 88.89
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 8 88.89




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckOnlyInMessageState_A 2147483647 7580133 0 0
KeyDataStableWhenValid_M 2147483647 336780582 0 0
KeyLengthStableWhenValid_M 2147483647 336780582 0 0
KmacEnStable_M 2147483647 20959 0 0
MaxKeyLenMatchToKey512_A 1023 1023 0 0
ModeStable_M 2147483647 32410 0 0
ProcessLatchedCleared_A 2147483647 0 0 0
StrengthStable_M 2147483647 38724 0 0
u_state_regs_A 2147483647 2147483647 0 0


AckOnlyInMessageState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7580133 0 0
T1 4064 1 0 0
T2 849000 27868 0 0
T3 401280 5412 0 0
T9 624338 5064 0 0
T13 435786 49924 0 0
T14 998584 5609 0 0
T15 945675 0 0 0
T16 619382 3821 0 0
T17 472943 1896 0 0
T20 1393 0 0 0
T64 0 56743 0 0
T88 0 142 0 0

KeyDataStableWhenValid_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 336780582 0 0
T1 4064 96 0 0
T2 849000 571422 0 0
T3 401280 213058 0 0
T9 624338 315086 0 0
T13 435786 322962 0 0
T14 998584 626344 0 0
T15 945675 0 0 0
T16 619382 341055 0 0
T17 472943 219835 0 0
T20 1393 0 0 0
T64 0 149798 0 0
T88 0 50123 0 0

KeyLengthStableWhenValid_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 336780582 0 0
T1 4064 96 0 0
T2 849000 571422 0 0
T3 401280 213058 0 0
T9 624338 315086 0 0
T13 435786 322962 0 0
T14 998584 626344 0 0
T15 945675 0 0 0
T16 619382 341055 0 0
T17 472943 219835 0 0
T20 1393 0 0 0
T64 0 149798 0 0
T88 0 50123 0 0

KmacEnStable_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 20959 0 0
T1 4064 1 0 0
T2 849000 31 0 0
T3 401280 82 0 0
T9 624338 73 0 0
T13 435786 43 0 0
T14 998584 58 0 0
T15 945675 0 0 0
T16 619382 33 0 0
T17 472943 20 0 0
T20 1393 0 0 0
T21 0 7 0 0
T88 0 31 0 0

MaxKeyLenMatchToKey512_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0

ModeStable_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 32410 0 0
T1 4064 1 0 0
T2 849000 31 0 0
T3 401280 132 0 0
T9 624338 148 0 0
T13 435786 43 0 0
T14 998584 61 0 0
T15 945675 0 0 0
T16 619382 99 0 0
T17 472943 42 0 0
T18 0 1 0 0
T20 1393 0 0 0
T88 0 36 0 0

ProcessLatchedCleared_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 0 0 0

StrengthStable_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 38724 0 0
T1 4064 3 0 0
T2 849000 35 0 0
T3 401280 152 0 0
T9 624338 151 0 0
T13 435786 51 0 0
T14 998584 68 0 0
T15 945675 2 0 0
T16 619382 104 0 0
T17 472943 40 0 0
T20 1393 1 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%