Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : kmac
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.19 96.27 93.33 63.67 100.00 93.85 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 97.24 96.27 93.33 100.00 100.00 93.85 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.24 96.27 93.33 100.00 100.00 93.85 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.48 95.89 92.30 100.00 67.77 94.11 98.84


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
intr_fifo_empty 86.94 90.00 77.78 80.00 100.00
intr_kmac_done 93.75 100.00 75.00 100.00 100.00
intr_kmac_err 93.75 100.00 75.00 100.00 100.00
kmac_csr_assert 100.00 100.00
sha3pad_assert_cov_if 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_app_intf 81.00 91.14 87.72 37.78 88.35 100.00
u_errchk 92.70 97.22 96.67 73.33 96.30 100.00
u_kmac_core 95.80 98.75 92.86 100.00 100.00 92.31 90.91
u_msgfifo 97.75 100.00 95.00 100.00 93.75 100.00
u_prim_lc_sync 100.00 100.00 100.00 100.00
u_reg 98.98 99.19 96.97 100.00 98.72 100.00
u_sha3 92.16 91.91 88.51 100.00 80.56 92.00 100.00
u_sha3_done_sender 100.00 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_staterd 89.97 89.88 81.45 88.54 100.00
u_tlul_adapter_msgfifo 80.11 87.12 74.69 77.38 81.25

Line Coverage for Module : kmac
Line No.TotalCoveredPercent
TOTAL16115596.27
ALWAYS34600
ALWAYS34622100.00
ALWAYS352100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42211100.00
CONT_ASSIGN42611100.00
ALWAYS42999100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46511100.00
CONT_ASSIGN46611100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47311100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47811100.00
CONT_ASSIGN48111100.00
ALWAYS48866100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51811100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53311100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN53700
CONT_ASSIGN53911100.00
CONT_ASSIGN54311100.00
CONT_ASSIGN54511100.00
CONT_ASSIGN54611100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55311100.00
ALWAYS56155100.00
CONT_ASSIGN57111100.00
CONT_ASSIGN57711100.00
CONT_ASSIGN57811100.00
CONT_ASSIGN57911100.00
CONT_ASSIGN58711100.00
CONT_ASSIGN62911100.00
CONT_ASSIGN63511100.00
CONT_ASSIGN64311100.00
CONT_ASSIGN64811100.00
ALWAYS65155100.00
CONT_ASSIGN67911100.00
CONT_ASSIGN68411100.00
ALWAYS6877571.43
CONT_ASSIGN72311100.00
CONT_ASSIGN728100.00
CONT_ASSIGN73511100.00
CONT_ASSIGN74511100.00
ALWAYS76533100.00
ALWAYS7692828100.00
CONT_ASSIGN92011100.00
CONT_ASSIGN92311100.00
CONT_ASSIGN99211100.00
CONT_ASSIGN99411100.00
CONT_ASSIGN102911100.00
CONT_ASSIGN103411100.00
CONT_ASSIGN103511100.00
CONT_ASSIGN103711100.00
CONT_ASSIGN104000
ALWAYS116100
ALWAYS116122100.00
CONT_ASSIGN1315100.00
CONT_ASSIGN131611100.00
CONT_ASSIGN131711100.00
CONT_ASSIGN132711100.00
CONT_ASSIGN132811100.00
CONT_ASSIGN133411100.00
CONT_ASSIGN133511100.00
CONT_ASSIGN133611100.00
CONT_ASSIGN133711100.00
CONT_ASSIGN134011100.00
CONT_ASSIGN134911100.00
CONT_ASSIGN139111100.00
CONT_ASSIGN140511100.00
CONT_ASSIGN141211100.00
CONT_ASSIGN141711100.00
ALWAYS14236583.33
CONT_ASSIGN143211100.00
CONT_ASSIGN143411100.00
ALWAYS144644100.00
CONT_ASSIGN145211100.00
ALWAYS147544100.00
ALWAYS148533100.00
CONT_ASSIGN149611100.00
CONT_ASSIGN150011100.00
CONT_ASSIGN150211100.00
CONT_ASSIGN150211100.00
CONT_ASSIGN150211100.00
CONT_ASSIGN150211100.00
CONT_ASSIGN150211100.00
CONT_ASSIGN150211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
346 1 1
347 1 1
352 0 1
421 1 1
422 1 1
426 1 1
429 1 1
430 1 1
431 1 1
432 1 1
434 1 1
436 1 1
440 1 1
444 1 1
448 1 1
464 1 1
465 1 1
466 1 1
469 1 1
473 1 1
474 1 1
478 1 1
481 1 1
488 1 1
489 1 1
490 1 1
491 1 1
492 1 1
493 1 1
MISSING_ELSE
MISSING_ELSE
513 1 1
518 1 1
525 1 1
528 1 1
529 1 1
530 1 1
532 1 1
533 1 1
535 1 1
537 unreachable
539 1 1
543 1 1
545 1 1
546 1 1
549 1 1
550 1 1
553 1 1
561 1 1
562 1 1
563 1 1
564 1 1
566 1 1
571 1 1
577 1 1
578 1 1
579 1 1
587 1 1
629 1 1
635 1 1
643 1 1
648 1 1
651 1 1
652 1 1
653 1 1
655 1 1
656 1 1
679 1 1
684 1 1
687 1 1
689 1 1
694 1 1
698 1 1
702 1 1
706 0 1
710 0 1
723 1 1
728 0 1
735 1 1
745 1 1
765 3 3
769 1 1
771 1 1
772 1 1
774 1 1
776 1 1
778 1 1
779 1 1
782 1 1
785 1 1
791 1 1
792 1 1
794 1 1
799 1 1
800 1 1
801 1 1
803 1 1
809 1 1
814 1 1
815 1 1
817 1 1
819 1 1
825 1 1
826 1 1
828 1 1
834 1 1
835 1 1
847 1 1
848 1 1
MISSING_ELSE
920 1 1
923 1 1
992 1 1
994 1 1
1029 1 1
1034 1 1
1035 1 1
1037 1 1
1040 unreachable
1161 1 1
1162 1 1
1315 0 1
1316 1 1
1317 1 1
1327 1 1
1328 1 1
1334 1 1
1335 1 1
1336 1 1
1337 1 1
1340 1 1
1349 1 1
1391 1 1
1405 1 1
1412 1 1
1417 1 1
1423 1 1
1424 1 1
1425 1 1
1426 0 1
1427 1 1
1428 1 1
MISSING_ELSE
1432 1 1
1434 1 1
1446 1 1
1447 1 1
1448 1 1
1449 1 1
MISSING_ELSE
1452 1 1
1475 1 1
1476 1 1
1477 1 1
1479 1 1
MISSING_ELSE
1485 1 1
1486 1 1
1489 1 1
1496 1 1
1500 1 1
1502 6 6


Cond Coverage for Module : kmac
TotalCoveredPercent
Conditions908493.33
Logical908493.33
Non-Logical00
Event00

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T9

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T41,T42

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T41,T42

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------
-1--2-StatusTests
01CoveredT43,T44,T45
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----
-1--2--3-StatusTests
011CoveredT2,T3,T9
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T22,T23

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T13,T16

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T9

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T9,T16

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T9

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------
-1-StatusTests
0CoveredT13,T38,T24
1CoveredT1,T2,T3

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT27,T46,T37
0010Not Covered
0100CoveredT1,T21,T27
1000CoveredT16,T24,T25

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010CoveredT10,T11,T12
0100Unreachable
1000CoveredT10,T11,T12

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001CoveredT10,T11,T12
000010Unreachable
000100CoveredT10,T11,T12
001000CoveredT10,T11,T12
010000CoveredT10,T11,T12
100000CoveredT10,T11,T12

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------
-1-StatusTests
0CoveredT2,T3,T9
1CoveredT1,T2,T3

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----
-1-StatusTests
0CoveredT3,T9,T16
1CoveredT1,T2,T3

 LINE       1029
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       1162
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T9

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------
-1--2-StatusTests
01CoveredT20,T47,T48
10CoveredT1,T2,T3
11CoveredT20,T47,T48

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------
-1--2-StatusTests
01CoveredT20,T47,T48
10CoveredT1,T2,T3
11CoveredT20,T47,T48

 LINE       1434
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010CoveredT10,T11,T12
00100CoveredT1,T4,T5
01000CoveredT10,T11,T12
10000Not Covered

Toggle Coverage for Module : kmac
TotalCoveredPercent
Totals 71 64 90.14
Total Bits 6534 4160 63.67
Total Bits 0->1 3267 2080 63.67
Total Bits 1->0 3267 2080 63.67

Ports 71 64 90.14
Port Bits 6534 4160 63.67
Port Bits 0->1 3267 2080 63.67
Port Bits 1->0 3267 2080 63.67

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T17,T4 Yes T1,T2,T3 INPUT
rst_shadowed_ni Yes Yes T1,T17,T4 Yes T1,T2,T3 INPUT
clk_edn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_edn_ni Yes Yes T1,T17,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T14,T16 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T15,T17 Yes T2,T15,T17 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T49,T50,T51 Yes T49,T50,T51 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T20,T47,T48 Yes T20,T47,T48 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T20,T47 Yes T1,T20,T47 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T20,T47,T48 Yes T20,T47,T48 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T20,T47 Yes T1,T20,T47 OUTPUT
keymgr_key_i.key[1:0][255:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
keymgr_key_i.valid Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
app_i[0].last Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[0].strb[7:0] Yes Yes T9,T17,T26 Yes T9,T17,T26 INPUT
app_i[0].data[63:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[0].valid Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT
app_i[1].last Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[1].strb[7:0] Yes Yes T9,T17,T26 Yes T9,T17,T26 INPUT
app_i[1].data[63:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[1].valid Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT
app_i[2].last Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[2].strb[7:0] Yes Yes T9,T17,T26 Yes T9,T17,T26 INPUT
app_i[2].data[63:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[2].valid Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT
app_o[0].error Yes Yes T1,T16,T21 Yes T1,T16,T21 OUTPUT
app_o[0].digest_share1[383:0] No No No OUTPUT
app_o[0].digest_share0[383:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[0].done Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[0].ready Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[1].error Yes Yes T16,T4,T24 Yes T16,T4,T24 OUTPUT
app_o[1].digest_share1[383:0] No No No OUTPUT
app_o[1].digest_share0[383:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[1].done Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[1].ready Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[2].error Yes Yes T16,T24,T25 Yes T16,T24,T25 OUTPUT
app_o[2].digest_share1[383:0] No No No OUTPUT
app_o[2].digest_share0[383:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[2].done Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[2].ready Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
entropy_o.edn_req No No No OUTPUT
entropy_i.edn_bus[31:0] No No No INPUT
entropy_i.edn_fips No No No INPUT
entropy_i.edn_ack No No No INPUT
lc_escalate_en_i[3:0] Yes Yes T4,T5,T32 Yes T4,T5,T32 INPUT
intr_kmac_done_o Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
intr_fifo_empty_o Yes Yes T13,T38,T24 Yes T13,T38,T24 OUTPUT
intr_kmac_err_o Yes Yes T1,T16,T21 Yes T1,T16,T21 OUTPUT
en_masking_o Unreachable Unreachable Unreachable OUTPUT
idle_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

FSM Coverage for Module : kmac
Summary for FSM :: kmac_st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 13 13 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: kmac_st
statesLine No.CoveredTests
KmacDigest 817 Covered T2,T3,T9
KmacIdle 785 Covered T1,T2,T3
KmacKeyBlock 792 Covered T1,T2,T3
KmacMsgFeed 782 Covered T1,T2,T3
KmacPrefix 779 Covered T1,T2,T3
KmacTerminalError 834 Covered T1,T4,T5


transitionsLine No.CoveredTests
KmacDigest->KmacIdle 826 Covered T2,T3,T9
KmacDigest->KmacTerminalError 848 Covered T5,T52,T53
KmacIdle->KmacMsgFeed 782 Covered T2,T3,T9
KmacIdle->KmacPrefix 779 Covered T1,T2,T3
KmacIdle->KmacTerminalError 848 Covered T10,T34,T11
KmacKeyBlock->KmacMsgFeed 801 Covered T1,T2,T3
KmacKeyBlock->KmacTerminalError 848 Covered T54,T55,T56
KmacMsgFeed->KmacDigest 817 Covered T2,T3,T9
KmacMsgFeed->KmacIdle 814 Covered T3,T9,T16
KmacMsgFeed->KmacTerminalError 848 Covered T1,T8,T32
KmacPrefix->KmacKeyBlock 792 Covered T1,T2,T3
KmacPrefix->KmacMsgFeed 792 Covered T3,T9,T16
KmacPrefix->KmacTerminalError 848 Covered T4,T7,T57



Branch Coverage for Module : kmac
Line No.TotalCoveredPercent
Branches 65 61 93.85
TERNARY 426 2 2 100.00
TERNARY 635 4 4 100.00
TERNARY 643 4 4 100.00
TERNARY 648 2 2 100.00
CASE 434 6 5 83.33
IF 488 3 3 100.00
IF 561 3 3 100.00
IF 651 2 2 100.00
CASE 689 6 4 66.67
IF 765 2 2 100.00
CASE 774 15 15 100.00
IF 847 2 2 100.00
TERNARY 1162 2 2 100.00
IF 1423 4 3 75.00
IF 1446 3 3 100.00
IF 1475 3 3 100.00
IF 1485 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 426 (cmd_update) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 635 (msgfifo_full) ? -2-: 635 (msgfifo_empty_negedge) ? -3-: 635 (msgfifo2kmac_process) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T3,T13,T16
0 1 - Covered T1,T2,T3
0 0 1 Covered T2,T3,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 643 (app_active) ? -2-: 643 ((sha3_fsm != StAbsorb)) ? -3-: 643 (msgfifo2kmac_process) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T3,T9,T16
0 1 - Covered T1,T2,T3
0 0 1 Covered T2,T3,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 648 (msgfifo_empty_gate) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T13,T38,T24


LineNo. Expression -1-: 434 case (kmac_cmd)

Branches:
-1-StatusTests
CmdStart Covered T1,T2,T3
CmdProcess Covered T2,T3,T9
CmdManualRun Covered T2,T3,T9
CmdDone Covered T2,T3,T9
CmdNone Covered T1,T2,T3
default Not Covered


LineNo. Expression -1-: 488 if ((!rst_ni)) -2-: 490 if (engine_stable)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 561 if ((!rst_ni)) -2-: 563 if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 651 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 689 case (1'b1)

Branches:
-1-StatusTests
app_err.valid Covered T1,T21,T27
errchecker_err.valid Covered T27,T46,T37
sha3_err.valid Covered T16,T24,T25
entropy_err.valid Not Covered
msgfifo_err.valid Not Covered
default Covered T1,T2,T3


LineNo. Expression -1-: 765 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 774 case (kmac_st) -2-: 776 if ((kmac_cmd == CmdStart)) -3-: 778 if ((CShake == app_sha3_mode)) -4-: 791 if (sha3_block_processed) -5-: 792 (app_kmac_en) ? -6-: 800 if (sha3_block_processed) -7-: 809 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done))) -8-: 815 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done))) -9-: 825 if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
KmacIdle 1 1 - - - - - - Covered T1,T2,T3
KmacIdle 1 0 - - - - - - Covered T2,T3,T9
KmacIdle 0 - - - - - - - Covered T1,T2,T3
KmacPrefix - - 1 1 - - - - Covered T1,T2,T3
KmacPrefix - - 1 0 - - - - Covered T3,T9,T16
KmacPrefix - - 0 - - - - - Covered T1,T2,T3
KmacKeyBlock - - - - 1 - - - Covered T1,T2,T3
KmacKeyBlock - - - - 0 - - - Covered T1,T2,T3
KmacMsgFeed - - - - - 1 - - Covered T3,T9,T16
KmacMsgFeed - - - - - 0 1 - Covered T2,T3,T9
KmacMsgFeed - - - - - 0 0 - Covered T1,T2,T3
KmacDigest - - - - - - - 1 Covered T2,T3,T9
KmacDigest - - - - - - - 0 Covered T2,T3,T9
KmacTerminalError - - - - - - - - Covered T1,T4,T5
default - - - - - - - - Covered T10,T11,T12


LineNo. Expression -1-: 847 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 1162 (reg_state_valid) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 1423 if ((!rst_ni)) -2-: 1425 if (alert_recov_operation) -3-: 1427 if (err_processed)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Covered T21,T22,T23
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1446 if ((!rst_ni)) -2-: 1448 if (alert_fatal)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1475 if ((!rst_ni)) -2-: 1477 if (alerts[1])

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1485 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : kmac
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 30 30 100.00 30 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 30 30 100.00 30 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 2147483647 2147483647 0 0
CmdSparse_M 2147483647 1264590 0 0
EnMaskingKnown_A 2147483647 2147483647 0 0
EntropyReadyLatched_A 2147483647 335127 0 0
EntrySizeRegSameToEntrySizePkg_A 1023 1023 0 0
ErrProcessedLatched_A 2147483647 497 0 0
FifoEmpty_A 2147483647 2147483647 0 0
FpvSecCmErrorCheckFsmCheck_A 2147483647 70 0 0
FpvSecCmKeccackFsmCheck_A 2147483647 70 0 0
FpvSecCmKeyIndexCountCheck_A 2147483647 70 0 0
FpvSecCmKmacAppFsmCheck_A 2147483647 70 0 0
FpvSecCmKmacCoreFsmCheck_A 2147483647 70 0 0
FpvSecCmKmacFsmCheck_A 2147483647 70 0 0
FpvSecCmRegWeOnehotCheck_A 2147483647 70 0 0
FpvSecCmRoundCountCheck_A 2147483647 70 0 0
FpvSecCmSHA3FsmCheck_A 2147483647 70 0 0
FpvSecCmSHA3padFsmCheck_A 2147483647 70 0 0
FpvSecCmSentMsgCountCheck_A 2147483647 70 0 0
KmacCmd_A 2147483647 2147483647 0 0
KmacDone_A 2147483647 2147483647 0 0
KmacErr_A 2147483647 2147483647 0 0
KmacStKnown_A 2147483647 2147483647 0 0
NumAlerts2_A 1023 1023 0 0
NumEntriesRegSameToNumEntriesPkg_A 1023 1023 0 0
PrefixRegSameToPrefixPkg_A 1023 1023 0 0
SecretKeyDivideBy32_A 1023 1023 0 0
Sha3AbsorbedPulse_A 2147483647 345653 0 0
TlOAReadyKnown_A 2147483647 2147483647 0 0
TlODValidKnown_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

CmdSparse_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1264590 0 0
T1 4064 2 0 0
T2 849000 477 0 0
T3 401280 965 0 0
T9 624338 780 0 0
T13 435786 728 0 0
T14 998584 945 0 0
T15 945675 786 0 0
T16 619382 491 0 0
T17 472943 227 0 0
T18 0 7905 0 0
T20 1393 0 0 0

EnMaskingKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

EntropyReadyLatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 335127 0 0
T1 4064 1 0 0
T2 849000 65 0 0
T3 401280 162 0 0
T9 624338 147 0 0
T13 435786 104 0 0
T14 998584 134 0 0
T15 945675 234 0 0
T16 619382 95 0 0
T17 472943 53 0 0
T18 0 2208 0 0
T20 1393 0 0 0

EntrySizeRegSameToEntrySizePkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0

ErrProcessedLatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 497 0 0
T21 23780 5 0 0
T22 0 8 0 0
T23 0 1 0 0
T26 657349 0 0 0
T27 625539 0 0 0
T35 0 5 0 0
T48 1446 0 0 0
T58 0 16 0 0
T59 0 4 0 0
T60 0 2 0 0
T61 0 17 0 0
T62 0 12 0 0
T63 0 5 0 0
T64 217067 0 0 0
T65 591479 0 0 0
T66 209542 0 0 0
T67 256714 0 0 0
T68 17024 0 0 0
T69 107438 0 0 0

FifoEmpty_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

FpvSecCmErrorCheckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmKeccackFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmKeyIndexCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmKmacAppFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmKmacCoreFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmKmacFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmRoundCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmSHA3FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmSHA3padFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmSentMsgCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

KmacCmd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

KmacDone_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

KmacErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

KmacStKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

NumAlerts2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0

NumEntriesRegSameToNumEntriesPkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0

PrefixRegSameToPrefixPkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0

SecretKeyDivideBy32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0

Sha3AbsorbedPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 345653 0 0
T2 849000 66 0 0
T3 401280 162 0 0
T9 624338 147 0 0
T13 435786 105 0 0
T14 998584 134 0 0
T15 945675 246 0 0
T16 619382 95 0 0
T17 472943 54 0 0
T18 431948 2265 0 0
T19 0 246 0 0
T20 1393 0 0 0

TlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

TlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL16115596.27
ALWAYS34600
ALWAYS34622100.00
ALWAYS352100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42211100.00
CONT_ASSIGN42611100.00
ALWAYS42999100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46511100.00
CONT_ASSIGN46611100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47311100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47811100.00
CONT_ASSIGN48111100.00
ALWAYS48866100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51811100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53311100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN53700
CONT_ASSIGN53911100.00
CONT_ASSIGN54311100.00
CONT_ASSIGN54511100.00
CONT_ASSIGN54611100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55311100.00
ALWAYS56155100.00
CONT_ASSIGN57111100.00
CONT_ASSIGN57711100.00
CONT_ASSIGN57811100.00
CONT_ASSIGN57911100.00
CONT_ASSIGN58711100.00
CONT_ASSIGN62911100.00
CONT_ASSIGN63511100.00
CONT_ASSIGN64311100.00
CONT_ASSIGN64811100.00
ALWAYS65155100.00
CONT_ASSIGN67911100.00
CONT_ASSIGN68411100.00
ALWAYS6877571.43
CONT_ASSIGN72311100.00
CONT_ASSIGN728100.00
CONT_ASSIGN73511100.00
CONT_ASSIGN74511100.00
ALWAYS76533100.00
ALWAYS7692828100.00
CONT_ASSIGN92011100.00
CONT_ASSIGN92311100.00
CONT_ASSIGN99211100.00
CONT_ASSIGN99411100.00
CONT_ASSIGN102911100.00
CONT_ASSIGN103411100.00
CONT_ASSIGN103511100.00
CONT_ASSIGN103711100.00
CONT_ASSIGN104000
ALWAYS116100
ALWAYS116122100.00
CONT_ASSIGN1315100.00
CONT_ASSIGN131611100.00
CONT_ASSIGN131711100.00
CONT_ASSIGN132711100.00
CONT_ASSIGN132811100.00
CONT_ASSIGN133411100.00
CONT_ASSIGN133511100.00
CONT_ASSIGN133611100.00
CONT_ASSIGN133711100.00
CONT_ASSIGN134011100.00
CONT_ASSIGN134911100.00
CONT_ASSIGN139111100.00
CONT_ASSIGN140511100.00
CONT_ASSIGN141211100.00
CONT_ASSIGN141711100.00
ALWAYS14236583.33
CONT_ASSIGN143211100.00
CONT_ASSIGN143411100.00
ALWAYS144644100.00
CONT_ASSIGN145211100.00
ALWAYS147544100.00
ALWAYS148533100.00
CONT_ASSIGN149611100.00
CONT_ASSIGN150011100.00
CONT_ASSIGN150211100.00
CONT_ASSIGN150211100.00
CONT_ASSIGN150211100.00
CONT_ASSIGN150211100.00
CONT_ASSIGN150211100.00
CONT_ASSIGN150211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
346 1 1
347 1 1
352 0 1
421 1 1
422 1 1
426 1 1
429 1 1
430 1 1
431 1 1
432 1 1
434 1 1
436 1 1
440 1 1
444 1 1
448 1 1
464 1 1
465 1 1
466 1 1
469 1 1
473 1 1
474 1 1
478 1 1
481 1 1
488 1 1
489 1 1
490 1 1
491 1 1
492 1 1
493 1 1
MISSING_ELSE
MISSING_ELSE
513 1 1
518 1 1
525 1 1
528 1 1
529 1 1
530 1 1
532 1 1
533 1 1
535 1 1
537 unreachable
539 1 1
543 1 1
545 1 1
546 1 1
549 1 1
550 1 1
553 1 1
561 1 1
562 1 1
563 1 1
564 1 1
566 1 1
571 1 1
577 1 1
578 1 1
579 1 1
587 1 1
629 1 1
635 1 1
643 1 1
648 1 1
651 1 1
652 1 1
653 1 1
655 1 1
656 1 1
679 1 1
684 1 1
687 1 1
689 1 1
694 1 1
698 1 1
702 1 1
706 0 1
710 0 1
723 1 1
728 0 1
735 1 1
745 1 1
765 3 3
769 1 1
771 1 1
772 1 1
774 1 1
776 1 1
778 1 1
779 1 1
782 1 1
785 1 1
791 1 1
792 1 1
794 1 1
799 1 1
800 1 1
801 1 1
803 1 1
809 1 1
814 1 1
815 1 1
817 1 1
819 1 1
825 1 1
826 1 1
828 1 1
834 1 1
835 1 1
847 1 1
848 1 1
MISSING_ELSE
920 1 1
923 1 1
992 1 1
994 1 1
1029 1 1
1034 1 1
1035 1 1
1037 1 1
1040 unreachable
1161 1 1
1162 1 1
1315 0 1
1316 1 1
1317 1 1
1327 1 1
1328 1 1
1334 1 1
1335 1 1
1336 1 1
1337 1 1
1340 1 1
1349 1 1
1391 1 1
1405 1 1
1412 1 1
1417 1 1
1423 1 1
1424 1 1
1425 1 1
1426 0 1
1427 1 1
1428 1 1
MISSING_ELSE
1432 1 1
1434 1 1
1446 1 1
1447 1 1
1448 1 1
1449 1 1
MISSING_ELSE
1452 1 1
1475 1 1
1476 1 1
1477 1 1
1479 1 1
MISSING_ELSE
1485 1 1
1486 1 1
1489 1 1
1496 1 1
1500 1 1
1502 6 6


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions908493.33
Logical908493.33
Non-Logical00
Event00

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T9

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T41,T42

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T41,T42

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------
-1--2-StatusTests
01CoveredT43,T44,T45
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----
-1--2--3-StatusTests
011CoveredT2,T3,T9
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T22,T23

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T13,T16

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T9

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T9,T16

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T9

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------
-1-StatusTests
0CoveredT13,T38,T24
1CoveredT1,T2,T3

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT27,T46,T37
0010Not Covered
0100CoveredT1,T21,T27
1000CoveredT16,T24,T25

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010CoveredT10,T11,T12
0100Unreachable
1000CoveredT10,T11,T12

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001CoveredT10,T11,T12
000010Unreachable
000100CoveredT10,T11,T12
001000CoveredT10,T11,T12
010000CoveredT10,T11,T12
100000CoveredT10,T11,T12

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------
-1-StatusTests
0CoveredT2,T3,T9
1CoveredT1,T2,T3

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----
-1-StatusTests
0CoveredT3,T9,T16
1CoveredT1,T2,T3

 LINE       1029
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       1162
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T9

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------
-1--2-StatusTests
01CoveredT20,T47,T48
10CoveredT1,T2,T3
11CoveredT20,T47,T48

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------
-1--2-StatusTests
01CoveredT20,T47,T48
10CoveredT1,T2,T3
11CoveredT20,T47,T48

 LINE       1434
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010CoveredT10,T11,T12
00100CoveredT1,T4,T5
01000CoveredT10,T11,T12
10000Not Covered

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 64 64 100.00
Total Bits 4160 4160 100.00
Total Bits 0->1 2080 2080 100.00
Total Bits 1->0 2080 2080 100.00

Ports 64 64 100.00
Port Bits 4160 4160 100.00
Port Bits 0->1 2080 2080 100.00
Port Bits 1->0 2080 2080 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T17,T4 Yes T1,T2,T3 INPUT
rst_shadowed_ni Yes Yes T1,T17,T4 Yes T1,T2,T3 INPUT
clk_edn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_edn_ni Yes Yes T1,T17,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T14,T16 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T15,T17 Yes T2,T15,T17 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T49,T50,T51 Yes T49,T50,T51 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T20,T47,T48 Yes T20,T47,T48 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T20,T47 Yes T1,T20,T47 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T20,T47,T48 Yes T20,T47,T48 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T20,T47 Yes T1,T20,T47 OUTPUT
keymgr_key_i.key[1:0][255:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
keymgr_key_i.valid Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
app_i[0].last Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[0].strb[7:0] Yes Yes T9,T17,T26 Yes T9,T17,T26 INPUT
app_i[0].data[63:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[0].valid Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT
app_i[1].last Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[1].strb[7:0] Yes Yes T9,T17,T26 Yes T9,T17,T26 INPUT
app_i[1].data[63:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[1].valid Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT
app_i[2].last Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[2].strb[7:0] Yes Yes T9,T17,T26 Yes T9,T17,T26 INPUT
app_i[2].data[63:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 INPUT
app_i[2].valid Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT
app_o[0].error Yes Yes T1,T16,T21 Yes T1,T16,T21 OUTPUT
app_o[0].digest_share1[383:0] Excluded Excluded Excluded OUTPUT [UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[0].done Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[0].ready Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[1].error Yes Yes T16,T4,T24 Yes T16,T4,T24 OUTPUT
app_o[1].digest_share1[383:0] Excluded Excluded Excluded OUTPUT [UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[1].done Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[1].ready Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[2].error Yes Yes T16,T24,T25 Yes T16,T24,T25 OUTPUT
app_o[2].digest_share1[383:0] Excluded Excluded Excluded OUTPUT [UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0] Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[2].done Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
app_o[2].ready Yes Yes T3,T9,T16 Yes T3,T9,T16 OUTPUT
entropy_o.edn_req[0:0] Excluded Excluded Excluded OUTPUT [UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0] Excluded Excluded Excluded INPUT [UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0] Excluded Excluded Excluded INPUT [UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0] Excluded Excluded Excluded INPUT [UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0] Yes Yes T4,T5,T32 Yes T4,T5,T32 INPUT
intr_kmac_done_o Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
intr_fifo_empty_o Yes Yes T13,T38,T24 Yes T13,T38,T24 OUTPUT
intr_kmac_err_o Yes Yes T1,T16,T21 Yes T1,T16,T21 OUTPUT
en_masking_o Unreachable Unreachable Unreachable OUTPUT
idle_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

FSM Coverage for Instance : tb.dut
Summary for FSM :: kmac_st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 13 13 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: kmac_st
statesLine No.CoveredTests
KmacDigest 817 Covered T2,T3,T9
KmacIdle 785 Covered T1,T2,T3
KmacKeyBlock 792 Covered T1,T2,T3
KmacMsgFeed 782 Covered T1,T2,T3
KmacPrefix 779 Covered T1,T2,T3
KmacTerminalError 834 Covered T1,T4,T5


transitionsLine No.CoveredTests
KmacDigest->KmacIdle 826 Covered T2,T3,T9
KmacDigest->KmacTerminalError 848 Covered T5,T52,T53
KmacIdle->KmacMsgFeed 782 Covered T2,T3,T9
KmacIdle->KmacPrefix 779 Covered T1,T2,T3
KmacIdle->KmacTerminalError 848 Covered T10,T34,T11
KmacKeyBlock->KmacMsgFeed 801 Covered T1,T2,T3
KmacKeyBlock->KmacTerminalError 848 Covered T54,T55,T56
KmacMsgFeed->KmacDigest 817 Covered T2,T3,T9
KmacMsgFeed->KmacIdle 814 Covered T3,T9,T16
KmacMsgFeed->KmacTerminalError 848 Covered T1,T8,T32
KmacPrefix->KmacKeyBlock 792 Covered T1,T2,T3
KmacPrefix->KmacMsgFeed 792 Covered T3,T9,T16
KmacPrefix->KmacTerminalError 848 Covered T4,T7,T57



Branch Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
Branches 65 61 93.85
TERNARY 426 2 2 100.00
TERNARY 635 4 4 100.00
TERNARY 643 4 4 100.00
TERNARY 648 2 2 100.00
CASE 434 6 5 83.33
IF 488 3 3 100.00
IF 561 3 3 100.00
IF 651 2 2 100.00
CASE 689 6 4 66.67
IF 765 2 2 100.00
CASE 774 15 15 100.00
IF 847 2 2 100.00
TERNARY 1162 2 2 100.00
IF 1423 4 3 75.00
IF 1446 3 3 100.00
IF 1475 3 3 100.00
IF 1485 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 426 (cmd_update) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 635 (msgfifo_full) ? -2-: 635 (msgfifo_empty_negedge) ? -3-: 635 (msgfifo2kmac_process) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T3,T13,T16
0 1 - Covered T1,T2,T3
0 0 1 Covered T2,T3,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 643 (app_active) ? -2-: 643 ((sha3_fsm != StAbsorb)) ? -3-: 643 (msgfifo2kmac_process) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T3,T9,T16
0 1 - Covered T1,T2,T3
0 0 1 Covered T2,T3,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 648 (msgfifo_empty_gate) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T13,T38,T24


LineNo. Expression -1-: 434 case (kmac_cmd)

Branches:
-1-StatusTests
CmdStart Covered T1,T2,T3
CmdProcess Covered T2,T3,T9
CmdManualRun Covered T2,T3,T9
CmdDone Covered T2,T3,T9
CmdNone Covered T1,T2,T3
default Not Covered


LineNo. Expression -1-: 488 if ((!rst_ni)) -2-: 490 if (engine_stable)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 561 if ((!rst_ni)) -2-: 563 if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 651 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 689 case (1'b1)

Branches:
-1-StatusTests
app_err.valid Covered T1,T21,T27
errchecker_err.valid Covered T27,T46,T37
sha3_err.valid Covered T16,T24,T25
entropy_err.valid Not Covered
msgfifo_err.valid Not Covered
default Covered T1,T2,T3


LineNo. Expression -1-: 765 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 774 case (kmac_st) -2-: 776 if ((kmac_cmd == CmdStart)) -3-: 778 if ((CShake == app_sha3_mode)) -4-: 791 if (sha3_block_processed) -5-: 792 (app_kmac_en) ? -6-: 800 if (sha3_block_processed) -7-: 809 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done))) -8-: 815 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done))) -9-: 825 if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
KmacIdle 1 1 - - - - - - Covered T1,T2,T3
KmacIdle 1 0 - - - - - - Covered T2,T3,T9
KmacIdle 0 - - - - - - - Covered T1,T2,T3
KmacPrefix - - 1 1 - - - - Covered T1,T2,T3
KmacPrefix - - 1 0 - - - - Covered T3,T9,T16
KmacPrefix - - 0 - - - - - Covered T1,T2,T3
KmacKeyBlock - - - - 1 - - - Covered T1,T2,T3
KmacKeyBlock - - - - 0 - - - Covered T1,T2,T3
KmacMsgFeed - - - - - 1 - - Covered T3,T9,T16
KmacMsgFeed - - - - - 0 1 - Covered T2,T3,T9
KmacMsgFeed - - - - - 0 0 - Covered T1,T2,T3
KmacDigest - - - - - - - 1 Covered T2,T3,T9
KmacDigest - - - - - - - 0 Covered T2,T3,T9
KmacTerminalError - - - - - - - - Covered T1,T4,T5
default - - - - - - - - Covered T10,T11,T12


LineNo. Expression -1-: 847 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 1162 (reg_state_valid) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 1423 if ((!rst_ni)) -2-: 1425 if (alert_recov_operation) -3-: 1427 if (err_processed)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Covered T21,T22,T23
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1446 if ((!rst_ni)) -2-: 1448 if (alert_fatal)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1475 if ((!rst_ni)) -2-: 1477 if (alerts[1])

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1485 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 30 30 100.00 30 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 30 30 100.00 30 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 2147483647 2147483647 0 0
CmdSparse_M 2147483647 1264590 0 0
EnMaskingKnown_A 2147483647 2147483647 0 0
EntropyReadyLatched_A 2147483647 335127 0 0
EntrySizeRegSameToEntrySizePkg_A 1023 1023 0 0
ErrProcessedLatched_A 2147483647 497 0 0
FifoEmpty_A 2147483647 2147483647 0 0
FpvSecCmErrorCheckFsmCheck_A 2147483647 70 0 0
FpvSecCmKeccackFsmCheck_A 2147483647 70 0 0
FpvSecCmKeyIndexCountCheck_A 2147483647 70 0 0
FpvSecCmKmacAppFsmCheck_A 2147483647 70 0 0
FpvSecCmKmacCoreFsmCheck_A 2147483647 70 0 0
FpvSecCmKmacFsmCheck_A 2147483647 70 0 0
FpvSecCmRegWeOnehotCheck_A 2147483647 70 0 0
FpvSecCmRoundCountCheck_A 2147483647 70 0 0
FpvSecCmSHA3FsmCheck_A 2147483647 70 0 0
FpvSecCmSHA3padFsmCheck_A 2147483647 70 0 0
FpvSecCmSentMsgCountCheck_A 2147483647 70 0 0
KmacCmd_A 2147483647 2147483647 0 0
KmacDone_A 2147483647 2147483647 0 0
KmacErr_A 2147483647 2147483647 0 0
KmacStKnown_A 2147483647 2147483647 0 0
NumAlerts2_A 1023 1023 0 0
NumEntriesRegSameToNumEntriesPkg_A 1023 1023 0 0
PrefixRegSameToPrefixPkg_A 1023 1023 0 0
SecretKeyDivideBy32_A 1023 1023 0 0
Sha3AbsorbedPulse_A 2147483647 345653 0 0
TlOAReadyKnown_A 2147483647 2147483647 0 0
TlODValidKnown_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

CmdSparse_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1264590 0 0
T1 4064 2 0 0
T2 849000 477 0 0
T3 401280 965 0 0
T9 624338 780 0 0
T13 435786 728 0 0
T14 998584 945 0 0
T15 945675 786 0 0
T16 619382 491 0 0
T17 472943 227 0 0
T18 0 7905 0 0
T20 1393 0 0 0

EnMaskingKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

EntropyReadyLatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 335127 0 0
T1 4064 1 0 0
T2 849000 65 0 0
T3 401280 162 0 0
T9 624338 147 0 0
T13 435786 104 0 0
T14 998584 134 0 0
T15 945675 234 0 0
T16 619382 95 0 0
T17 472943 53 0 0
T18 0 2208 0 0
T20 1393 0 0 0

EntrySizeRegSameToEntrySizePkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0

ErrProcessedLatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 497 0 0
T21 23780 5 0 0
T22 0 8 0 0
T23 0 1 0 0
T26 657349 0 0 0
T27 625539 0 0 0
T35 0 5 0 0
T48 1446 0 0 0
T58 0 16 0 0
T59 0 4 0 0
T60 0 2 0 0
T61 0 17 0 0
T62 0 12 0 0
T63 0 5 0 0
T64 217067 0 0 0
T65 591479 0 0 0
T66 209542 0 0 0
T67 256714 0 0 0
T68 17024 0 0 0
T69 107438 0 0 0

FifoEmpty_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

FpvSecCmErrorCheckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmKeccackFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmKeyIndexCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmKmacAppFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmKmacCoreFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmKmacFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmRoundCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmSHA3FsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmSHA3padFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

FpvSecCmSentMsgCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70 0 0
T10 518443 20 0 0
T11 0 10 0 0
T12 0 10 0 0
T29 138381 0 0 0
T70 0 10 0 0
T71 0 20 0 0
T72 956690 0 0 0
T73 1125 0 0 0
T74 418605 0 0 0
T75 16599 0 0 0
T76 385124 0 0 0
T77 21186 0 0 0
T78 331117 0 0 0
T79 89711 0 0 0

KmacCmd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

KmacDone_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

KmacErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

KmacStKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

NumAlerts2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0

NumEntriesRegSameToNumEntriesPkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0

PrefixRegSameToPrefixPkg_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0

SecretKeyDivideBy32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T20 1 1 0 0

Sha3AbsorbedPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 345653 0 0
T2 849000 66 0 0
T3 401280 162 0 0
T9 624338 147 0 0
T13 435786 105 0 0
T14 998584 134 0 0
T15 945675 246 0 0
T16 619382 95 0 0
T17 472943 54 0 0
T18 431948 2265 0 0
T19 0 246 0 0
T20 1393 0 0 0

TlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

TlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4064 3938 0 0
T2 849000 848917 0 0
T3 401280 401215 0 0
T9 624338 624282 0 0
T13 435786 435709 0 0
T14 998584 998490 0 0
T15 945675 945598 0 0
T16 619382 619319 0 0
T17 472943 472496 0 0
T20 1393 1295 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%