Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	67260	0	0
entropy_period_rd_A	2147483647	1582	0	0
intr_enable_rd_A	2147483647	2236	0	0
prefix_0_rd_A	2147483647	1584	0	0
prefix_10_rd_A	2147483647	1608	0	0
prefix_1_rd_A	2147483647	1636	0	0
prefix_2_rd_A	2147483647	1674	0	0
prefix_3_rd_A	2147483647	1656	0	0
prefix_4_rd_A	2147483647	1663	0	0
prefix_5_rd_A	2147483647	1643	0	0
prefix_6_rd_A	2147483647	1749	0	0
prefix_7_rd_A	2147483647	1641	0	0
prefix_8_rd_A	2147483647	1541	0	0
prefix_9_rd_A	2147483647	1699	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67260	0	0
T49	190155	17393	0	0
T50	0	46426	0	0
T51	0	220	0	0
T110	0	1	0	0
T111	0	2	0	0
T118	0	13	0	0
T120	0	3	0	0
T121	0	1	0	0
T122	0	5	0	0
T123	0	1	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1582	0	0
T49	190155	77	0	0
T98	0	5	0	0
T111	0	67	0	0
T120	0	23	0	0
T122	0	6	0	0
T123	0	6	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	128	0	0
T144	0	25	0	0
T145	0	14	0	0
T146	0	44	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2236	0	0
T49	190155	53	0	0
T98	0	13	0	0
T111	0	83	0	0
T120	0	17	0	0
T122	0	22	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T144	0	34	0	0
T147	0	24	0	0
T148	0	3	0	0
T149	0	13	0	0
T150	0	2	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1584	0	0
T49	190155	39	0	0
T98	0	16	0	0
T111	0	48	0	0
T120	0	11	0	0
T122	0	3	0	0
T123	0	4	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	92	0	0
T144	0	10	0	0
T146	0	35	0	0
T151	0	10	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1608	0	0
T49	190155	32	0	0
T98	0	21	0	0
T111	0	43	0	0
T120	0	11	0	0
T122	0	6	0	0
T123	0	10	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	97	0	0
T144	0	2	0	0
T145	0	7	0	0
T146	0	36	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1636	0	0
T49	190155	52	0	0
T98	0	19	0	0
T111	0	33	0	0
T120	0	20	0	0
T122	0	16	0	0
T123	0	1	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	78	0	0
T144	0	5	0	0
T145	0	21	0	0
T146	0	36	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1674	0	0
T49	190155	80	0	0
T98	0	11	0	0
T111	0	20	0	0
T120	0	27	0	0
T122	0	6	0	0
T123	0	2	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	90	0	0
T144	0	31	0	0
T145	0	33	0	0
T146	0	38	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1656	0	0
T49	190155	68	0	0
T98	0	16	0	0
T111	0	30	0	0
T120	0	14	0	0
T123	0	7	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	73	0	0
T144	0	25	0	0
T145	0	2	0	0
T146	0	50	0	0
T152	0	12	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1663	0	0
T49	190155	76	0	0
T98	0	18	0	0
T111	0	36	0	0
T120	0	18	0	0
T122	0	15	0	0
T123	0	7	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	101	0	0
T144	0	7	0	0
T145	0	15	0	0
T146	0	4	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1643	0	0
T49	190155	86	0	0
T98	0	7	0	0
T111	0	44	0	0
T120	0	17	0	0
T122	0	4	0	0
T123	0	6	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	101	0	0
T144	0	42	0	0
T145	0	11	0	0
T146	0	5	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1749	0	0
T49	190155	60	0	0
T98	0	11	0	0
T111	0	21	0	0
T120	0	19	0	0
T122	0	10	0	0
T123	0	4	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	93	0	0
T144	0	25	0	0
T145	0	12	0	0
T146	0	36	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1641	0	0
T49	190155	54	0	0
T98	0	16	0	0
T111	0	45	0	0
T120	0	25	0	0
T122	0	20	0	0
T123	0	6	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	72	0	0
T144	0	10	0	0
T145	0	31	0	0
T146	0	35	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1541	0	0
T49	190155	55	0	0
T98	0	18	0	0
T111	0	38	0	0
T120	0	17	0	0
T122	0	8	0	0
T123	0	5	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	81	0	0
T144	0	25	0	0
T145	0	10	0	0
T146	0	34	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1699	0	0
T49	190155	42	0	0
T98	0	14	0	0
T111	0	48	0	0
T120	0	18	0	0
T122	0	3	0	0
T123	0	10	0	0
T124	483146	0	0	0
T125	131158	0	0	0
T126	226162	0	0	0
T127	366638	0	0	0
T128	901226	0	0	0
T129	909901	0	0	0
T130	141971	0	0	0
T131	2361	0	0	0
T132	496058	0	0	0
T133	0	62	0	0
T144	0	54	0	0
T145	0	15	0	0
T146	0	37	0	0