Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	74066	0	0
entropy_period_rd_A	2147483647	1671	0	0
intr_enable_rd_A	2147483647	2395	0	0
prefix_0_rd_A	2147483647	1498	0	0
prefix_10_rd_A	2147483647	1335	0	0
prefix_1_rd_A	2147483647	1446	0	0
prefix_2_rd_A	2147483647	1534	0	0
prefix_3_rd_A	2147483647	1496	0	0
prefix_4_rd_A	2147483647	1466	0	0
prefix_5_rd_A	2147483647	1599	0	0
prefix_6_rd_A	2147483647	1393	0	0
prefix_7_rd_A	2147483647	1415	0	0
prefix_8_rd_A	2147483647	1378	0	0
prefix_9_rd_A	2147483647	1458	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	74066	0	0
T18	474075	40682	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T49	0	29887	0	0
T50	0	209	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T105	0	2	0	0
T106	0	1	0	0
T108	0	205	0	0
T109	0	160	0	0
T113	0	25	0	0
T114	0	2	0	0
T115	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1671	0	0
T18	474075	39	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T94	0	59	0	0
T101	0	32	0	0
T107	0	52	0	0
T116	0	9	0	0
T126	0	15	0	0
T127	0	5	0	0
T128	0	13	0	0
T129	0	19	0	0
T130	0	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2395	0	0
T18	474075	72	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T94	0	81	0	0
T107	0	73	0	0
T116	0	6	0	0
T126	0	8	0	0
T127	0	13	0	0
T128	0	17	0	0
T129	0	68	0	0
T130	0	26	0	0
T131	0	20	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1498	0	0
T18	474075	70	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T90	0	3	0	0
T94	0	42	0	0
T107	0	31	0	0
T116	0	11	0	0
T126	0	10	0	0
T127	0	2	0	0
T128	0	10	0	0
T129	0	13	0	0
T130	0	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1335	0	0
T18	474075	36	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T94	0	66	0	0
T107	0	31	0	0
T109	0	1	0	0
T116	0	5	0	0
T126	0	5	0	0
T127	0	7	0	0
T128	0	10	0	0
T129	0	29	0	0
T130	0	14	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1446	0	0
T18	474075	81	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T90	0	11	0	0
T94	0	58	0	0
T107	0	26	0	0
T116	0	1	0	0
T126	0	8	0	0
T127	0	13	0	0
T128	0	5	0	0
T129	0	19	0	0
T130	0	14	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1534	0	0
T18	474075	56	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T90	0	4	0	0
T94	0	73	0	0
T107	0	40	0	0
T109	0	5	0	0
T116	0	19	0	0
T126	0	7	0	0
T127	0	15	0	0
T128	0	13	0	0
T129	0	27	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1496	0	0
T18	474075	61	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T90	0	9	0	0
T94	0	65	0	0
T107	0	19	0	0
T116	0	6	0	0
T126	0	7	0	0
T127	0	7	0	0
T128	0	4	0	0
T129	0	31	0	0
T130	0	41	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1466	0	0
T18	474075	55	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T90	0	2	0	0
T94	0	69	0	0
T107	0	40	0	0
T116	0	6	0	0
T126	0	1	0	0
T127	0	15	0	0
T128	0	8	0	0
T129	0	29	0	0
T130	0	15	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1599	0	0
T18	474075	59	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T90	0	2	0	0
T94	0	43	0	0
T107	0	38	0	0
T116	0	18	0	0
T126	0	7	0	0
T127	0	15	0	0
T128	0	2	0	0
T129	0	20	0	0
T130	0	28	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1393	0	0
T18	474075	45	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T90	0	4	0	0
T94	0	54	0	0
T107	0	43	0	0
T116	0	4	0	0
T126	0	7	0	0
T127	0	6	0	0
T128	0	12	0	0
T129	0	12	0	0
T130	0	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1415	0	0
T18	474075	43	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T90	0	6	0	0
T94	0	49	0	0
T107	0	26	0	0
T116	0	17	0	0
T126	0	5	0	0
T127	0	4	0	0
T128	0	16	0	0
T129	0	34	0	0
T130	0	20	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1378	0	0
T18	474075	37	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T90	0	1	0	0
T94	0	54	0	0
T107	0	28	0	0
T116	0	13	0	0
T126	0	14	0	0
T127	0	5	0	0
T128	0	13	0	0
T129	0	23	0	0
T130	0	10	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1458	0	0
T18	474075	52	0	0
T19	144764	0	0	0
T22	799086	0	0	0
T24	66530	0	0	0
T36	144158	0	0	0
T37	191911	0	0	0
T65	601806	0	0	0
T66	433831	0	0	0
T87	6784	0	0	0
T88	77635	0	0	0
T90	0	2	0	0
T94	0	58	0	0
T107	0	52	0	0
T116	0	13	0	0
T126	0	10	0	0
T127	0	4	0	0
T128	0	13	0	0
T129	0	19	0	0
T130	0	14	0	0