Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 168166909 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 137495139 1 T1 66742 T2 10 T3 1386



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 160197103 1 T1 75056 T2 1 T3 1063
values[0x0] 70000911 1 T1 17262 T2 12 T3 471
values[0x1] 75464034 1 T1 18644 T2 16 T3 503



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 131106407 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 174555641 1 T1 76936 T2 15 T3 1522



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2912377 1 T1 518 T3 13 T4 1165
valid_sources[0x01] 885144 1 T1 402 T3 6 T4 1117
valid_sources[0x02] 1345873 1 T1 408 T3 15 T4 1242
valid_sources[0x03] 889400 1 T1 475 T3 4 T4 1074
valid_sources[0x04] 918876 1 T1 420 T3 10 T4 1142
valid_sources[0x05] 885956 1 T1 490 T3 9 T4 1030
valid_sources[0x06] 891723 1 T1 400 T3 3 T4 1057
valid_sources[0x07] 887527 1 T1 441 T3 9 T4 1170
valid_sources[0x08] 910524 1 T1 420 T3 10 T4 990
valid_sources[0x09] 892591 1 T1 415 T3 3 T4 1150
valid_sources[0x0a] 887165 1 T1 474 T3 12 T4 1059
valid_sources[0x0b] 1041302 1 T1 467 T3 4 T4 1119
valid_sources[0x0c] 883024 1 T1 401 T3 16 T4 1195
valid_sources[0x0d] 2229668 1 T1 392 T3 11 T4 1068
valid_sources[0x0e] 1460680 1 T1 468 T3 9 T4 1026
valid_sources[0x0f] 891032 1 T1 426 T3 4 T4 1001
valid_sources[0x10] 905086 1 T1 471 T2 2 T3 7
valid_sources[0x11] 889981 1 T1 451 T3 12 T4 1092
valid_sources[0x12] 898432 1 T1 491 T2 3 T3 9
valid_sources[0x13] 1179953 1 T1 452 T3 7 T4 1079
valid_sources[0x14] 1347008 1 T1 453 T2 3 T3 10
valid_sources[0x15] 935303 1 T1 438 T3 7 T4 1068
valid_sources[0x16] 892142 1 T1 447 T3 6 T4 1066
valid_sources[0x17] 891147 1 T1 455 T4 1014 T14 8
valid_sources[0x18] 887185 1 T1 438 T3 6 T4 1087
valid_sources[0x19] 891193 1 T1 413 T3 18 T4 937
valid_sources[0x1a] 1756621 1 T1 407 T3 5 T4 1076
valid_sources[0x1b] 890673 1 T1 429 T3 8 T4 1109
valid_sources[0x1c] 906542 1 T1 368 T3 7 T4 1166
valid_sources[0x1d] 888647 1 T1 464 T3 7 T4 1199
valid_sources[0x1e] 1102898 1 T1 383 T3 9 T4 1108
valid_sources[0x1f] 1773131 1 T1 420 T3 15 T4 1156
valid_sources[0x20] 892000 1 T1 445 T3 11 T4 1186
valid_sources[0x21] 892073 1 T1 489 T3 9 T4 1104
valid_sources[0x22] 884849 1 T1 370 T3 4 T4 1007
valid_sources[0x23] 890263 1 T1 398 T3 8 T4 1055
valid_sources[0x24] 918094 1 T1 431 T3 10 T4 1168
valid_sources[0x25] 3330579 1 T1 414 T3 5 T4 1124
valid_sources[0x26] 887277 1 T1 417 T3 4 T4 1089
valid_sources[0x27] 1607721 1 T1 407 T3 6 T4 1128
valid_sources[0x28] 886009 1 T1 477 T3 9 T4 1141
valid_sources[0x29] 1161887 1 T1 417 T3 10 T4 1090
valid_sources[0x2a] 890719 1 T1 462 T3 8 T4 998
valid_sources[0x2b] 1784522 1 T1 409 T3 4 T4 1095
valid_sources[0x2c] 1129139 1 T1 409 T4 1174 T14 13
valid_sources[0x2d] 889696 1 T1 443 T3 6 T4 1103
valid_sources[0x2e] 1539440 1 T1 459 T3 11 T4 950
valid_sources[0x2f] 1793770 1 T1 359 T3 11 T4 1216
valid_sources[0x30] 908948 1 T1 459 T3 4 T4 1006
valid_sources[0x31] 892565 1 T1 426 T3 8 T4 1109
valid_sources[0x32] 892086 1 T1 493 T3 5 T4 1171
valid_sources[0x33] 1620187 1 T1 396 T3 4 T4 1101
valid_sources[0x34] 888889 1 T1 436 T3 12 T4 1186
valid_sources[0x35] 887042 1 T1 439 T3 2 T4 1009
valid_sources[0x36] 933575 1 T1 438 T3 14 T4 1095
valid_sources[0x37] 883031 1 T1 414 T2 3 T3 14
valid_sources[0x38] 889033 1 T1 390 T3 11 T4 1020
valid_sources[0x39] 889471 1 T1 456 T3 6 T4 1060
valid_sources[0x3a] 886548 1 T1 464 T3 3 T4 1266
valid_sources[0x3b] 2989013 1 T1 463 T3 14 T4 1018
valid_sources[0x3c] 1362258 1 T1 367 T3 7 T4 1157
valid_sources[0x3d] 1603819 1 T1 402 T3 11 T4 1063
valid_sources[0x3e] 891857 1 T1 388 T2 1 T3 9
valid_sources[0x3f] 892271 1 T1 459 T3 5 T4 1029
valid_sources[0x40] 890457 1 T1 481 T2 4 T3 11
valid_sources[0x41] 1044462 1 T1 424 T3 2 T4 990
valid_sources[0x42] 1756384 1 T1 462 T3 3 T4 1261
valid_sources[0x43] 890287 1 T1 396 T3 7 T4 1051
valid_sources[0x44] 936697 1 T1 446 T3 5 T4 1009
valid_sources[0x45] 3319279 1 T1 487 T3 4 T4 1132
valid_sources[0x46] 928865 1 T1 426 T3 14 T4 1128
valid_sources[0x47] 1658763 1 T1 403 T3 7 T4 1184
valid_sources[0x48] 1205060 1 T1 490 T3 11 T4 1123
valid_sources[0x49] 890098 1 T1 498 T3 13 T4 1078
valid_sources[0x4a] 1040651 1 T1 424 T3 12 T4 1042
valid_sources[0x4b] 988833 1 T1 432 T3 10 T4 1011
valid_sources[0x4c] 1406916 1 T1 473 T3 5 T4 1170
valid_sources[0x4d] 1559442 1 T1 417 T3 6 T4 1050
valid_sources[0x4e] 2194952 1 T1 467 T3 8 T4 1127
valid_sources[0x4f] 884203 1 T1 379 T4 1080 T14 2
valid_sources[0x50] 953733 1 T1 440 T3 13 T4 1142
valid_sources[0x51] 887215 1 T1 478 T3 9 T4 1098
valid_sources[0x52] 1067306 1 T1 457 T3 6 T4 1012
valid_sources[0x53] 884635 1 T1 440 T3 13 T4 1074
valid_sources[0x54] 1879279 1 T1 401 T3 6 T4 1198
valid_sources[0x55] 893733 1 T1 448 T3 10 T4 1032
valid_sources[0x56] 955454 1 T1 440 T3 8 T4 1032
valid_sources[0x57] 1575194 1 T1 388 T3 17 T4 1211
valid_sources[0x58] 898566 1 T1 445 T2 2 T3 4
valid_sources[0x59] 890274 1 T1 447 T3 17 T4 1008
valid_sources[0x5a] 892284 1 T1 443 T3 13 T4 1209
valid_sources[0x5b] 2931975 1 T1 387 T3 13 T4 1202
valid_sources[0x5c] 906156 1 T1 377 T3 5 T4 1189
valid_sources[0x5d] 890757 1 T1 451 T3 5 T4 1079
valid_sources[0x5e] 897317 1 T1 421 T3 9 T4 1050
valid_sources[0x5f] 889303 1 T1 474 T3 10 T4 1019
valid_sources[0x60] 891017 1 T1 398 T3 25 T4 993
valid_sources[0x61] 890992 1 T1 427 T3 10 T4 1104
valid_sources[0x62] 894850 1 T1 430 T3 18 T4 1094
valid_sources[0x63] 1351723 1 T1 512 T3 10 T4 995
valid_sources[0x64] 888973 1 T1 351 T3 5 T4 1127
valid_sources[0x65] 1570662 1 T1 476 T3 6 T4 1004
valid_sources[0x66] 1544293 1 T1 439 T3 9 T4 1004
valid_sources[0x67] 885002 1 T1 405 T3 15 T4 1077
valid_sources[0x68] 891353 1 T1 398 T3 5 T4 1215
valid_sources[0x69] 887988 1 T1 424 T3 10 T4 1029
valid_sources[0x6a] 893183 1 T1 413 T3 8 T4 1238
valid_sources[0x6b] 884429 1 T1 374 T3 4 T4 1015
valid_sources[0x6c] 1456275 1 T1 435 T3 5 T4 1144
valid_sources[0x6d] 956899 1 T1 471 T3 7 T4 1077
valid_sources[0x6e] 1396910 1 T1 351 T3 12 T4 1088
valid_sources[0x6f] 1208121 1 T1 493 T3 9 T4 1162
valid_sources[0x70] 1558933 1 T1 479 T3 5 T4 1089
valid_sources[0x71] 879276 1 T1 517 T2 2 T3 11
valid_sources[0x72] 888849 1 T1 462 T4 1103 T14 18
valid_sources[0x73] 893112 1 T1 436 T3 6 T4 1112
valid_sources[0x74] 1014436 1 T1 458 T3 3 T4 1156
valid_sources[0x75] 1550128 1 T1 401 T3 3 T4 1056
valid_sources[0x76] 1013344 1 T1 430 T3 9 T4 1195
valid_sources[0x77] 2917351 1 T1 380 T3 20 T4 1084
valid_sources[0x78] 1780786 1 T1 496 T2 1 T3 7
valid_sources[0x79] 903038 1 T1 440 T3 15 T4 1153
valid_sources[0x7a] 1075987 1 T1 400 T3 10 T4 1140
valid_sources[0x7b] 890739 1 T1 445 T3 13 T4 1010
valid_sources[0x7c] 2995635 1 T1 425 T3 15 T4 1021
valid_sources[0x7d] 893127 1 T1 456 T3 1 T4 1092
valid_sources[0x7e] 889202 1 T1 411 T3 5 T4 1019
valid_sources[0x7f] 882889 1 T1 498 T3 15 T4 1095
valid_sources[0x80] 886477 1 T1 482 T3 7 T4 1035



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 58977464 1 T1 46820 T2 1 T3 682
values[0x0] all_enables biggest_size 42086018 1 T1 10590 T2 5 T3 361
values[0x1] all_enables biggest_size 36431657 1 T1 9332 T2 4 T3 343

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%