Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

168673320

1

T1

44220

T2

19

T3

651

full_word

137526842

1

T1

66742

T2

10

T3

1386

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	306199882	1			T1	110962		T2	29		T3	2037
auto[TlIntgErrCmd]	84	1			T52	5		T118	4		T120	3
auto[TlIntgErrData]	96	1			T52	7		T118	7		T120	8
auto[TlIntgErrBoth]	100	1			T52	8		T118	9		T120	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160297891

1

T1

75056

T2

1

T3

1063

auto[1]

145902271

1

T1

35906

T2

28

T3

974

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	101312283	1			T1	28236		T3	381		T4	16251
auto[TlIntgErrNone]	partial	auto[1]	67360783	1			T1	15984		T2	19		T3	270
auto[TlIntgErrNone]	full_word	auto[0]	58985486	1			T1	46820		T2	1		T3	682
auto[TlIntgErrNone]	full_word	auto[1]	78541330	1			T1	19922		T2	9		T3	704
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T52	3		T138	2		T186	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T52	2		T118	4		T120	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T188	1		T189	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T138	2		T186	1		T189	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T118	3		T120	1		T138	3
auto[TlIntgErrData]	partial	auto[1]	38	1			T52	5		T118	2		T120	7
auto[TlIntgErrData]	full_word	auto[0]	5	1			T52	2		T190	1		T185	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T118	2		T187	1		T189	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T52	1		T118	5		T120	5
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T52	7		T118	4		T120	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T120	1		T138	1		T189	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T120	1		T138	1		T184	1