Module Definition
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Module Instance : tb.dut.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_kmac_core.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.46 98.55 92.86 100.00 92.00 88.89 u_kmac_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_sha3.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.96 97.56 88.89 100.00 93.33 100.00 u_sha3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_sha3.u_pad.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 99.38 88.37 100.00 95.70 100.00 u_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_sha3.u_keccak.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.06 65.98 100.00 40.00 79.31 100.00 u_keccak


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.49 90.99 84.93 40.00 86.52 100.00 u_app_intf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_errchk.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.60 96.83 96.67 73.33 96.15 100.00 u_errchk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00

Line Coverage for Module : prim_sparse_fsm_flop
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Module : prim_sparse_fsm_flop
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 6678 6678 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6678 6678 0 0
T1 7 7 0 0
T2 7 7 0 0
T3 7 7 0 0
T4 7 7 0 0
T14 7 7 0 0
T15 7 7 0 0
T16 7 7 0 0
T17 7 7 0 0
T18 7 7 0 0
T19 7 7 0 0

Line Coverage for Instance : tb.dut.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 954 954 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 954 954 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_kmac_core.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_kmac_core.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 954 954 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 954 954 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_sha3.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 954 954 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 954 954 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_pad.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_sha3.u_pad.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 954 954 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 954 954 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 954 954 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 954 954 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_app_intf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_app_intf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 954 954 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 954 954 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_errchk.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_errchk.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 954 954 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 954 954 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0