Unified Coverage Report :: Module :: keccak_2share

Module : keccak_2share

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.25	100.00	75.00			50.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p	81.25	100.00	75.00			50.00	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.25	100.00	75.00			50.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.25	100.00	75.00			50.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.06	65.98	100.00		40.00	79.31	100.00	u_keccak

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
TOTAL		73	73	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	0	0
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
ROUTINE	363	0	0
ROUTINE	363	5	5	100.00
ROUTINE	376	0	0
ROUTINE	376	5	5	100.00
ROUTINE	409	0	0
ROUTINE	409	10	10	100.00
ROUTINE	478	0	0
ROUTINE	478	4	4	100.00
ROUTINE	492	0	0
ROUTINE	492	3	3	100.00
ROUTINE	547	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
86	1	1
87	1	1
88	1	1
89	1	1
91		unreachable
98	1	1
99	1	1
114	1	1
115	1	1
116	1	1
125	1	1
129	1	1
136	1	1
143	1	1
296	1	1
297	1	1
314	1	1
315	1	1
322	1	1
324	24	24
344	1	1
363	1	1
364	1	1
365	1	1
366	1	1
370	1	1
376	1	1
377	1	1
378	1	1
379	1	1
383	1	1
409	1	1
410	1	1
412	1	1
413	1	1
415	1	1
416	1	1
419	1	1
420	1	1
421	1	1
424	1	1
478	1	1
479	1	1
480	1	1
483	1	1
492	1	1
493	1	1
495	1	1
547	1	1
548	1	1
550	1	1

---

Cond Coverage for Module : keccak_2share

	Total	Covered	Percent
Conditions	8	6	75.00
Logical	8	6	75.00
Non-Logical	0	0
Event	0	0

 LINE       415
 EXPRESSION ((z == 0) ? ((W - 1)) : ((z - 1)))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       415
 SUB-EXPRESSION (z == 0)
                ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       416
 EXPRESSION (c[ThetaIndexX1[x]][z] ^ c[ThetaIndexX2[x]][index_z])
             ----------1----------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

---

Branch Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
Branches		2	1	50.00
TERNARY	415	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	415	((z == 0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keccak_2share

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidL_A	954	954	0	0
ValidRound_A	954	954	0	0
ValidW_A	954	954	0	0
ValidWidth_A	954	954	0	0

ValidL_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ValidRound_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ValidW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0