Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1494714694	117222	0	0
entropy_period_rd_A	1494714694	1862	0	0
intr_enable_rd_A	1494714694	2424	0	0
prefix_0_rd_A	1494714694	1823	0	0
prefix_10_rd_A	1494714694	1751	0	0
prefix_1_rd_A	1494714694	1894	0	0
prefix_2_rd_A	1494714694	1865	0	0
prefix_3_rd_A	1494714694	1812	0	0
prefix_4_rd_A	1494714694	1878	0	0
prefix_5_rd_A	1494714694	1657	0	0
prefix_6_rd_A	1494714694	1800	0	0
prefix_7_rd_A	1494714694	1704	0	0
prefix_8_rd_A	1494714694	2010	0	0
prefix_9_rd_A	1494714694	1760	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	117222	0	0
T50	792024	113981	0	0
T51	0	3	0	0
T52	0	2	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	3	0	0
T121	0	129	0	0
T122	0	248	0	0
T134	0	6	0	0
T138	0	2	0	0
T139	1407	0	0	0
T140	179538	0	0	0
T141	23535	0	0	0
T142	52416	0	0	0
T143	6375	0	0	0
T144	716	0	0	0
T145	174432	0	0	0
T146	938793	0	0	0
T147	4835	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	1862	0	0
T51	4635	10	0	0
T101	10987	60	0	0
T103	8983	35	0	0
T110	5091	2	0	0
T120	23413	140	0	0
T128	2936	6	0	0
T134	5202	9	0	0
T159	10059	25	0	0
T160	1949	10	0	0
T161	1958	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	2424	0	0
T51	4635	12	0	0
T101	10987	113	0	0
T103	8983	54	0	0
T120	23413	142	0	0
T128	2936	10	0	0
T159	10059	24	0	0
T160	1949	7	0	0
T161	1958	8	0	0
T162	1082	6	0	0
T163	1323	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	1823	0	0
T51	4635	16	0	0
T101	10987	49	0	0
T103	8983	18	0	0
T110	5091	9	0	0
T120	23413	72	0	0
T128	2936	6	0	0
T134	5202	2	0	0
T159	10059	32	0	0
T160	1949	2	0	0
T161	1958	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	1751	0	0
T51	4635	13	0	0
T101	10987	76	0	0
T103	8983	31	0	0
T110	5091	8	0	0
T120	23413	71	0	0
T128	2936	9	0	0
T159	10059	8	0	0
T160	1949	3	0	0
T161	1958	4	0	0
T164	6662	17	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	1894	0	0
T51	4635	7	0	0
T101	10987	36	0	0
T103	8983	30	0	0
T110	5091	30	0	0
T120	23413	118	0	0
T128	2936	9	0	0
T159	10059	24	0	0
T160	1949	1	0	0
T161	1958	2	0	0
T165	1445	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	1865	0	0
T51	4635	2	0	0
T101	10987	63	0	0
T103	8983	24	0	0
T110	5091	6	0	0
T120	23413	80	0	0
T128	2936	7	0	0
T134	5202	2	0	0
T159	10059	32	0	0
T160	1949	3	0	0
T161	1958	9	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	1812	0	0
T51	4635	15	0	0
T101	10987	51	0	0
T103	8983	28	0	0
T110	5091	18	0	0
T120	23413	94	0	0
T128	2936	5	0	0
T134	5202	1	0	0
T159	10059	27	0	0
T160	1949	9	0	0
T161	1958	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	1878	0	0
T51	4635	12	0	0
T101	10987	61	0	0
T103	8983	24	0	0
T110	5091	10	0	0
T120	23413	79	0	0
T128	2936	9	0	0
T134	5202	4	0	0
T159	10059	34	0	0
T160	1949	2	0	0
T165	1445	10	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	1657	0	0
T51	4635	10	0	0
T101	10987	52	0	0
T103	8983	27	0	0
T110	5091	10	0	0
T120	23413	59	0	0
T128	2936	10	0	0
T134	5202	7	0	0
T159	10059	25	0	0
T160	1949	6	0	0
T161	1958	3	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	1800	0	0
T51	4635	4	0	0
T101	10987	45	0	0
T103	8983	50	0	0
T110	5091	16	0	0
T120	23413	96	0	0
T128	2936	4	0	0
T134	5202	2	0	0
T159	10059	29	0	0
T160	1949	3	0	0
T165	1445	5	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	1704	0	0
T51	4635	11	0	0
T101	10987	68	0	0
T103	8983	25	0	0
T110	5091	2	0	0
T120	23413	71	0	0
T128	2936	14	0	0
T159	10059	9	0	0
T160	1949	7	0	0
T161	1958	9	0	0
T165	1445	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	2010	0	0
T51	4635	4	0	0
T101	10987	65	0	0
T103	8983	25	0	0
T110	5091	12	0	0
T120	23413	113	0	0
T128	2936	17	0	0
T134	5202	3	0	0
T159	10059	11	0	0
T160	1949	1	0	0
T161	1958	1	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494714694	1760	0	0
T51	4635	6	0	0
T101	10987	43	0	0
T103	8983	10	0	0
T110	5091	1	0	0
T120	23413	81	0	0
T128	2936	7	0	0
T134	5202	16	0	0
T159	10059	21	0	0
T160	1949	2	0	0
T161	1958	2	0	0