Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1436183230	182896	0	0
entropy_period_rd_A	1436183230	2083	0	0
intr_enable_rd_A	1436183230	3016	0	0
prefix_0_rd_A	1436183230	2319	0	0
prefix_10_rd_A	1436183230	2408	0	0
prefix_1_rd_A	1436183230	2295	0	0
prefix_2_rd_A	1436183230	2351	0	0
prefix_3_rd_A	1436183230	2399	0	0
prefix_4_rd_A	1436183230	2280	0	0
prefix_5_rd_A	1436183230	2232	0	0
prefix_6_rd_A	1436183230	2270	0	0
prefix_7_rd_A	1436183230	2170	0	0
prefix_8_rd_A	1436183230	2363	0	0
prefix_9_rd_A	1436183230	2303	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	182896	0	0
T20	99688	0	0	0
T24	575910	73069	0	0
T25	846688	0	0	0
T30	374091	0	0	0
T38	381094	0	0	0
T48	0	30840	0	0
T49	0	76070	0	0
T65	471808	0	0	0
T66	62148	0	0	0
T86	318891	0	0	0
T87	466658	0	0	0
T88	707935	0	0	0
T115	0	4	0	0
T116	0	4	0	0
T117	0	123	0	0
T118	0	54	0	0
T119	0	3	0	0
T120	0	2	0	0
T121	0	45	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2083	0	0
T93	3141	5	0	0
T95	12694	86	0	0
T106	2408	8	0	0
T114	3047	10	0	0
T116	7180	18	0	0
T130	1748	1	0	0
T131	4825	11	0	0
T132	10710	26	0	0
T133	5182	12	0	0
T134	6193	19	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	3016	0	0
T93	3141	8	0	0
T95	12694	98	0	0
T106	2408	10	0	0
T114	3047	7	0	0
T116	7180	7	0	0
T130	1748	20	0	0
T131	4825	21	0	0
T132	10710	39	0	0
T133	5182	9	0	0
T135	911	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2319	0	0
T93	3141	7	0	0
T95	12694	58	0	0
T100	5457	34	0	0
T114	3047	9	0	0
T116	7180	8	0	0
T130	1748	7	0	0
T131	4825	5	0	0
T132	10710	74	0	0
T133	5182	15	0	0
T134	6193	43	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2408	0	0
T93	3141	11	0	0
T95	12694	53	0	0
T100	5457	25	0	0
T106	2408	9	0	0
T114	3047	9	0	0
T116	7180	7	0	0
T131	4825	6	0	0
T132	10710	21	0	0
T133	5182	53	0	0
T134	6193	9	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2295	0	0
T93	3141	5	0	0
T95	12694	62	0	0
T100	5457	18	0	0
T106	2408	11	0	0
T114	3047	9	0	0
T116	7180	12	0	0
T131	4825	6	0	0
T132	10710	14	0	0
T133	5182	10	0	0
T134	6193	25	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2351	0	0
T93	3141	10	0	0
T95	12694	34	0	0
T100	5457	12	0	0
T106	2408	1	0	0
T114	3047	7	0	0
T116	7180	4	0	0
T131	4825	19	0	0
T132	10710	32	0	0
T133	5182	53	0	0
T134	6193	28	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2399	0	0
T93	3141	1	0	0
T95	12694	48	0	0
T97	4722	10	0	0
T100	5457	25	0	0
T116	7180	6	0	0
T130	1748	4	0	0
T132	10710	5	0	0
T133	5182	7	0	0
T134	6193	25	0	0
T136	4622	10	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2280	0	0
T93	3141	2	0	0
T95	12694	45	0	0
T100	5457	8	0	0
T106	2408	3	0	0
T114	3047	5	0	0
T116	7180	12	0	0
T130	1748	3	0	0
T132	10710	50	0	0
T133	5182	10	0	0
T134	6193	38	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2232	0	0
T93	3141	11	0	0
T95	12694	44	0	0
T100	5457	18	0	0
T106	2408	6	0	0
T114	3047	1	0	0
T116	7180	9	0	0
T130	1748	8	0	0
T132	10710	56	0	0
T133	5182	8	0	0
T134	6193	60	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2270	0	0
T93	3141	12	0	0
T95	12694	53	0	0
T97	4722	10	0	0
T100	5457	22	0	0
T106	2408	11	0	0
T116	7180	8	0	0
T130	1748	8	0	0
T132	10710	12	0	0
T133	5182	36	0	0
T134	6193	39	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2170	0	0
T93	3141	7	0	0
T95	12694	58	0	0
T100	5457	17	0	0
T106	2408	12	0	0
T116	7180	14	0	0
T130	1748	9	0	0
T131	4825	23	0	0
T132	10710	61	0	0
T133	5182	24	0	0
T134	6193	35	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2363	0	0
T93	3141	7	0	0
T95	12694	51	0	0
T100	5457	11	0	0
T114	3047	9	0	0
T116	7180	17	0	0
T130	1748	2	0	0
T131	4825	11	0	0
T132	10710	68	0	0
T133	5182	16	0	0
T134	6193	33	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436183230	2303	0	0
T93	3141	5	0	0
T95	12694	52	0	0
T97	4722	11	0	0
T100	5457	12	0	0
T106	2408	16	0	0
T116	7180	15	0	0
T131	4825	1	0	0
T132	10710	21	0	0
T133	5182	47	0	0
T134	6193	18	0	0