Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.19	96.27	93.33	63.67	100.00	93.85	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	97.24	96.27	93.33	100.00	100.00	93.85	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.24	96.27	93.33	100.00	100.00	93.85	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.34	95.89	92.27	100.00	66.94	94.11	98.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	86.94	90.00	77.78			80.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	81.00	91.14	87.72		37.78	88.35	100.00
u_errchk	92.70	97.22	96.67		73.33	96.30	100.00
u_kmac_core	93.72	98.75	92.86	100.00	87.50	92.31	90.91
u_msgfifo	97.75	100.00	95.00		100.00	93.75	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.98	99.19	96.97	100.00		98.72	100.00
u_sha3	92.16	91.91	88.51	100.00	80.56	92.00	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.88	89.88	81.09			88.54	100.00
u_tlul_adapter_msgfifo	80.11	87.12	74.69			77.38	81.25

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	346	0	0
ALWAYS	346	2	2	100.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
ALWAYS	429	9	9	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
ALWAYS	488	6	6	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	537	0	0
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
ALWAYS	561	5	5	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
ALWAYS	651	5	5	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	687	7	5	71.43
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	728	1	0	0.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
ALWAYS	765	3	3	100.00
ALWAYS	769	28	28	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	923	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1034	1	1	100.00
CONT_ASSIGN	1035	1	1	100.00
CONT_ASSIGN	1037	1	1	100.00
CONT_ASSIGN	1040	0	0
ALWAYS	1161	0	0
ALWAYS	1161	2	2	100.00
CONT_ASSIGN	1315	1	0	0.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1405	1	1	100.00
CONT_ASSIGN	1412	1	1	100.00
CONT_ASSIGN	1417	1	1	100.00
ALWAYS	1423	6	5	83.33
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
ALWAYS	1446	4	4	100.00
CONT_ASSIGN	1452	1	1	100.00
ALWAYS	1475	4	4	100.00
ALWAYS	1485	3	3	100.00
CONT_ASSIGN	1496	1	1	100.00
CONT_ASSIGN	1500	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	1	1
347	1	1
352	0	1
421	1	1
422	1	1
426	1	1
429	1	1
430	1	1
431	1	1
432	1	1
434	1	1
436	1	1
440	1	1
444	1	1
448	1	1
464	1	1
465	1	1
466	1	1
469	1	1
473	1	1
474	1	1
478	1	1
481	1	1
488	1	1
489	1	1
490	1	1
491	1	1
492	1	1
493	1	1
			MISSING_ELSE
			MISSING_ELSE
513	1	1
518	1	1
525	1	1
528	1	1
529	1	1
530	1	1
532	1	1
533	1	1
535	1	1
537		unreachable
539	1	1
543	1	1
545	1	1
546	1	1
549	1	1
550	1	1
553	1	1
561	1	1
562	1	1
563	1	1
564	1	1
566	1	1
571	1	1
577	1	1
578	1	1
579	1	1
587	1	1
629	1	1
635	1	1
643	1	1
648	1	1
651	1	1
652	1	1
653	1	1
655	1	1
656	1	1
679	1	1
684	1	1
687	1	1
689	1	1
694	1	1
698	1	1
702	1	1
706	0	1
710	0	1
723	1	1
728	0	1
735	1	1
745	1	1
765	3	3
769	1	1
771	1	1
772	1	1
774	1	1
776	1	1
778	1	1
779	1	1
782	1	1
785	1	1
791	1	1
792	1	1
794	1	1
799	1	1
800	1	1
801	1	1
803	1	1
809	1	1
814	1	1
815	1	1
817	1	1
819	1	1
825	1	1
826	1	1
828	1	1
834	1	1
835	1	1
847	1	1
848	1	1
			MISSING_ELSE
920	1	1
923	1	1
992	1	1
994	1	1
1029	1	1
1034	1	1
1035	1	1
1037	1	1
1040		unreachable
1161	1	1
1162	1	1
1315	0	1
1316	1	1
1317	1	1
1327	1	1
1328	1	1
1334	1	1
1335	1	1
1336	1	1
1337	1	1
1340	1	1
1349	1	1
1391	1	1
1405	1	1
1412	1	1
1417	1	1
1423	1	1
1424	1	1
1425	1	1
1426	0	1
1427	1	1
1428	1	1
			MISSING_ELSE
1432	1	1
1434	1	1
1446	1	1
1447	1	1
1448	1	1
1449	1	1
			MISSING_ELSE
1452	1	1
1475	1	1
1476	1	1
1477	1	1
1479	1	1
			MISSING_ELSE
1485	1	1
1486	1	1
1489	1	1
1496	1	1
1500	1	1
1502	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T24,T38

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T24,T38

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T43,T44
1	0	Covered	T1,T3,T13
1	1	Covered	T1,T3,T13

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T21,T22

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T1,T3,T13

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T25,T39,T40
1	Covered	T1,T2,T3

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T3,T14,T18
0	0	1	0	Not Covered
0	1	0	0	Covered	T3,T18,T4
1	0	0	0	Covered	T23,T24,T25

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T10,T11,T12

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T10,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T10,T11,T12
0	0	1	0	0	0	Covered	T10,T11,T12
0	1	0	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	0	Covered	T10,T11,T12

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T3,T13,T14
1	Covered	T1,T2,T3

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T1,T2,T3

 LINE       1029
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T13
1	0	Not Covered
1	1	Covered	T1,T3,T13

 LINE       1162
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T13

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T45,T46,T47

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T45,T46,T47

 LINE       1434
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T10,T11,T12
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	64	90.14
Total Bits	6534	4160	63.67
Total Bits 0->1	3267	2080	63.67
Total Bits 1->0	3267	2080	63.67

Ports	71	64	90.14
Port Bits	6534	4160	63.67
Port Bits 0->1	3267	2080	63.67
Port Bits 1->0	3267	2080	63.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T24,T25	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T4,T24,T25	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T4,T24,T25	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T13	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T16,T17	Yes	T3,T16,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T24,T48,T49	Yes	T24,T48,T49	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
keymgr_key_i.key[1:0][255:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
keymgr_key_i.valid	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
app_i[0].last	Yes	Yes	T2,T3,T18	Yes	T2,T3,T14	INPUT
app_i[0].strb[7:0]	Yes	Yes	T28,T26,T24	Yes	T28,T26,T24	INPUT
app_i[0].data[63:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
app_i[0].valid	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
app_i[1].last	Yes	Yes	T2,T3,T28	Yes	T2,T3,T18	INPUT
app_i[1].strb[7:0]	Yes	Yes	T28,T26,T24	Yes	T28,T26,T24	INPUT
app_i[1].data[63:0]	Yes	Yes	T2,T3,T18	Yes	T2,T3,T18	INPUT
app_i[1].valid	Yes	Yes	T2,T3,T18	Yes	T2,T3,T18	INPUT
app_i[2].last	Yes	Yes	T2,T3,T28	Yes	T2,T3,T14	INPUT
app_i[2].strb[7:0]	Yes	Yes	T28,T26,T24	Yes	T28,T26,T24	INPUT
app_i[2].data[63:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
app_i[2].valid	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
app_o[0].error	Yes	Yes	T4,T23,T24	Yes	T4,T23,T24	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
app_o[0].done	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
app_o[0].ready	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
app_o[1].error	Yes	Yes	T23,T24,T50	Yes	T23,T24,T50	OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T2,T3,T28	Yes	T2,T3,T28	OUTPUT
app_o[1].done	Yes	Yes	T2,T3,T18	Yes	T2,T3,T18	OUTPUT
app_o[1].ready	Yes	Yes	T2,T3,T18	Yes	T2,T3,T18	OUTPUT
app_o[2].error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T2,T14,T18	Yes	T2,T14,T18	OUTPUT
app_o[2].done	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
app_o[2].ready	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
intr_kmac_done_o	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	OUTPUT
intr_fifo_empty_o	Yes	Yes	T25,T39,T40	Yes	T25,T39,T40	OUTPUT
intr_kmac_err_o	Yes	Yes	T3,T14,T18	Yes	T3,T14,T18	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	817	Covered	T1,T3,T13
KmacIdle	785	Covered	T1,T2,T3
KmacKeyBlock	792	Covered	T1,T2,T3
KmacMsgFeed	782	Covered	T1,T2,T3
KmacPrefix	779	Covered	T1,T2,T3
KmacTerminalError	834	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	826	Covered	T1,T3,T13
KmacDigest->KmacTerminalError	848	Covered	T51,T52,T53
KmacIdle->KmacMsgFeed	782	Covered	T3,T13,T14
KmacIdle->KmacPrefix	779	Covered	T1,T2,T3
KmacIdle->KmacTerminalError	848	Covered	T10,T11,T35
KmacKeyBlock->KmacMsgFeed	801	Covered	T1,T2,T3
KmacKeyBlock->KmacTerminalError	848	Covered	T54,T55,T56
KmacMsgFeed->KmacDigest	817	Covered	T1,T3,T13
KmacMsgFeed->KmacIdle	814	Covered	T2,T3,T14
KmacMsgFeed->KmacTerminalError	848	Covered	T4,T5,T6
KmacPrefix->KmacKeyBlock	792	Covered	T1,T2,T3
KmacPrefix->KmacMsgFeed	792	Covered	T2,T3,T14
KmacPrefix->KmacTerminalError	848	Covered	T57,T7,T8

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	426	2	2	100.00
TERNARY	635	4	4	100.00
TERNARY	643	4	4	100.00
TERNARY	648	2	2	100.00
CASE	434	6	5	83.33
IF	488	3	3	100.00
IF	561	3	3	100.00
IF	651	2	2	100.00
CASE	689	6	4	66.67
IF	765	2	2	100.00
CASE	774	15	15	100.00
IF	847	2	2	100.00
TERNARY	1162	2	2	100.00
IF	1423	4	3	75.00
IF	1446	3	3	100.00
IF	1475	3	3	100.00
IF	1485	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	635	(msgfifo_full) ? 
-2-:	635	(msgfifo_empty_negedge) ? 
-3-:	635	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T14
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	643	(app_active) ? 
-2-:	643	((sha3_fsm != StAbsorb)) ? 
-3-:	643	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T14
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T13
0	0	0	Covered	T1,T3,T13

	LineNo.	Expression
-1-:	648	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T25,T39,T40

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T3,T14,T18
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	if ((!rst_ni))
-2-:	563	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	651	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	689	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T3,T18,T4
errchecker_err.valid	Covered	T3,T14,T18
sha3_err.valid	Covered	T23,T24,T25
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	765	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	774	case (kmac_st)
-2-:	776	if ((kmac_cmd == CmdStart))
-3-:	778	if ((CShake == app_sha3_mode))
-4-:	791	if (sha3_block_processed)
-5-:	792	(app_kmac_en) ? 
-6-:	800	if (sha3_block_processed)
-7-:	809	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	815	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	825	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	1	0	-	-	-	-	-	-	Covered	T3,T13,T14
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T2,T3,T14
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T2,T3,T14
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T3,T13
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T3,T13
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T3,T13
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	847	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1162	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1423	if ((!rst_ni))
-2-:	1425	if (alert_recov_operation)
-3-:	1427	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1446	if ((!rst_ni))
-2-:	1448	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1475	if ((!rst_ni))
-2-:	1477	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1485	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	1434716550	1434564199	0	0
CmdSparse_M	1434716550	745572	0	0
EnMaskingKnown_A	1434716550	1434564199	0	0
EntropyReadyLatched_A	1434716550	187597	0	0
EntrySizeRegSameToEntrySizePkg_A	948	948	0	0
ErrProcessedLatched_A	1434716550	438	0	0
FifoEmpty_A	1434716550	1434564199	0	0
FpvSecCmErrorCheckFsmCheck_A	1434716550	70	0	0
FpvSecCmKeccackFsmCheck_A	1434716550	70	0	0
FpvSecCmKeyIndexCountCheck_A	1434716550	70	0	0
FpvSecCmKmacAppFsmCheck_A	1434716550	70	0	0
FpvSecCmKmacCoreFsmCheck_A	1434716550	70	0	0
FpvSecCmKmacFsmCheck_A	1434716550	70	0	0
FpvSecCmRegWeOnehotCheck_A	1434716550	70	0	0
FpvSecCmRoundCountCheck_A	1434716550	70	0	0
FpvSecCmSHA3FsmCheck_A	1434716550	70	0	0
FpvSecCmSHA3padFsmCheck_A	1434716550	70	0	0
FpvSecCmSentMsgCountCheck_A	1434716550	70	0	0
KmacCmd_A	1434716550	1434564199	0	0
KmacDone_A	1434716550	1434564199	0	0
KmacErr_A	1434716550	1434564199	0	0
KmacStKnown_A	1434716550	1434564199	0	0
NumAlerts2_A	948	948	0	0
NumEntriesRegSameToNumEntriesPkg_A	948	948	0	0
PrefixRegSameToPrefixPkg_A	948	948	0	0
SecretKeyDivideBy32_A	948	948	0	0
Sha3AbsorbedPulse_A	1434716550	193432	0	0
TlOAReadyKnown_A	1434716550	1434564199	0	0
TlODValidKnown_A	1434716550	1434564199	0	0
u_state_regs_A	1434716550	1434564199	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	745572	0	0
T1	16374	28	0	0
T2	137627	11	0	0
T3	382357	1173	0	0
T13	612625	1201	0	0
T14	135914	400	0	0
T15	591860	1187	0	0
T16	21501	27	0	0
T17	17269	28	0	0
T18	157175	1091	0	0
T19	464581	990	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	187597	0	0
T1	16374	9	0	0
T2	137627	0	0	0
T3	382357	166	0	0
T13	612625	360	0	0
T14	135914	55	0	0
T15	591860	367	0	0
T16	21501	9	0	0
T17	17269	8	0	0
T18	157175	149	0	0
T19	464581	294	0	0
T37	0	301	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	438	0	0
T5	3587	0	0	0
T6	33709	0	0	0
T20	99688	16	0	0
T21	0	4	0	0
T22	0	8	0	0
T30	374091	0	0	0
T38	381094	0	0	0
T58	0	3	0	0
T59	0	7	0	0
T60	0	4	0	0
T61	0	6	0	0
T62	0	15	0	0
T63	0	5	0	0
T64	0	4	0	0
T65	471808	0	0	0
T66	62148	0	0	0
T67	16905	0	0	0
T68	72521	0	0	0
T69	253498	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	193432	0	0
T1	16374	9	0	0
T2	137627	32	0	0
T3	382357	152	0	0
T13	612625	374	0	0
T14	135914	56	0	0
T15	591860	374	0	0
T16	21501	9	0	0
T17	17269	9	0	0
T18	157175	144	0	0
T19	464581	310	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	346	0	0
ALWAYS	346	2	2	100.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
ALWAYS	429	9	9	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
ALWAYS	488	6	6	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	537	0	0
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
ALWAYS	561	5	5	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
ALWAYS	651	5	5	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	687	7	5	71.43
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	728	1	0	0.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
ALWAYS	765	3	3	100.00
ALWAYS	769	28	28	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	923	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1034	1	1	100.00
CONT_ASSIGN	1035	1	1	100.00
CONT_ASSIGN	1037	1	1	100.00
CONT_ASSIGN	1040	0	0
ALWAYS	1161	0	0
ALWAYS	1161	2	2	100.00
CONT_ASSIGN	1315	1	0	0.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1405	1	1	100.00
CONT_ASSIGN	1412	1	1	100.00
CONT_ASSIGN	1417	1	1	100.00
ALWAYS	1423	6	5	83.33
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
ALWAYS	1446	4	4	100.00
CONT_ASSIGN	1452	1	1	100.00
ALWAYS	1475	4	4	100.00
ALWAYS	1485	3	3	100.00
CONT_ASSIGN	1496	1	1	100.00
CONT_ASSIGN	1500	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	1	1
347	1	1
352	0	1
421	1	1
422	1	1
426	1	1
429	1	1
430	1	1
431	1	1
432	1	1
434	1	1
436	1	1
440	1	1
444	1	1
448	1	1
464	1	1
465	1	1
466	1	1
469	1	1
473	1	1
474	1	1
478	1	1
481	1	1
488	1	1
489	1	1
490	1	1
491	1	1
492	1	1
493	1	1
			MISSING_ELSE
			MISSING_ELSE
513	1	1
518	1	1
525	1	1
528	1	1
529	1	1
530	1	1
532	1	1
533	1	1
535	1	1
537		unreachable
539	1	1
543	1	1
545	1	1
546	1	1
549	1	1
550	1	1
553	1	1
561	1	1
562	1	1
563	1	1
564	1	1
566	1	1
571	1	1
577	1	1
578	1	1
579	1	1
587	1	1
629	1	1
635	1	1
643	1	1
648	1	1
651	1	1
652	1	1
653	1	1
655	1	1
656	1	1
679	1	1
684	1	1
687	1	1
689	1	1
694	1	1
698	1	1
702	1	1
706	0	1
710	0	1
723	1	1
728	0	1
735	1	1
745	1	1
765	3	3
769	1	1
771	1	1
772	1	1
774	1	1
776	1	1
778	1	1
779	1	1
782	1	1
785	1	1
791	1	1
792	1	1
794	1	1
799	1	1
800	1	1
801	1	1
803	1	1
809	1	1
814	1	1
815	1	1
817	1	1
819	1	1
825	1	1
826	1	1
828	1	1
834	1	1
835	1	1
847	1	1
848	1	1
			MISSING_ELSE
920	1	1
923	1	1
992	1	1
994	1	1
1029	1	1
1034	1	1
1035	1	1
1037	1	1
1040		unreachable
1161	1	1
1162	1	1
1315	0	1
1316	1	1
1317	1	1
1327	1	1
1328	1	1
1334	1	1
1335	1	1
1336	1	1
1337	1	1
1340	1	1
1349	1	1
1391	1	1
1405	1	1
1412	1	1
1417	1	1
1423	1	1
1424	1	1
1425	1	1
1426	0	1
1427	1	1
1428	1	1
			MISSING_ELSE
1432	1	1
1434	1	1
1446	1	1
1447	1	1
1448	1	1
1449	1	1
			MISSING_ELSE
1452	1	1
1475	1	1
1476	1	1
1477	1	1
1479	1	1
			MISSING_ELSE
1485	1	1
1486	1	1
1489	1	1
1496	1	1
1500	1	1
1502	6	6

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T24,T38

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T24,T38

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T43,T44
1	0	Covered	T1,T3,T13
1	1	Covered	T1,T3,T13

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T21,T22

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T1,T3,T13

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T25,T39,T40
1	Covered	T1,T2,T3

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T3,T14,T18
0	0	1	0	Not Covered
0	1	0	0	Covered	T3,T18,T4
1	0	0	0	Covered	T23,T24,T25

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T10,T11,T12

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T10,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T10,T11,T12
0	0	1	0	0	0	Covered	T10,T11,T12
0	1	0	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	0	Covered	T10,T11,T12

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T3,T13,T14
1	Covered	T1,T2,T3

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T1,T2,T3

 LINE       1029
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T13
1	0	Not Covered
1	1	Covered	T1,T3,T13

 LINE       1162
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T13

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T45,T46,T47

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T45,T46,T47

 LINE       1434
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T10,T11,T12
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	64	100.00
Total Bits	4160	4160	100.00
Total Bits 0->1	2080	2080	100.00
Total Bits 1->0	2080	2080	100.00

Ports	64	64	100.00
Port Bits	4160	4160	100.00
Port Bits 0->1	2080	2080	100.00
Port Bits 1->0	2080	2080	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T24,T25	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T4,T24,T25	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T4,T24,T25	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T13	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T16,T17	Yes	T3,T16,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T24,T48,T49	Yes	T24,T48,T49	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
keymgr_key_i.key[1:0][255:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
keymgr_key_i.valid	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
app_i[0].last	Yes	Yes	T2,T3,T18	Yes	T2,T3,T14	INPUT
app_i[0].strb[7:0]	Yes	Yes	T28,T26,T24	Yes	T28,T26,T24	INPUT
app_i[0].data[63:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
app_i[0].valid	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
app_i[1].last	Yes	Yes	T2,T3,T28	Yes	T2,T3,T18	INPUT
app_i[1].strb[7:0]	Yes	Yes	T28,T26,T24	Yes	T28,T26,T24	INPUT
app_i[1].data[63:0]	Yes	Yes	T2,T3,T18	Yes	T2,T3,T18	INPUT
app_i[1].valid	Yes	Yes	T2,T3,T18	Yes	T2,T3,T18	INPUT
app_i[2].last	Yes	Yes	T2,T3,T28	Yes	T2,T3,T14	INPUT
app_i[2].strb[7:0]	Yes	Yes	T28,T26,T24	Yes	T28,T26,T24	INPUT
app_i[2].data[63:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
app_i[2].valid	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
app_o[0].error	Yes	Yes	T4,T23,T24	Yes	T4,T23,T24	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
app_o[0].done	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
app_o[0].ready	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
app_o[1].error	Yes	Yes	T23,T24,T50	Yes	T23,T24,T50	OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	Yes	Yes	T2,T3,T28	Yes	T2,T3,T28	OUTPUT
app_o[1].done	Yes	Yes	T2,T3,T18	Yes	T2,T3,T18	OUTPUT
app_o[1].ready	Yes	Yes	T2,T3,T18	Yes	T2,T3,T18	OUTPUT
app_o[2].error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	Yes	Yes	T2,T14,T18	Yes	T2,T14,T18	OUTPUT
app_o[2].done	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
app_o[2].ready	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
intr_kmac_done_o	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	OUTPUT
intr_fifo_empty_o	Yes	Yes	T25,T39,T40	Yes	T25,T39,T40	OUTPUT
intr_kmac_err_o	Yes	Yes	T3,T14,T18	Yes	T3,T14,T18	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	817	Covered	T1,T3,T13
KmacIdle	785	Covered	T1,T2,T3
KmacKeyBlock	792	Covered	T1,T2,T3
KmacMsgFeed	782	Covered	T1,T2,T3
KmacPrefix	779	Covered	T1,T2,T3
KmacTerminalError	834	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	826	Covered	T1,T3,T13
KmacDigest->KmacTerminalError	848	Covered	T51,T52,T53
KmacIdle->KmacMsgFeed	782	Covered	T3,T13,T14
KmacIdle->KmacPrefix	779	Covered	T1,T2,T3
KmacIdle->KmacTerminalError	848	Covered	T10,T11,T35
KmacKeyBlock->KmacMsgFeed	801	Covered	T1,T2,T3
KmacKeyBlock->KmacTerminalError	848	Covered	T54,T55,T56
KmacMsgFeed->KmacDigest	817	Covered	T1,T3,T13
KmacMsgFeed->KmacIdle	814	Covered	T2,T3,T14
KmacMsgFeed->KmacTerminalError	848	Covered	T4,T5,T6
KmacPrefix->KmacKeyBlock	792	Covered	T1,T2,T3
KmacPrefix->KmacMsgFeed	792	Covered	T2,T3,T14
KmacPrefix->KmacTerminalError	848	Covered	T57,T7,T8

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	426	2	2	100.00
TERNARY	635	4	4	100.00
TERNARY	643	4	4	100.00
TERNARY	648	2	2	100.00
CASE	434	6	5	83.33
IF	488	3	3	100.00
IF	561	3	3	100.00
IF	651	2	2	100.00
CASE	689	6	4	66.67
IF	765	2	2	100.00
CASE	774	15	15	100.00
IF	847	2	2	100.00
TERNARY	1162	2	2	100.00
IF	1423	4	3	75.00
IF	1446	3	3	100.00
IF	1475	3	3	100.00
IF	1485	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	635	(msgfifo_full) ? 
-2-:	635	(msgfifo_empty_negedge) ? 
-3-:	635	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T14
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	643	(app_active) ? 
-2-:	643	((sha3_fsm != StAbsorb)) ? 
-3-:	643	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T14
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T13
0	0	0	Covered	T1,T3,T13

	LineNo.	Expression
-1-:	648	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T25,T39,T40

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T3,T14,T18
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	if ((!rst_ni))
-2-:	563	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	651	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	689	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T3,T18,T4
errchecker_err.valid	Covered	T3,T14,T18
sha3_err.valid	Covered	T23,T24,T25
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	765	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	774	case (kmac_st)
-2-:	776	if ((kmac_cmd == CmdStart))
-3-:	778	if ((CShake == app_sha3_mode))
-4-:	791	if (sha3_block_processed)
-5-:	792	(app_kmac_en) ? 
-6-:	800	if (sha3_block_processed)
-7-:	809	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	815	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	825	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	1	0	-	-	-	-	-	-	Covered	T3,T13,T14
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T2,T3,T14
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T2,T3,T14
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T3,T13
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T3,T13
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T3,T13
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	847	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1162	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1423	if ((!rst_ni))
-2-:	1425	if (alert_recov_operation)
-3-:	1427	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1446	if ((!rst_ni))
-2-:	1448	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1475	if ((!rst_ni))
-2-:	1477	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1485	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	1434716550	1434564199	0	0
CmdSparse_M	1434716550	745572	0	0
EnMaskingKnown_A	1434716550	1434564199	0	0
EntropyReadyLatched_A	1434716550	187597	0	0
EntrySizeRegSameToEntrySizePkg_A	948	948	0	0
ErrProcessedLatched_A	1434716550	438	0	0
FifoEmpty_A	1434716550	1434564199	0	0
FpvSecCmErrorCheckFsmCheck_A	1434716550	70	0	0
FpvSecCmKeccackFsmCheck_A	1434716550	70	0	0
FpvSecCmKeyIndexCountCheck_A	1434716550	70	0	0
FpvSecCmKmacAppFsmCheck_A	1434716550	70	0	0
FpvSecCmKmacCoreFsmCheck_A	1434716550	70	0	0
FpvSecCmKmacFsmCheck_A	1434716550	70	0	0
FpvSecCmRegWeOnehotCheck_A	1434716550	70	0	0
FpvSecCmRoundCountCheck_A	1434716550	70	0	0
FpvSecCmSHA3FsmCheck_A	1434716550	70	0	0
FpvSecCmSHA3padFsmCheck_A	1434716550	70	0	0
FpvSecCmSentMsgCountCheck_A	1434716550	70	0	0
KmacCmd_A	1434716550	1434564199	0	0
KmacDone_A	1434716550	1434564199	0	0
KmacErr_A	1434716550	1434564199	0	0
KmacStKnown_A	1434716550	1434564199	0	0
NumAlerts2_A	948	948	0	0
NumEntriesRegSameToNumEntriesPkg_A	948	948	0	0
PrefixRegSameToPrefixPkg_A	948	948	0	0
SecretKeyDivideBy32_A	948	948	0	0
Sha3AbsorbedPulse_A	1434716550	193432	0	0
TlOAReadyKnown_A	1434716550	1434564199	0	0
TlODValidKnown_A	1434716550	1434564199	0	0
u_state_regs_A	1434716550	1434564199	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	745572	0	0
T1	16374	28	0	0
T2	137627	11	0	0
T3	382357	1173	0	0
T13	612625	1201	0	0
T14	135914	400	0	0
T15	591860	1187	0	0
T16	21501	27	0	0
T17	17269	28	0	0
T18	157175	1091	0	0
T19	464581	990	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	187597	0	0
T1	16374	9	0	0
T2	137627	0	0	0
T3	382357	166	0	0
T13	612625	360	0	0
T14	135914	55	0	0
T15	591860	367	0	0
T16	21501	9	0	0
T17	17269	8	0	0
T18	157175	149	0	0
T19	464581	294	0	0
T37	0	301	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	438	0	0
T5	3587	0	0	0
T6	33709	0	0	0
T20	99688	16	0	0
T21	0	4	0	0
T22	0	8	0	0
T30	374091	0	0	0
T38	381094	0	0	0
T58	0	3	0	0
T59	0	7	0	0
T60	0	4	0	0
T61	0	6	0	0
T62	0	15	0	0
T63	0	5	0	0
T64	0	4	0	0
T65	471808	0	0	0
T66	62148	0	0	0
T67	16905	0	0	0
T68	72521	0	0	0
T69	253498	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	70	0	0
T10	290888	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T21	44512	0	0	0
T27	130047	0	0	0
T33	4370	0	0	0
T45	1059	0	0	0
T46	1051	0	0	0
T70	0	10	0	0
T71	0	20	0	0
T72	957603	0	0	0
T73	24192	0	0	0
T74	180788	0	0	0
T75	16570	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	193432	0	0
T1	16374	9	0	0
T2	137627	32	0	0
T3	382357	152	0	0
T13	612625	374	0	0
T14	135914	56	0	0
T15	591860	374	0	0
T16	21501	9	0	0
T17	17269	9	0	0
T18	157175	144	0	0
T19	464581	310	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434716550	1434564199	0	0
T1	16374	16279	0	0
T2	137627	137556	0	0
T3	382357	382304	0	0
T13	612625	612616	0	0
T14	135914	135841	0	0
T15	591860	591854	0	0
T16	21501	21430	0	0
T17	17269	17198	0	0
T18	157175	157168	0	0
T19	464581	464573	0	0