Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1479125817	80334	0	0
entropy_period_rd_A	1479125817	1597	0	0
intr_enable_rd_A	1479125817	2127	0	0
prefix_0_rd_A	1479125817	1661	0	0
prefix_10_rd_A	1479125817	1552	0	0
prefix_1_rd_A	1479125817	1624	0	0
prefix_2_rd_A	1479125817	1531	0	0
prefix_3_rd_A	1479125817	1709	0	0
prefix_4_rd_A	1479125817	1561	0	0
prefix_5_rd_A	1479125817	1694	0	0
prefix_6_rd_A	1479125817	1589	0	0
prefix_7_rd_A	1479125817	1685	0	0
prefix_8_rd_A	1479125817	1554	0	0
prefix_9_rd_A	1479125817	1653	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	80334	0	0
T25	942890	0	0	0
T28	564140	54202	0	0
T38	235012	0	0	0
T53	0	23004	0	0
T54	0	3	0	0
T79	643080	0	0	0
T80	104367	0	0	0
T91	729006	0	0	0
T92	923563	0	0	0
T113	0	1	0	0
T114	0	2	0	0
T116	0	2	0	0
T117	0	2	0	0
T118	0	22	0	0
T125	0	7	0	0
T127	0	1	0	0
T128	113413	0	0	0
T129	6096	0	0	0
T130	434399	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1597	0	0
T54	7032	17	0	0
T96	2595	6	0	0
T114	8411	31	0	0
T116	22855	112	0	0
T143	12621	79	0	0
T144	10217	131	0	0
T145	4465	10	0	0
T146	144936	223	0	0
T147	1895	5	0	0
T148	4414	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	2127	0	0
T54	7032	13	0	0
T96	2595	3	0	0
T114	8411	28	0	0
T116	22855	177	0	0
T120	896	8	0	0
T121	1988	17	0	0
T143	12621	57	0	0
T144	10217	45	0	0
T145	4465	17	0	0
T146	144936	486	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1661	0	0
T54	7032	16	0	0
T96	2595	3	0	0
T101	3172	2	0	0
T114	8411	11	0	0
T116	22855	87	0	0
T143	12621	52	0	0
T144	10217	35	0	0
T145	4465	12	0	0
T146	144936	437	0	0
T148	4414	10	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1552	0	0
T54	7032	12	0	0
T96	2595	4	0	0
T114	8411	17	0	0
T116	22855	76	0	0
T143	12621	32	0	0
T144	10217	23	0	0
T145	4465	11	0	0
T146	144936	474	0	0
T147	1895	2	0	0
T148	4414	8	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1624	0	0
T54	7032	10	0	0
T96	2595	2	0	0
T114	8411	15	0	0
T116	22855	86	0	0
T143	12621	25	0	0
T144	10217	20	0	0
T145	4465	10	0	0
T146	144936	454	0	0
T147	1895	7	0	0
T148	4414	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1531	0	0
T54	7032	5	0	0
T96	2595	3	0	0
T114	8411	8	0	0
T116	22855	77	0	0
T143	12621	57	0	0
T144	10217	68	0	0
T145	4465	12	0	0
T146	144936	459	0	0
T147	1895	3	0	0
T148	4414	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1709	0	0
T96	2595	11	0	0
T101	3172	4	0	0
T114	8411	24	0	0
T116	22855	97	0	0
T143	12621	58	0	0
T144	10217	56	0	0
T145	4465	8	0	0
T146	144936	461	0	0
T147	1895	1	0	0
T148	4414	9	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1561	0	0
T96	2595	4	0	0
T101	3172	3	0	0
T114	8411	11	0	0
T116	22855	92	0	0
T143	12621	56	0	0
T144	10217	27	0	0
T145	4465	11	0	0
T146	144936	413	0	0
T148	4414	2	0	0
T149	52258	420	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1694	0	0
T54	7032	17	0	0
T96	2595	9	0	0
T101	3172	1	0	0
T114	8411	16	0	0
T116	22855	71	0	0
T143	12621	34	0	0
T144	10217	79	0	0
T145	4465	4	0	0
T146	144936	452	0	0
T148	4414	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1589	0	0
T54	7032	6	0	0
T96	2595	2	0	0
T114	8411	20	0	0
T116	22855	65	0	0
T143	12621	48	0	0
T144	10217	40	0	0
T145	4465	6	0	0
T146	144936	469	0	0
T147	1895	3	0	0
T148	4414	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1685	0	0
T54	7032	9	0	0
T96	2595	9	0	0
T114	8411	14	0	0
T116	22855	86	0	0
T143	12621	29	0	0
T144	10217	65	0	0
T145	4465	14	0	0
T146	144936	464	0	0
T147	1895	6	0	0
T148	4414	6	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1554	0	0
T54	7032	2	0	0
T96	2595	10	0	0
T114	8411	30	0	0
T116	22855	66	0	0
T143	12621	29	0	0
T144	10217	36	0	0
T145	4465	8	0	0
T146	144936	456	0	0
T147	1895	6	0	0
T148	4414	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479125817	1653	0	0
T54	7032	2	0	0
T96	2595	7	0	0
T114	8411	12	0	0
T116	22855	76	0	0
T143	12621	32	0	0
T144	10217	18	0	0
T145	4465	7	0	0
T146	144936	465	0	0
T147	1895	2	0	0
T148	4414	6	0	0