Line Coverage for Module :
kmac
| Line No. | Total | Covered | Percent |
TOTAL | | 161 | 155 | 96.27 |
ALWAYS | 346 | 0 | 0 | |
ALWAYS | 346 | 2 | 2 | 100.00 |
ALWAYS | 352 | 1 | 0 | 0.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 422 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
ALWAYS | 429 | 9 | 9 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 465 | 1 | 1 | 100.00 |
CONT_ASSIGN | 466 | 1 | 1 | 100.00 |
CONT_ASSIGN | 469 | 1 | 1 | 100.00 |
CONT_ASSIGN | 473 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 478 | 1 | 1 | 100.00 |
CONT_ASSIGN | 481 | 1 | 1 | 100.00 |
ALWAYS | 488 | 6 | 6 | 100.00 |
CONT_ASSIGN | 513 | 1 | 1 | 100.00 |
CONT_ASSIGN | 518 | 1 | 1 | 100.00 |
CONT_ASSIGN | 525 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 529 | 1 | 1 | 100.00 |
CONT_ASSIGN | 530 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 533 | 1 | 1 | 100.00 |
CONT_ASSIGN | 535 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 0 | 0 | |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 543 | 1 | 1 | 100.00 |
CONT_ASSIGN | 545 | 1 | 1 | 100.00 |
CONT_ASSIGN | 546 | 1 | 1 | 100.00 |
CONT_ASSIGN | 549 | 1 | 1 | 100.00 |
CONT_ASSIGN | 550 | 1 | 1 | 100.00 |
CONT_ASSIGN | 553 | 1 | 1 | 100.00 |
ALWAYS | 561 | 5 | 5 | 100.00 |
CONT_ASSIGN | 571 | 1 | 1 | 100.00 |
CONT_ASSIGN | 577 | 1 | 1 | 100.00 |
CONT_ASSIGN | 578 | 1 | 1 | 100.00 |
CONT_ASSIGN | 579 | 1 | 1 | 100.00 |
CONT_ASSIGN | 587 | 1 | 1 | 100.00 |
CONT_ASSIGN | 629 | 1 | 1 | 100.00 |
CONT_ASSIGN | 635 | 1 | 1 | 100.00 |
CONT_ASSIGN | 643 | 1 | 1 | 100.00 |
CONT_ASSIGN | 648 | 1 | 1 | 100.00 |
ALWAYS | 651 | 5 | 5 | 100.00 |
CONT_ASSIGN | 679 | 1 | 1 | 100.00 |
CONT_ASSIGN | 684 | 1 | 1 | 100.00 |
ALWAYS | 687 | 7 | 5 | 71.43 |
CONT_ASSIGN | 723 | 1 | 1 | 100.00 |
CONT_ASSIGN | 728 | 1 | 0 | 0.00 |
CONT_ASSIGN | 735 | 1 | 1 | 100.00 |
CONT_ASSIGN | 745 | 1 | 1 | 100.00 |
ALWAYS | 765 | 3 | 3 | 100.00 |
ALWAYS | 769 | 28 | 28 | 100.00 |
CONT_ASSIGN | 920 | 1 | 1 | 100.00 |
CONT_ASSIGN | 923 | 1 | 1 | 100.00 |
CONT_ASSIGN | 992 | 1 | 1 | 100.00 |
CONT_ASSIGN | 994 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1029 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1034 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1035 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1037 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1040 | 0 | 0 | |
ALWAYS | 1161 | 0 | 0 | |
ALWAYS | 1161 | 2 | 2 | 100.00 |
CONT_ASSIGN | 1315 | 1 | 0 | 0.00 |
CONT_ASSIGN | 1316 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1327 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1328 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1335 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1337 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1340 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1391 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1405 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1412 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1417 | 1 | 1 | 100.00 |
ALWAYS | 1423 | 6 | 5 | 83.33 |
CONT_ASSIGN | 1432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1434 | 1 | 1 | 100.00 |
ALWAYS | 1446 | 4 | 4 | 100.00 |
CONT_ASSIGN | 1452 | 1 | 1 | 100.00 |
ALWAYS | 1475 | 4 | 4 | 100.00 |
ALWAYS | 1485 | 3 | 3 | 100.00 |
CONT_ASSIGN | 1496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1500 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
346 |
1 |
1 |
347 |
1 |
1 |
352 |
0 |
1 |
421 |
1 |
1 |
422 |
1 |
1 |
426 |
1 |
1 |
429 |
1 |
1 |
430 |
1 |
1 |
431 |
1 |
1 |
432 |
1 |
1 |
434 |
1 |
1 |
436 |
1 |
1 |
440 |
1 |
1 |
444 |
1 |
1 |
448 |
1 |
1 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
469 |
1 |
1 |
473 |
1 |
1 |
474 |
1 |
1 |
478 |
1 |
1 |
481 |
1 |
1 |
488 |
1 |
1 |
489 |
1 |
1 |
490 |
1 |
1 |
491 |
1 |
1 |
492 |
1 |
1 |
493 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
513 |
1 |
1 |
518 |
1 |
1 |
525 |
1 |
1 |
528 |
1 |
1 |
529 |
1 |
1 |
530 |
1 |
1 |
532 |
1 |
1 |
533 |
1 |
1 |
535 |
1 |
1 |
537 |
|
unreachable |
539 |
1 |
1 |
543 |
1 |
1 |
545 |
1 |
1 |
546 |
1 |
1 |
549 |
1 |
1 |
550 |
1 |
1 |
553 |
1 |
1 |
561 |
1 |
1 |
562 |
1 |
1 |
563 |
1 |
1 |
564 |
1 |
1 |
566 |
1 |
1 |
571 |
1 |
1 |
577 |
1 |
1 |
578 |
1 |
1 |
579 |
1 |
1 |
587 |
1 |
1 |
629 |
1 |
1 |
635 |
1 |
1 |
643 |
1 |
1 |
648 |
1 |
1 |
651 |
1 |
1 |
652 |
1 |
1 |
653 |
1 |
1 |
655 |
1 |
1 |
656 |
1 |
1 |
679 |
1 |
1 |
684 |
1 |
1 |
687 |
1 |
1 |
689 |
1 |
1 |
694 |
1 |
1 |
698 |
1 |
1 |
702 |
1 |
1 |
706 |
0 |
1 |
710 |
0 |
1 |
723 |
1 |
1 |
728 |
0 |
1 |
735 |
1 |
1 |
745 |
1 |
1 |
765 |
3 |
3 |
769 |
1 |
1 |
771 |
1 |
1 |
772 |
1 |
1 |
774 |
1 |
1 |
776 |
1 |
1 |
778 |
1 |
1 |
779 |
1 |
1 |
782 |
1 |
1 |
785 |
1 |
1 |
791 |
1 |
1 |
792 |
1 |
1 |
794 |
1 |
1 |
799 |
1 |
1 |
800 |
1 |
1 |
801 |
1 |
1 |
803 |
1 |
1 |
809 |
1 |
1 |
814 |
1 |
1 |
815 |
1 |
1 |
817 |
1 |
1 |
819 |
1 |
1 |
825 |
1 |
1 |
826 |
1 |
1 |
828 |
1 |
1 |
834 |
1 |
1 |
835 |
1 |
1 |
847 |
1 |
1 |
848 |
1 |
1 |
|
|
|
MISSING_ELSE |
920 |
1 |
1 |
923 |
1 |
1 |
992 |
1 |
1 |
994 |
1 |
1 |
1029 |
1 |
1 |
1034 |
1 |
1 |
1035 |
1 |
1 |
1037 |
1 |
1 |
1040 |
|
unreachable |
1161 |
1 |
1 |
1162 |
1 |
1 |
1315 |
0 |
1 |
1316 |
1 |
1 |
1317 |
1 |
1 |
1327 |
1 |
1 |
1328 |
1 |
1 |
1334 |
1 |
1 |
1335 |
1 |
1 |
1336 |
1 |
1 |
1337 |
1 |
1 |
1340 |
1 |
1 |
1349 |
1 |
1 |
1391 |
1 |
1 |
1405 |
1 |
1 |
1412 |
1 |
1 |
1417 |
1 |
1 |
1423 |
1 |
1 |
1424 |
1 |
1 |
1425 |
1 |
1 |
1426 |
0 |
1 |
1427 |
1 |
1 |
1428 |
1 |
1 |
|
|
|
MISSING_ELSE |
1432 |
1 |
1 |
1434 |
1 |
1 |
1446 |
1 |
1 |
1447 |
1 |
1 |
1448 |
1 |
1 |
1449 |
1 |
1 |
|
|
|
MISSING_ELSE |
1452 |
1 |
1 |
1475 |
1 |
1 |
1476 |
1 |
1 |
1477 |
1 |
1 |
1479 |
1 |
1 |
|
|
|
MISSING_ELSE |
1485 |
1 |
1 |
1486 |
1 |
1 |
1489 |
1 |
1 |
1496 |
1 |
1 |
1500 |
1 |
1 |
1502 |
6 |
6 |
Cond Coverage for Module :
kmac
| Total | Covered | Percent |
Conditions | 90 | 84 | 93.33 |
Logical | 90 | 84 | 93.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 426
EXPRESSION (cmd_update ? cmd_q : CmdNone)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 464
EXPRESSION (sha3_fsm == StIdle)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 465
EXPRESSION (sha3_fsm == StAbsorb)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 466
EXPRESSION (sha3_fsm == StSqueeze)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 478
EXPRESSION (sha3_fsm == StIdle)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 530
EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
------------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T44,T24 |
LINE 539
EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
-------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T27,T45,T26 |
LINE 543
EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
-----------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T46,T47,T48 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 550
EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
------1----- ----2---- ----3----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 563
EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
----------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 563
SUB-EXPRESSION (sha3_fsm == StIdle)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 563
SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
------1------ ---------2--------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T1,T2,T3 |
LINE 571
EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
-------------1------------ -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T18,T21 |
LINE 629
EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
-------1------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 635
EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T28 |
LINE 635
SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 635
SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 643
EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T13 |
LINE 643
SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 643
SUB-EXPRESSION (sha3_fsm != StAbsorb)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 643
SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 648
EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
---------1--------
-1- | Status | Tests |
0 | Covered | T28,T39,T40 |
1 | Covered | T1,T2,T3 |
LINE 679
EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
-------1------ ------2------ --------3-------- ----------4---------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Covered | T2,T29,T49 |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Covered | T2,T13,T18 |
1 | 0 | 0 | 0 | Covered | T22,T23,T24 |
LINE 723
EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
--------1------- ---------------2--------------- -------3------- ----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Covered | T10,T11,T12 |
0 | 1 | 0 | 0 | Unreachable | |
1 | 0 | 0 | 0 | Covered | T10,T11,T12 |
LINE 735
EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
--------1------- -----------2----------- ----------3---------- ----------4--------- ------------5----------- --------6-------
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 0 | 1 | Covered | T10,T11,T12 |
0 | 0 | 0 | 0 | 1 | 0 | Unreachable | |
0 | 0 | 0 | 1 | 0 | 0 | Covered | T10,T11,T12 |
0 | 0 | 1 | 0 | 0 | 0 | Covered | T10,T11,T12 |
0 | 1 | 0 | 0 | 0 | 0 | Covered | T10,T11,T12 |
1 | 0 | 0 | 0 | 0 | 0 | Covered | T10,T11,T12 |
LINE 776
EXPRESSION (kmac_cmd == CmdStart)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 778
EXPRESSION (CShake == app_sha3_mode)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T13 |
LINE 792
EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T16 |
1 | Covered | T1,T2,T13 |
LINE 1029
EXPRESSION (tlram_req & tlram_we)
----1---- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 1162
EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1405
SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
-----------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T20,T50,T51 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T20,T50,T51 |
LINE 1405
SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
-------------------1------------------- --------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T20,T50,T51 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T20,T50,T51 |
LINE 1434
EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
----------1--------- -------2------ --------3------- ------4------ -----------5-----------
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 0 | 1 | 0 | Covered | T10,T11,T12 |
0 | 0 | 1 | 0 | 0 | Covered | T4,T5,T6 |
0 | 1 | 0 | 0 | 0 | Covered | T10,T11,T12 |
1 | 0 | 0 | 0 | 0 | Not Covered | |
Toggle Coverage for Module :
kmac
| Total | Covered | Percent |
Totals |
71 |
64 |
90.14 |
Total Bits |
6534 |
4160 |
63.67 |
Total Bits 0->1 |
3267 |
2080 |
63.67 |
Total Bits 1->0 |
3267 |
2080 |
63.67 |
| | | |
Ports |
71 |
64 |
90.14 |
Port Bits |
6534 |
4160 |
63.67 |
Port Bits 0->1 |
3267 |
2080 |
63.67 |
Port Bits 1->0 |
3267 |
2080 |
63.67 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T28,T4,T45 |
Yes |
T1,T2,T3 |
INPUT |
rst_shadowed_ni |
Yes |
Yes |
T28,T4,T45 |
Yes |
T1,T2,T3 |
INPUT |
clk_edn_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_edn_ni |
Yes |
Yes |
T28,T4,T45 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T2,T52,T27 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T28,T53,T54 |
Yes |
T28,T53,T54 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T20,T50,T51 |
Yes |
T20,T50,T51 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[1].ack_p |
Yes |
Yes |
T20,T4,T50 |
Yes |
T20,T4,T50 |
INPUT |
alert_rx_i[1].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T20,T50,T51 |
Yes |
T20,T50,T51 |
OUTPUT |
alert_tx_o[1].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[1].alert_p |
Yes |
Yes |
T20,T4,T50 |
Yes |
T20,T4,T50 |
OUTPUT |
keymgr_key_i.key[0][4:0] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][5] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][8:6] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][10:9] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][11] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][12] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][13] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][15:14] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][17:16] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][19:18] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][20] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][22:21] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][23] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][24] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][25] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][26] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][28:27] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][30:29] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][31] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][32] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][33] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][38:34] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][39] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][40] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][42:41] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][43] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][45:44] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][46] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][47] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][48] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][49] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][50] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][51] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][52] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][53] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][54] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][56:55] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][58:57] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][61:59] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][62] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][64:63] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][65] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][66] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][68:67] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][73:69] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][75:74] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][76] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][77] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][80:78] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][81] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][82] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][83] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][85:84] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][86] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][87] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][88] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][89] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][90] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][91] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][92] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][93] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][94] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][95] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][97:96] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][101:98] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][104:102] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][105] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][106] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][109:107] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][111:110] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][112] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][113] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][114] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][115] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][120:116] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][121] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][122] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][125:123] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][126] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][128:127] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][129] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][130] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][131] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][132] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][133] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][134] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][135] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][136] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][137] |
Yes |
Yes |
T2,T15,T16 |
Yes |
T2,T15,T16 |
INPUT |
keymgr_key_i.key[0][138] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][140:139] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][142:141] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][147:143] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][150:148] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][154:151] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][156:155] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][157] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][159:158] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][160] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][164:161] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][166:165] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][167] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][170:168] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][171] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][172] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][175:173] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][180:176] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][184:181] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][185] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][186] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][187] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][190:188] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][191] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][193:192] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][194] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][195] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][197:196] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][198] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][201:199] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][204:202] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][205] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][206] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][207] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][209:208] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][210] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][211] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][214:212] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][215] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][216] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][217] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][218] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][219] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][221:220] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][225:222] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][226] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][230:227] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][234:231] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][239:235] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][240] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][241] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][243:242] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][244] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][245] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][246] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][248:247] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][252:249] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][253] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][254] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][255] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][0] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][1] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][2] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][4:3] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][5] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][6] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][7] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][9:8] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][10] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][13:11] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][14] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][17:15] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][18] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][19] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][20] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][22:21] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][23] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][24] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][25] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][26] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][28:27] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][29] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][30] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][31] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][33:32] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][34] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][35] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][37:36] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][38] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][39] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][40] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][41] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][43:42] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][44] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][46:45] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][47] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][48] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][51:49] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][52] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][54:53] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][55] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][56] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][58:57] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][59] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][60] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][61] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][62] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][64:63] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][65] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][67:66] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][68] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][70:69] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][71] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][73:72] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][75:74] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][76] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][77] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][78] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][79] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][81:80] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][82] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][83] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][85:84] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][88:86] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][89] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][90] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][91] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][92] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][93] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][94] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][97:95] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][98] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][99] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][100] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][102:101] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][103] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][104] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][105] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][106] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][107] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][109:108] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][111:110] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][114:112] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][115] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][117:116] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][118] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][119] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][120] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][122:121] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][125:123] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][127:126] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][128] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][129] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][130] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][131] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][132] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][133] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][134] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][136:135] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][137] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][140:138] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][141] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][142] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][143] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][144] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][148:145] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][149] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][151:150] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][155:152] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][156] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][158:157] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][159] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][162:160] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][163] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][165:164] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][166] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][167] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][168] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][169] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][170] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][171] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][172] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][173] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][175:174] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][177:176] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][178] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][183:179] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][184] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][186:185] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][187] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][190:188] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][191] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][192] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][193] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][194] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][195] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][196] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][197] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][198] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][201:199] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][202] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][203] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][205:204] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][206] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][207] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][208] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][209] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][210] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][211] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][215:212] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][216] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][218:217] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][222:219] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][225:223] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][226] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][227] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][228] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][231:229] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][232] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][234:233] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][236:235] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][239:237] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][240] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][242:241] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][243] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][244] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][245] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][246] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][248:247] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][249] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][250] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][251] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][252] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][253] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][254] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][255] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.valid |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
app_i[0].last |
Yes |
Yes |
T1,T13,T16 |
Yes |
T1,T2,T13 |
INPUT |
app_i[0].strb[7:0] |
Yes |
Yes |
T27,T28,T25 |
Yes |
T27,T28,T25 |
INPUT |
app_i[0].data[63:0] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
INPUT |
app_i[0].valid |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
INPUT |
app_i[1].last |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
INPUT |
app_i[1].strb[7:0] |
Yes |
Yes |
T27,T28,T25 |
Yes |
T27,T28,T25 |
INPUT |
app_i[1].data[63:0] |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
INPUT |
app_i[1].valid |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
INPUT |
app_i[2].last |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T2,T16 |
INPUT |
app_i[2].strb[7:0] |
Yes |
Yes |
T27,T25,T45 |
Yes |
T27,T25,T45 |
INPUT |
app_i[2].data[63:0] |
Yes |
Yes |
T1,T2,T16 |
Yes |
T1,T2,T16 |
INPUT |
app_i[2].valid |
Yes |
Yes |
T1,T2,T16 |
Yes |
T1,T2,T16 |
INPUT |
app_o[0].error |
Yes |
Yes |
T13,T18,T4 |
Yes |
T13,T18,T4 |
OUTPUT |
app_o[0].digest_share1[383:0] |
No |
No |
|
No |
|
OUTPUT |
app_o[0].digest_share0[383:0] |
Yes |
Yes |
T1,T16,T28 |
Yes |
T1,T16,T28 |
OUTPUT |
app_o[0].done |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
app_o[0].ready |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
app_o[1].error |
Yes |
Yes |
T22,T24,T55 |
Yes |
T22,T24,T55 |
OUTPUT |
app_o[1].digest_share1[383:0] |
No |
No |
|
No |
|
OUTPUT |
app_o[1].digest_share0[383:0] |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
OUTPUT |
app_o[1].done |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
OUTPUT |
app_o[1].ready |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
OUTPUT |
app_o[2].error |
Yes |
Yes |
T22,T24,T55 |
Yes |
T22,T24,T55 |
OUTPUT |
app_o[2].digest_share1[383:0] |
No |
No |
|
No |
|
OUTPUT |
app_o[2].digest_share0[383:0] |
Yes |
Yes |
T1,T16,T25 |
Yes |
T1,T16,T25 |
OUTPUT |
app_o[2].done |
Yes |
Yes |
T1,T2,T16 |
Yes |
T1,T2,T16 |
OUTPUT |
app_o[2].ready |
Yes |
Yes |
T1,T2,T16 |
Yes |
T1,T2,T16 |
OUTPUT |
entropy_o.edn_req |
No |
No |
|
No |
|
OUTPUT |
entropy_i.edn_bus[31:0] |
No |
No |
|
No |
|
INPUT |
entropy_i.edn_fips |
No |
No |
|
No |
|
INPUT |
entropy_i.edn_ack |
No |
No |
|
No |
|
INPUT |
lc_escalate_en_i[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
intr_kmac_done_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
intr_fifo_empty_o |
Yes |
Yes |
T28,T39,T40 |
Yes |
T28,T39,T40 |
OUTPUT |
intr_kmac_err_o |
Yes |
Yes |
T2,T13,T18 |
Yes |
T2,T13,T18 |
OUTPUT |
en_masking_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
idle_o[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
*Tests covering at least one bit in the range
FSM Coverage for Module :
kmac
Summary for FSM :: kmac_st
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
13 |
13 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: kmac_st
states | Line No. | Covered | Tests |
KmacDigest |
817 |
Covered |
T1,T2,T3 |
KmacIdle |
785 |
Covered |
T1,T2,T3 |
KmacKeyBlock |
792 |
Covered |
T1,T2,T13 |
KmacMsgFeed |
782 |
Covered |
T1,T2,T3 |
KmacPrefix |
779 |
Covered |
T1,T2,T13 |
KmacTerminalError |
834 |
Covered |
T4,T5,T6 |
transitions | Line No. | Covered | Tests |
KmacDigest->KmacIdle |
826 |
Covered |
T1,T2,T3 |
KmacDigest->KmacTerminalError |
848 |
Covered |
T56 |
KmacIdle->KmacMsgFeed |
782 |
Covered |
T1,T2,T3 |
KmacIdle->KmacPrefix |
779 |
Covered |
T1,T2,T13 |
KmacIdle->KmacTerminalError |
848 |
Covered |
T5,T10,T11 |
KmacKeyBlock->KmacMsgFeed |
801 |
Covered |
T1,T2,T13 |
KmacKeyBlock->KmacTerminalError |
848 |
Covered |
T57 |
KmacMsgFeed->KmacDigest |
817 |
Covered |
T1,T2,T3 |
KmacMsgFeed->KmacIdle |
814 |
Covered |
T1,T2,T13 |
KmacMsgFeed->KmacTerminalError |
848 |
Covered |
T4,T6,T36 |
KmacPrefix->KmacKeyBlock |
792 |
Covered |
T1,T2,T13 |
KmacPrefix->KmacMsgFeed |
792 |
Covered |
T1,T2,T16 |
KmacPrefix->KmacTerminalError |
848 |
Covered |
T58,T7,T59 |
Branch Coverage for Module :
kmac
| Line No. | Total | Covered | Percent |
Branches |
|
65 |
61 |
93.85 |
TERNARY |
426 |
2 |
2 |
100.00 |
TERNARY |
635 |
4 |
4 |
100.00 |
TERNARY |
643 |
4 |
4 |
100.00 |
TERNARY |
648 |
2 |
2 |
100.00 |
CASE |
434 |
6 |
5 |
83.33 |
IF |
488 |
3 |
3 |
100.00 |
IF |
561 |
3 |
3 |
100.00 |
IF |
651 |
2 |
2 |
100.00 |
CASE |
689 |
6 |
4 |
66.67 |
IF |
765 |
2 |
2 |
100.00 |
CASE |
774 |
15 |
15 |
100.00 |
IF |
847 |
2 |
2 |
100.00 |
TERNARY |
1162 |
2 |
2 |
100.00 |
IF |
1423 |
4 |
3 |
75.00 |
IF |
1446 |
3 |
3 |
100.00 |
IF |
1475 |
3 |
3 |
100.00 |
IF |
1485 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 426 (cmd_update) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 635 (msgfifo_full) ?
-2-: 635 (msgfifo_empty_negedge) ?
-3-: 635 (msgfifo2kmac_process) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T28 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 643 (app_active) ?
-2-: 643 ((sha3_fsm != StAbsorb)) ?
-3-: 643 (msgfifo2kmac_process) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T13 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 648 (msgfifo_empty_gate) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T28,T39,T40 |
LineNo. Expression
-1-: 434 case (kmac_cmd)
Branches:
-1- | Status | Tests |
CmdStart |
Covered |
T1,T2,T3 |
CmdProcess |
Covered |
T1,T2,T3 |
CmdManualRun |
Covered |
T1,T2,T15 |
CmdDone |
Covered |
T1,T2,T3 |
CmdNone |
Covered |
T1,T2,T3 |
default |
Not Covered |
|
LineNo. Expression
-1-: 488 if ((!rst_ni))
-2-: 490 if (engine_stable)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 561 if ((!rst_ni))
-2-: 563 if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 651 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 689 case (1'b1)
Branches:
-1- | Status | Tests |
app_err.valid |
Covered |
T2,T13,T18 |
errchecker_err.valid |
Covered |
T2,T29,T49 |
sha3_err.valid |
Covered |
T22,T23,T24 |
entropy_err.valid |
Not Covered |
|
msgfifo_err.valid |
Not Covered |
|
default |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 765 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 774 case (kmac_st)
-2-: 776 if ((kmac_cmd == CmdStart))
-3-: 778 if ((CShake == app_sha3_mode))
-4-: 791 if (sha3_block_processed)
-5-: 792 (app_kmac_en) ?
-6-: 800 if (sha3_block_processed)
-7-: 809 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-: 815 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-: 825 if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | Status | Tests |
KmacIdle |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
KmacIdle |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
KmacIdle |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
KmacPrefix |
- |
- |
1 |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
KmacPrefix |
- |
- |
1 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T16 |
KmacPrefix |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
KmacKeyBlock |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T13 |
KmacKeyBlock |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T13 |
KmacMsgFeed |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T1,T2,T13 |
KmacMsgFeed |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T1,T2,T3 |
KmacMsgFeed |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T2,T3 |
KmacDigest |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
KmacDigest |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
KmacTerminalError |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T11,T12 |
LineNo. Expression
-1-: 847 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 1162 (reg_state_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 1423 if ((!rst_ni))
-2-: 1425 if (alert_recov_operation)
-3-: 1427 if (err_processed)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T13,T18,T21 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 1446 if ((!rst_ni))
-2-: 1448 if (alert_fatal)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 1475 if ((!rst_ni))
-2-: 1477 if (alerts[1])
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 1485 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
kmac
Assertion Details
AlertKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
CmdSparse_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
835203 |
0 |
0 |
T1 |
104075 |
167 |
0 |
0 |
T2 |
480157 |
359 |
0 |
0 |
T3 |
138038 |
993 |
0 |
0 |
T13 |
27237 |
5 |
0 |
0 |
T14 |
6351 |
29 |
0 |
0 |
T15 |
32419 |
105 |
0 |
0 |
T16 |
432502 |
770 |
0 |
0 |
T17 |
179260 |
1194 |
0 |
0 |
T18 |
120829 |
22 |
0 |
0 |
T19 |
0 |
88 |
0 |
0 |
T20 |
818 |
0 |
0 |
0 |
EnMaskingKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
EntropyReadyLatched_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
211980 |
0 |
0 |
T1 |
104075 |
38 |
0 |
0 |
T2 |
480157 |
56 |
0 |
0 |
T3 |
138038 |
299 |
0 |
0 |
T13 |
27237 |
4 |
0 |
0 |
T14 |
6351 |
9 |
0 |
0 |
T15 |
32419 |
13 |
0 |
0 |
T16 |
432502 |
155 |
0 |
0 |
T17 |
179260 |
364 |
0 |
0 |
T18 |
120829 |
20 |
0 |
0 |
T19 |
0 |
13 |
0 |
0 |
T20 |
818 |
0 |
0 |
0 |
EntrySizeRegSameToEntrySizePkg_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
952 |
952 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
ErrProcessedLatched_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
522 |
0 |
0 |
T13 |
27237 |
4 |
0 |
0 |
T14 |
6351 |
0 |
0 |
0 |
T15 |
32419 |
0 |
0 |
0 |
T16 |
432502 |
0 |
0 |
0 |
T17 |
179260 |
0 |
0 |
0 |
T18 |
120829 |
20 |
0 |
0 |
T19 |
29419 |
0 |
0 |
0 |
T20 |
818 |
0 |
0 |
0 |
T21 |
0 |
8 |
0 |
0 |
T27 |
91766 |
0 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T52 |
483707 |
0 |
0 |
0 |
T60 |
0 |
11 |
0 |
0 |
T61 |
0 |
17 |
0 |
0 |
T62 |
0 |
14 |
0 |
0 |
T63 |
0 |
6 |
0 |
0 |
T64 |
0 |
15 |
0 |
0 |
T65 |
0 |
10 |
0 |
0 |
FifoEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
FpvSecCmErrorCheckFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmKeccackFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmKeyIndexCountCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmKmacAppFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmKmacCoreFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmKmacFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmRoundCountCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmSHA3FsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmSHA3padFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmSentMsgCountCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
KmacCmd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
KmacDone_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
KmacErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
KmacStKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
NumAlerts2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
952 |
952 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
NumEntriesRegSameToNumEntriesPkg_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
952 |
952 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
PrefixRegSameToPrefixPkg_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
952 |
952 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
SecretKeyDivideBy32_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
952 |
952 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
Sha3AbsorbedPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
218580 |
0 |
0 |
T1 |
104075 |
38 |
0 |
0 |
T2 |
480157 |
52 |
0 |
0 |
T3 |
138038 |
310 |
0 |
0 |
T13 |
27237 |
4 |
0 |
0 |
T14 |
6351 |
9 |
0 |
0 |
T15 |
32419 |
13 |
0 |
0 |
T16 |
432502 |
155 |
0 |
0 |
T17 |
179260 |
374 |
0 |
0 |
T18 |
120829 |
20 |
0 |
0 |
T19 |
0 |
13 |
0 |
0 |
T20 |
818 |
0 |
0 |
0 |
TlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
TlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
Line Coverage for Instance : tb.dut
| Line No. | Total | Covered | Percent |
TOTAL | | 161 | 155 | 96.27 |
ALWAYS | 346 | 0 | 0 | |
ALWAYS | 346 | 2 | 2 | 100.00 |
ALWAYS | 352 | 1 | 0 | 0.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 422 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
ALWAYS | 429 | 9 | 9 | 100.00 |
CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
CONT_ASSIGN | 465 | 1 | 1 | 100.00 |
CONT_ASSIGN | 466 | 1 | 1 | 100.00 |
CONT_ASSIGN | 469 | 1 | 1 | 100.00 |
CONT_ASSIGN | 473 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 478 | 1 | 1 | 100.00 |
CONT_ASSIGN | 481 | 1 | 1 | 100.00 |
ALWAYS | 488 | 6 | 6 | 100.00 |
CONT_ASSIGN | 513 | 1 | 1 | 100.00 |
CONT_ASSIGN | 518 | 1 | 1 | 100.00 |
CONT_ASSIGN | 525 | 1 | 1 | 100.00 |
CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
CONT_ASSIGN | 529 | 1 | 1 | 100.00 |
CONT_ASSIGN | 530 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 533 | 1 | 1 | 100.00 |
CONT_ASSIGN | 535 | 1 | 1 | 100.00 |
CONT_ASSIGN | 537 | 0 | 0 | |
CONT_ASSIGN | 539 | 1 | 1 | 100.00 |
CONT_ASSIGN | 543 | 1 | 1 | 100.00 |
CONT_ASSIGN | 545 | 1 | 1 | 100.00 |
CONT_ASSIGN | 546 | 1 | 1 | 100.00 |
CONT_ASSIGN | 549 | 1 | 1 | 100.00 |
CONT_ASSIGN | 550 | 1 | 1 | 100.00 |
CONT_ASSIGN | 553 | 1 | 1 | 100.00 |
ALWAYS | 561 | 5 | 5 | 100.00 |
CONT_ASSIGN | 571 | 1 | 1 | 100.00 |
CONT_ASSIGN | 577 | 1 | 1 | 100.00 |
CONT_ASSIGN | 578 | 1 | 1 | 100.00 |
CONT_ASSIGN | 579 | 1 | 1 | 100.00 |
CONT_ASSIGN | 587 | 1 | 1 | 100.00 |
CONT_ASSIGN | 629 | 1 | 1 | 100.00 |
CONT_ASSIGN | 635 | 1 | 1 | 100.00 |
CONT_ASSIGN | 643 | 1 | 1 | 100.00 |
CONT_ASSIGN | 648 | 1 | 1 | 100.00 |
ALWAYS | 651 | 5 | 5 | 100.00 |
CONT_ASSIGN | 679 | 1 | 1 | 100.00 |
CONT_ASSIGN | 684 | 1 | 1 | 100.00 |
ALWAYS | 687 | 7 | 5 | 71.43 |
CONT_ASSIGN | 723 | 1 | 1 | 100.00 |
CONT_ASSIGN | 728 | 1 | 0 | 0.00 |
CONT_ASSIGN | 735 | 1 | 1 | 100.00 |
CONT_ASSIGN | 745 | 1 | 1 | 100.00 |
ALWAYS | 765 | 3 | 3 | 100.00 |
ALWAYS | 769 | 28 | 28 | 100.00 |
CONT_ASSIGN | 920 | 1 | 1 | 100.00 |
CONT_ASSIGN | 923 | 1 | 1 | 100.00 |
CONT_ASSIGN | 992 | 1 | 1 | 100.00 |
CONT_ASSIGN | 994 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1029 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1034 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1035 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1037 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1040 | 0 | 0 | |
ALWAYS | 1161 | 0 | 0 | |
ALWAYS | 1161 | 2 | 2 | 100.00 |
CONT_ASSIGN | 1315 | 1 | 0 | 0.00 |
CONT_ASSIGN | 1316 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1327 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1328 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1335 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1337 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1340 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1391 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1405 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1412 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1417 | 1 | 1 | 100.00 |
ALWAYS | 1423 | 6 | 5 | 83.33 |
CONT_ASSIGN | 1432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1434 | 1 | 1 | 100.00 |
ALWAYS | 1446 | 4 | 4 | 100.00 |
CONT_ASSIGN | 1452 | 1 | 1 | 100.00 |
ALWAYS | 1475 | 4 | 4 | 100.00 |
ALWAYS | 1485 | 3 | 3 | 100.00 |
CONT_ASSIGN | 1496 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1500 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1502 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
346 |
1 |
1 |
347 |
1 |
1 |
352 |
0 |
1 |
421 |
1 |
1 |
422 |
1 |
1 |
426 |
1 |
1 |
429 |
1 |
1 |
430 |
1 |
1 |
431 |
1 |
1 |
432 |
1 |
1 |
434 |
1 |
1 |
436 |
1 |
1 |
440 |
1 |
1 |
444 |
1 |
1 |
448 |
1 |
1 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
469 |
1 |
1 |
473 |
1 |
1 |
474 |
1 |
1 |
478 |
1 |
1 |
481 |
1 |
1 |
488 |
1 |
1 |
489 |
1 |
1 |
490 |
1 |
1 |
491 |
1 |
1 |
492 |
1 |
1 |
493 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
513 |
1 |
1 |
518 |
1 |
1 |
525 |
1 |
1 |
528 |
1 |
1 |
529 |
1 |
1 |
530 |
1 |
1 |
532 |
1 |
1 |
533 |
1 |
1 |
535 |
1 |
1 |
537 |
|
unreachable |
539 |
1 |
1 |
543 |
1 |
1 |
545 |
1 |
1 |
546 |
1 |
1 |
549 |
1 |
1 |
550 |
1 |
1 |
553 |
1 |
1 |
561 |
1 |
1 |
562 |
1 |
1 |
563 |
1 |
1 |
564 |
1 |
1 |
566 |
1 |
1 |
571 |
1 |
1 |
577 |
1 |
1 |
578 |
1 |
1 |
579 |
1 |
1 |
587 |
1 |
1 |
629 |
1 |
1 |
635 |
1 |
1 |
643 |
1 |
1 |
648 |
1 |
1 |
651 |
1 |
1 |
652 |
1 |
1 |
653 |
1 |
1 |
655 |
1 |
1 |
656 |
1 |
1 |
679 |
1 |
1 |
684 |
1 |
1 |
687 |
1 |
1 |
689 |
1 |
1 |
694 |
1 |
1 |
698 |
1 |
1 |
702 |
1 |
1 |
706 |
0 |
1 |
710 |
0 |
1 |
723 |
1 |
1 |
728 |
0 |
1 |
735 |
1 |
1 |
745 |
1 |
1 |
765 |
3 |
3 |
769 |
1 |
1 |
771 |
1 |
1 |
772 |
1 |
1 |
774 |
1 |
1 |
776 |
1 |
1 |
778 |
1 |
1 |
779 |
1 |
1 |
782 |
1 |
1 |
785 |
1 |
1 |
791 |
1 |
1 |
792 |
1 |
1 |
794 |
1 |
1 |
799 |
1 |
1 |
800 |
1 |
1 |
801 |
1 |
1 |
803 |
1 |
1 |
809 |
1 |
1 |
814 |
1 |
1 |
815 |
1 |
1 |
817 |
1 |
1 |
819 |
1 |
1 |
825 |
1 |
1 |
826 |
1 |
1 |
828 |
1 |
1 |
834 |
1 |
1 |
835 |
1 |
1 |
847 |
1 |
1 |
848 |
1 |
1 |
|
|
|
MISSING_ELSE |
920 |
1 |
1 |
923 |
1 |
1 |
992 |
1 |
1 |
994 |
1 |
1 |
1029 |
1 |
1 |
1034 |
1 |
1 |
1035 |
1 |
1 |
1037 |
1 |
1 |
1040 |
|
unreachable |
1161 |
1 |
1 |
1162 |
1 |
1 |
1315 |
0 |
1 |
1316 |
1 |
1 |
1317 |
1 |
1 |
1327 |
1 |
1 |
1328 |
1 |
1 |
1334 |
1 |
1 |
1335 |
1 |
1 |
1336 |
1 |
1 |
1337 |
1 |
1 |
1340 |
1 |
1 |
1349 |
1 |
1 |
1391 |
1 |
1 |
1405 |
1 |
1 |
1412 |
1 |
1 |
1417 |
1 |
1 |
1423 |
1 |
1 |
1424 |
1 |
1 |
1425 |
1 |
1 |
1426 |
0 |
1 |
1427 |
1 |
1 |
1428 |
1 |
1 |
|
|
|
MISSING_ELSE |
1432 |
1 |
1 |
1434 |
1 |
1 |
1446 |
1 |
1 |
1447 |
1 |
1 |
1448 |
1 |
1 |
1449 |
1 |
1 |
|
|
|
MISSING_ELSE |
1452 |
1 |
1 |
1475 |
1 |
1 |
1476 |
1 |
1 |
1477 |
1 |
1 |
1479 |
1 |
1 |
|
|
|
MISSING_ELSE |
1485 |
1 |
1 |
1486 |
1 |
1 |
1489 |
1 |
1 |
1496 |
1 |
1 |
1500 |
1 |
1 |
1502 |
6 |
6 |
Cond Coverage for Instance : tb.dut
| Total | Covered | Percent |
Conditions | 90 | 84 | 93.33 |
Logical | 90 | 84 | 93.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 426
EXPRESSION (cmd_update ? cmd_q : CmdNone)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 464
EXPRESSION (sha3_fsm == StIdle)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 465
EXPRESSION (sha3_fsm == StAbsorb)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 466
EXPRESSION (sha3_fsm == StSqueeze)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 478
EXPRESSION (sha3_fsm == StIdle)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 530
EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
------------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T44,T24 |
LINE 539
EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
-------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T27,T45,T26 |
LINE 543
EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
-----------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T46,T47,T48 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 550
EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
------1----- ----2---- ----3----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 563
EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
----------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 563
SUB-EXPRESSION (sha3_fsm == StIdle)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 563
SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
------1------ ---------2--------
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T1,T2,T3 |
LINE 571
EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
-------------1------------ -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T18,T21 |
LINE 629
EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
-------1------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 635
EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T28 |
LINE 635
SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 635
SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 643
EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T13 |
LINE 643
SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 643
SUB-EXPRESSION (sha3_fsm != StAbsorb)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 643
SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 648
EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
---------1--------
-1- | Status | Tests |
0 | Covered | T28,T39,T40 |
1 | Covered | T1,T2,T3 |
LINE 679
EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
-------1------ ------2------ --------3-------- ----------4---------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Covered | T2,T29,T49 |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Covered | T2,T13,T18 |
1 | 0 | 0 | 0 | Covered | T22,T23,T24 |
LINE 723
EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
--------1------- ---------------2--------------- -------3------- ----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Covered | T10,T11,T12 |
0 | 1 | 0 | 0 | Unreachable | |
1 | 0 | 0 | 0 | Covered | T10,T11,T12 |
LINE 735
EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
--------1------- -----------2----------- ----------3---------- ----------4--------- ------------5----------- --------6-------
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 0 | 1 | Covered | T10,T11,T12 |
0 | 0 | 0 | 0 | 1 | 0 | Unreachable | |
0 | 0 | 0 | 1 | 0 | 0 | Covered | T10,T11,T12 |
0 | 0 | 1 | 0 | 0 | 0 | Covered | T10,T11,T12 |
0 | 1 | 0 | 0 | 0 | 0 | Covered | T10,T11,T12 |
1 | 0 | 0 | 0 | 0 | 0 | Covered | T10,T11,T12 |
LINE 776
EXPRESSION (kmac_cmd == CmdStart)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 778
EXPRESSION (CShake == app_sha3_mode)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T13 |
LINE 792
EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T16 |
1 | Covered | T1,T2,T13 |
LINE 1029
EXPRESSION (tlram_req & tlram_we)
----1---- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 1162
EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 1405
SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
-----------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T20,T50,T51 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T20,T50,T51 |
LINE 1405
SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
-------------------1------------------- --------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T20,T50,T51 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T20,T50,T51 |
LINE 1434
EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
----------1--------- -------2------ --------3------- ------4------ -----------5-----------
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 0 | 1 | 0 | Covered | T10,T11,T12 |
0 | 0 | 1 | 0 | 0 | Covered | T4,T5,T6 |
0 | 1 | 0 | 0 | 0 | Covered | T10,T11,T12 |
1 | 0 | 0 | 0 | 0 | Not Covered | |
Toggle Coverage for Instance : tb.dut
| Total | Covered | Percent |
Totals |
64 |
64 |
100.00 |
Total Bits |
4160 |
4160 |
100.00 |
Total Bits 0->1 |
2080 |
2080 |
100.00 |
Total Bits 1->0 |
2080 |
2080 |
100.00 |
| | | |
Ports |
64 |
64 |
100.00 |
Port Bits |
4160 |
4160 |
100.00 |
Port Bits 0->1 |
2080 |
2080 |
100.00 |
Port Bits 1->0 |
2080 |
2080 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction | Exclude Annotation |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
rst_ni |
Yes |
Yes |
T28,T4,T45 |
Yes |
T1,T2,T3 |
INPUT |
|
rst_shadowed_ni |
Yes |
Yes |
T28,T4,T45 |
Yes |
T1,T2,T3 |
INPUT |
|
clk_edn_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
rst_edn_ni |
Yes |
Yes |
T28,T4,T45 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_i.d_ready |
Yes |
Yes |
T2,T52,T27 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
tl_o.d_error |
Yes |
Yes |
T28,T53,T54 |
Yes |
T28,T53,T54 |
OUTPUT |
|
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
alert_rx_i[0].ack_p |
Yes |
Yes |
T20,T50,T51 |
Yes |
T20,T50,T51 |
INPUT |
|
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
alert_rx_i[1].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
|
alert_rx_i[1].ack_p |
Yes |
Yes |
T20,T4,T50 |
Yes |
T20,T4,T50 |
INPUT |
|
alert_rx_i[1].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
alert_rx_i[1].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
|
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
alert_tx_o[0].alert_p |
Yes |
Yes |
T20,T50,T51 |
Yes |
T20,T50,T51 |
OUTPUT |
|
alert_tx_o[1].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
alert_tx_o[1].alert_p |
Yes |
Yes |
T20,T4,T50 |
Yes |
T20,T4,T50 |
OUTPUT |
|
keymgr_key_i.key[0][4:0] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][5] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][8:6] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][10:9] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][11] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][12] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][13] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][15:14] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][17:16] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][19:18] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][20] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][22:21] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][23] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][24] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][25] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][26] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][28:27] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][30:29] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][31] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][32] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][33] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][38:34] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][39] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][40] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][42:41] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][43] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][45:44] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][46] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][47] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][48] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][49] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][50] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][51] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][52] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][53] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][54] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][56:55] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][58:57] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][61:59] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][62] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][64:63] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][65] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][66] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][68:67] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][73:69] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][75:74] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][76] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][77] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][80:78] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][81] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][82] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][83] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][85:84] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][86] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][87] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][88] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][89] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][90] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][91] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][92] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][93] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][94] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][95] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][97:96] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][101:98] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][104:102] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][105] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][106] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][109:107] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][111:110] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][112] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][113] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][114] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][115] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][120:116] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][121] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][122] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][125:123] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][126] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][128:127] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][129] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][130] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][131] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][132] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][133] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][134] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][135] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][136] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][137] |
Yes |
Yes |
T2,T15,T16 |
Yes |
T2,T15,T16 |
INPUT |
keymgr_key_i.key[0][138] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][140:139] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][142:141] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][147:143] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][150:148] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][154:151] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][156:155] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][157] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][159:158] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][160] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][164:161] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][166:165] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][167] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][170:168] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][171] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][172] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][175:173] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][180:176] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][184:181] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][185] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][186] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][187] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][190:188] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][191] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][193:192] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][194] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][195] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][197:196] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][198] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][201:199] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][204:202] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][205] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][206] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][207] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][209:208] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][210] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][211] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][214:212] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][215] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][216] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][217] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][218] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][219] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][221:220] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][225:222] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][226] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][230:227] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][234:231] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][239:235] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][240] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][241] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][243:242] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][244] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][245] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][246] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][248:247] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][252:249] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][253] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][254] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[0][255] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][0] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][1] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][2] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][4:3] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][5] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][6] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][7] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][9:8] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][10] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][13:11] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][14] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][17:15] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][18] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][19] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][20] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][22:21] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][23] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][24] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][25] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][26] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][28:27] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][29] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][30] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][31] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][33:32] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][34] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][35] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][37:36] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][38] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][39] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][40] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][41] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][43:42] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][44] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][46:45] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][47] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][48] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][51:49] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][52] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][54:53] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][55] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][56] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][58:57] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][59] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][60] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][61] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][62] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][64:63] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][65] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][67:66] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][68] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][70:69] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][71] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][73:72] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][75:74] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][76] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][77] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][78] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][79] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][81:80] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][82] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][83] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][85:84] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][88:86] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][89] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][90] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][91] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][92] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][93] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][94] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][97:95] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][98] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][99] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][100] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][102:101] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][103] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][104] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][105] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][106] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][107] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][109:108] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][111:110] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][114:112] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][115] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][117:116] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][118] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][119] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][120] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][122:121] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][125:123] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][127:126] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][128] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][129] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][130] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][131] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][132] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][133] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][134] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][136:135] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][137] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][140:138] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][141] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][142] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][143] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][144] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][148:145] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][149] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][151:150] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][155:152] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][156] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][158:157] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][159] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][162:160] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][163] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][165:164] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][166] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][167] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][168] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][169] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][170] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][171] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][172] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][173] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][175:174] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][177:176] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][178] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][183:179] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][184] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][186:185] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][187] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][190:188] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][191] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][192] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][193] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][194] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][195] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][196] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][197] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][198] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][201:199] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][202] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][203] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][205:204] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][206] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][207] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][208] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][209] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][210] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][211] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][215:212] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][216] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][218:217] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][222:219] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][225:223] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][226] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][227] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][228] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][231:229] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][232] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][234:233] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][236:235] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][239:237] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][240] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][242:241] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][243] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][244] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][245] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][246] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][248:247] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][249] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][250] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][251] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][252] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][253] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][254] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.key[1][255] |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
keymgr_key_i.valid |
Yes |
Yes |
T1,T2,T15 |
Yes |
T1,T2,T15 |
INPUT |
|
app_i[0].last |
Yes |
Yes |
T1,T13,T16 |
Yes |
T1,T2,T13 |
INPUT |
|
app_i[0].strb[7:0] |
Yes |
Yes |
T27,T28,T25 |
Yes |
T27,T28,T25 |
INPUT |
|
app_i[0].data[63:0] |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
INPUT |
|
app_i[0].valid |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
INPUT |
|
app_i[1].last |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
INPUT |
|
app_i[1].strb[7:0] |
Yes |
Yes |
T27,T28,T25 |
Yes |
T27,T28,T25 |
INPUT |
|
app_i[1].data[63:0] |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
INPUT |
|
app_i[1].valid |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
INPUT |
|
app_i[2].last |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T2,T16 |
INPUT |
|
app_i[2].strb[7:0] |
Yes |
Yes |
T27,T25,T45 |
Yes |
T27,T25,T45 |
INPUT |
|
app_i[2].data[63:0] |
Yes |
Yes |
T1,T2,T16 |
Yes |
T1,T2,T16 |
INPUT |
|
app_i[2].valid |
Yes |
Yes |
T1,T2,T16 |
Yes |
T1,T2,T16 |
INPUT |
|
app_o[0].error |
Yes |
Yes |
T13,T18,T4 |
Yes |
T13,T18,T4 |
OUTPUT |
|
app_o[0].digest_share1[383:0] |
Excluded |
Excluded |
|
Excluded |
|
OUTPUT |
[UNSUPPORTED]: unmasked kmac share1 always output 0. |
app_o[0].digest_share0[383:0] |
Yes |
Yes |
T1,T16,T28 |
Yes |
T1,T16,T28 |
OUTPUT |
|
app_o[0].done |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
|
app_o[0].ready |
Yes |
Yes |
T1,T2,T13 |
Yes |
T1,T2,T13 |
OUTPUT |
|
app_o[1].error |
Yes |
Yes |
T22,T24,T55 |
Yes |
T22,T24,T55 |
OUTPUT |
|
app_o[1].digest_share1[383:0] |
Excluded |
Excluded |
|
Excluded |
|
OUTPUT |
[UNSUPPORTED]: unmasked kmac share1 always output 0. |
app_o[1].digest_share0[383:0] |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
OUTPUT |
|
app_o[1].done |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
OUTPUT |
|
app_o[1].ready |
Yes |
Yes |
T1,T16,T27 |
Yes |
T1,T16,T27 |
OUTPUT |
|
app_o[2].error |
Yes |
Yes |
T22,T24,T55 |
Yes |
T22,T24,T55 |
OUTPUT |
|
app_o[2].digest_share1[383:0] |
Excluded |
Excluded |
|
Excluded |
|
OUTPUT |
[UNSUPPORTED]: unmasked kmac share1 always output 0. |
app_o[2].digest_share0[383:0] |
Yes |
Yes |
T1,T16,T25 |
Yes |
T1,T16,T25 |
OUTPUT |
|
app_o[2].done |
Yes |
Yes |
T1,T2,T16 |
Yes |
T1,T2,T16 |
OUTPUT |
|
app_o[2].ready |
Yes |
Yes |
T1,T2,T16 |
Yes |
T1,T2,T16 |
OUTPUT |
|
entropy_o.edn_req[0:0] |
Excluded |
Excluded |
|
Excluded |
|
OUTPUT |
[UNSUPPORTED]: unmasked kmac does not use entropy. |
entropy_i.edn_bus[31:0] |
Excluded |
Excluded |
|
Excluded |
|
INPUT |
[UNSUPPORTED]: unmasked kmac does not use entropy. |
entropy_i.edn_fips[0:0] |
Excluded |
Excluded |
|
Excluded |
|
INPUT |
[UNSUPPORTED]: unmasked kmac does not use entropy. |
entropy_i.edn_ack[0:0] |
Excluded |
Excluded |
|
Excluded |
|
INPUT |
[UNSUPPORTED]: unmasked kmac does not use entropy. |
lc_escalate_en_i[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
|
intr_kmac_done_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
intr_fifo_empty_o |
Yes |
Yes |
T28,T39,T40 |
Yes |
T28,T39,T40 |
OUTPUT |
|
intr_kmac_err_o |
Yes |
Yes |
T2,T13,T18 |
Yes |
T2,T13,T18 |
OUTPUT |
|
en_masking_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
|
idle_o[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
|
*Tests covering at least one bit in the range
FSM Coverage for Instance : tb.dut
Summary for FSM :: kmac_st
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
13 |
13 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: kmac_st
states | Line No. | Covered | Tests |
KmacDigest |
817 |
Covered |
T1,T2,T3 |
KmacIdle |
785 |
Covered |
T1,T2,T3 |
KmacKeyBlock |
792 |
Covered |
T1,T2,T13 |
KmacMsgFeed |
782 |
Covered |
T1,T2,T3 |
KmacPrefix |
779 |
Covered |
T1,T2,T13 |
KmacTerminalError |
834 |
Covered |
T4,T5,T6 |
transitions | Line No. | Covered | Tests |
KmacDigest->KmacIdle |
826 |
Covered |
T1,T2,T3 |
KmacDigest->KmacTerminalError |
848 |
Covered |
T56 |
KmacIdle->KmacMsgFeed |
782 |
Covered |
T1,T2,T3 |
KmacIdle->KmacPrefix |
779 |
Covered |
T1,T2,T13 |
KmacIdle->KmacTerminalError |
848 |
Covered |
T5,T10,T11 |
KmacKeyBlock->KmacMsgFeed |
801 |
Covered |
T1,T2,T13 |
KmacKeyBlock->KmacTerminalError |
848 |
Covered |
T57 |
KmacMsgFeed->KmacDigest |
817 |
Covered |
T1,T2,T3 |
KmacMsgFeed->KmacIdle |
814 |
Covered |
T1,T2,T13 |
KmacMsgFeed->KmacTerminalError |
848 |
Covered |
T4,T6,T36 |
KmacPrefix->KmacKeyBlock |
792 |
Covered |
T1,T2,T13 |
KmacPrefix->KmacMsgFeed |
792 |
Covered |
T1,T2,T16 |
KmacPrefix->KmacTerminalError |
848 |
Covered |
T58,T7,T59 |
Branch Coverage for Instance : tb.dut
| Line No. | Total | Covered | Percent |
Branches |
|
65 |
61 |
93.85 |
TERNARY |
426 |
2 |
2 |
100.00 |
TERNARY |
635 |
4 |
4 |
100.00 |
TERNARY |
643 |
4 |
4 |
100.00 |
TERNARY |
648 |
2 |
2 |
100.00 |
CASE |
434 |
6 |
5 |
83.33 |
IF |
488 |
3 |
3 |
100.00 |
IF |
561 |
3 |
3 |
100.00 |
IF |
651 |
2 |
2 |
100.00 |
CASE |
689 |
6 |
4 |
66.67 |
IF |
765 |
2 |
2 |
100.00 |
CASE |
774 |
15 |
15 |
100.00 |
IF |
847 |
2 |
2 |
100.00 |
TERNARY |
1162 |
2 |
2 |
100.00 |
IF |
1423 |
4 |
3 |
75.00 |
IF |
1446 |
3 |
3 |
100.00 |
IF |
1475 |
3 |
3 |
100.00 |
IF |
1485 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 426 (cmd_update) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 635 (msgfifo_full) ?
-2-: 635 (msgfifo_empty_negedge) ?
-3-: 635 (msgfifo2kmac_process) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T28 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 643 (app_active) ?
-2-: 643 ((sha3_fsm != StAbsorb)) ?
-3-: 643 (msgfifo2kmac_process) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T13 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 648 (msgfifo_empty_gate) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T28,T39,T40 |
LineNo. Expression
-1-: 434 case (kmac_cmd)
Branches:
-1- | Status | Tests |
CmdStart |
Covered |
T1,T2,T3 |
CmdProcess |
Covered |
T1,T2,T3 |
CmdManualRun |
Covered |
T1,T2,T15 |
CmdDone |
Covered |
T1,T2,T3 |
CmdNone |
Covered |
T1,T2,T3 |
default |
Not Covered |
|
LineNo. Expression
-1-: 488 if ((!rst_ni))
-2-: 490 if (engine_stable)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 561 if ((!rst_ni))
-2-: 563 if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 651 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 689 case (1'b1)
Branches:
-1- | Status | Tests |
app_err.valid |
Covered |
T2,T13,T18 |
errchecker_err.valid |
Covered |
T2,T29,T49 |
sha3_err.valid |
Covered |
T22,T23,T24 |
entropy_err.valid |
Not Covered |
|
msgfifo_err.valid |
Not Covered |
|
default |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 765 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 774 case (kmac_st)
-2-: 776 if ((kmac_cmd == CmdStart))
-3-: 778 if ((CShake == app_sha3_mode))
-4-: 791 if (sha3_block_processed)
-5-: 792 (app_kmac_en) ?
-6-: 800 if (sha3_block_processed)
-7-: 809 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-: 815 if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-: 825 if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | Status | Tests |
KmacIdle |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
KmacIdle |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
KmacIdle |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
KmacPrefix |
- |
- |
1 |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
KmacPrefix |
- |
- |
1 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T16 |
KmacPrefix |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T13 |
KmacKeyBlock |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T13 |
KmacKeyBlock |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T13 |
KmacMsgFeed |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T1,T2,T13 |
KmacMsgFeed |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T1,T2,T3 |
KmacMsgFeed |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T2,T3 |
KmacDigest |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
KmacDigest |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
KmacTerminalError |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T11,T12 |
LineNo. Expression
-1-: 847 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 1162 (reg_state_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 1423 if ((!rst_ni))
-2-: 1425 if (alert_recov_operation)
-3-: 1427 if (err_processed)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T13,T18,T21 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 1446 if ((!rst_ni))
-2-: 1448 if (alert_fatal)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 1475 if ((!rst_ni))
-2-: 1477 if (alerts[1])
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 1485 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut
Assertion Details
AlertKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
CmdSparse_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
835203 |
0 |
0 |
T1 |
104075 |
167 |
0 |
0 |
T2 |
480157 |
359 |
0 |
0 |
T3 |
138038 |
993 |
0 |
0 |
T13 |
27237 |
5 |
0 |
0 |
T14 |
6351 |
29 |
0 |
0 |
T15 |
32419 |
105 |
0 |
0 |
T16 |
432502 |
770 |
0 |
0 |
T17 |
179260 |
1194 |
0 |
0 |
T18 |
120829 |
22 |
0 |
0 |
T19 |
0 |
88 |
0 |
0 |
T20 |
818 |
0 |
0 |
0 |
EnMaskingKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
EntropyReadyLatched_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
211980 |
0 |
0 |
T1 |
104075 |
38 |
0 |
0 |
T2 |
480157 |
56 |
0 |
0 |
T3 |
138038 |
299 |
0 |
0 |
T13 |
27237 |
4 |
0 |
0 |
T14 |
6351 |
9 |
0 |
0 |
T15 |
32419 |
13 |
0 |
0 |
T16 |
432502 |
155 |
0 |
0 |
T17 |
179260 |
364 |
0 |
0 |
T18 |
120829 |
20 |
0 |
0 |
T19 |
0 |
13 |
0 |
0 |
T20 |
818 |
0 |
0 |
0 |
EntrySizeRegSameToEntrySizePkg_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
952 |
952 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
ErrProcessedLatched_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
522 |
0 |
0 |
T13 |
27237 |
4 |
0 |
0 |
T14 |
6351 |
0 |
0 |
0 |
T15 |
32419 |
0 |
0 |
0 |
T16 |
432502 |
0 |
0 |
0 |
T17 |
179260 |
0 |
0 |
0 |
T18 |
120829 |
20 |
0 |
0 |
T19 |
29419 |
0 |
0 |
0 |
T20 |
818 |
0 |
0 |
0 |
T21 |
0 |
8 |
0 |
0 |
T27 |
91766 |
0 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T52 |
483707 |
0 |
0 |
0 |
T60 |
0 |
11 |
0 |
0 |
T61 |
0 |
17 |
0 |
0 |
T62 |
0 |
14 |
0 |
0 |
T63 |
0 |
6 |
0 |
0 |
T64 |
0 |
15 |
0 |
0 |
T65 |
0 |
10 |
0 |
0 |
FifoEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
FpvSecCmErrorCheckFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmKeccackFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmKeyIndexCountCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmKmacAppFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmKmacCoreFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmKmacFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmRoundCountCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmSHA3FsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmSHA3padFsmCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
FpvSecCmSentMsgCountCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
70 |
0 |
0 |
T10 |
306308 |
20 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T33 |
4907 |
0 |
0 |
0 |
T66 |
0 |
20 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
T68 |
679426 |
0 |
0 |
0 |
T69 |
901592 |
0 |
0 |
0 |
T70 |
110760 |
0 |
0 |
0 |
T71 |
191100 |
0 |
0 |
0 |
T72 |
50761 |
0 |
0 |
0 |
T73 |
245236 |
0 |
0 |
0 |
T74 |
818973 |
0 |
0 |
0 |
T75 |
1389 |
0 |
0 |
0 |
KmacCmd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
KmacDone_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
KmacErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
KmacStKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
NumAlerts2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
952 |
952 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
NumEntriesRegSameToNumEntriesPkg_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
952 |
952 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
PrefixRegSameToPrefixPkg_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
952 |
952 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
SecretKeyDivideBy32_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
952 |
952 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
Sha3AbsorbedPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
218580 |
0 |
0 |
T1 |
104075 |
38 |
0 |
0 |
T2 |
480157 |
52 |
0 |
0 |
T3 |
138038 |
310 |
0 |
0 |
T13 |
27237 |
4 |
0 |
0 |
T14 |
6351 |
9 |
0 |
0 |
T15 |
32419 |
13 |
0 |
0 |
T16 |
432502 |
155 |
0 |
0 |
T17 |
179260 |
374 |
0 |
0 |
T18 |
120829 |
20 |
0 |
0 |
T19 |
0 |
13 |
0 |
0 |
T20 |
818 |
0 |
0 |
0 |
TlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
TlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1477745179 |
1477591979 |
0 |
0 |
T1 |
104075 |
103996 |
0 |
0 |
T2 |
480157 |
480059 |
0 |
0 |
T3 |
138038 |
138032 |
0 |
0 |
T13 |
27237 |
27183 |
0 |
0 |
T14 |
6351 |
6279 |
0 |
0 |
T15 |
32419 |
32336 |
0 |
0 |
T16 |
432502 |
432419 |
0 |
0 |
T17 |
179260 |
179252 |
0 |
0 |
T18 |
120829 |
120773 |
0 |
0 |
T20 |
818 |
767 |
0 |
0 |