Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	204718630	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

165198816

1

T1

20549

T2

261117

T3

314101

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	195119116	1			T1	16260		T2	343631		T3	93393
values[0x0]	84035804	1			T1	3822		T2	156260		T3	121264
values[0x1]	90762526	1			T1	4056		T2	170806		T3	122270

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	159566404	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

210351042

1

T1

21454

T2

351653

T3

320084

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1077915	1			T1	53		T2	2430		T3	1306
valid_sources[0x01]	1068921	1			T1	58		T2	2593		T3	1317
valid_sources[0x02]	1115672	1			T1	76		T2	2439		T3	1311
valid_sources[0x03]	1173051	1			T1	33		T2	2587		T3	1279
valid_sources[0x04]	1909031	1			T1	53		T2	2668		T3	1295
valid_sources[0x05]	1924061	1			T1	72		T2	2473		T3	1376
valid_sources[0x06]	1076189	1			T1	105		T2	2512		T3	1310
valid_sources[0x07]	3487580	1			T1	68		T2	2614		T3	1252
valid_sources[0x08]	3134981	1			T1	104		T2	2299		T3	1304
valid_sources[0x09]	1073480	1			T1	69		T2	2849		T3	1299
valid_sources[0x0a]	1999718	1			T1	30		T2	2419		T3	1387
valid_sources[0x0b]	1443311	1			T1	58		T2	2621		T3	1270
valid_sources[0x0c]	1074710	1			T1	106		T2	2759		T3	1434
valid_sources[0x0d]	1080146	1			T1	170		T2	2742		T3	1255
valid_sources[0x0e]	1079329	1			T1	169		T2	2406		T3	1418
valid_sources[0x0f]	1740924	1			T1	156		T2	2581		T3	1258
valid_sources[0x10]	1077923	1			T1	124		T2	2597		T3	1350
valid_sources[0x11]	3147442	1			T1	61		T2	2702		T3	1248
valid_sources[0x12]	1073626	1			T1	156		T2	2519		T3	1293
valid_sources[0x13]	1072328	1			T1	69		T2	2754		T3	1403
valid_sources[0x14]	3165651	1			T1	110		T2	2609		T3	1275
valid_sources[0x15]	1079388	1			T1	126		T2	2382		T3	1222
valid_sources[0x16]	1721189	1			T1	35		T2	2718		T3	1303
valid_sources[0x17]	1074775	1			T1	2		T2	2650		T3	1319
valid_sources[0x18]	1071254	1			T1	99		T2	2737		T3	1341
valid_sources[0x19]	1749101	1			T1	121		T2	2482		T3	1363
valid_sources[0x1a]	1951635	1			T2	2855		T3	1296		T13	2468
valid_sources[0x1b]	1113755	1			T1	113		T2	3085		T3	1347
valid_sources[0x1c]	1080208	1			T1	47		T2	2454		T3	1294
valid_sources[0x1d]	1090818	1			T1	98		T2	2895		T3	1264
valid_sources[0x1e]	1077947	1			T1	133		T2	2413		T3	1358
valid_sources[0x1f]	1078227	1			T1	82		T2	2596		T3	1374
valid_sources[0x20]	1276682	1			T1	74		T2	2591		T3	1382
valid_sources[0x21]	1074392	1			T1	32		T2	2605		T3	1333
valid_sources[0x22]	1071195	1			T1	97		T2	2324		T3	1392
valid_sources[0x23]	3120610	1			T1	73		T2	2349		T3	1342
valid_sources[0x24]	1074376	1			T1	100		T2	2659		T3	1329
valid_sources[0x25]	1216194	1			T1	86		T2	2789		T3	1391
valid_sources[0x26]	1085407	1			T1	178		T2	2805		T3	1353
valid_sources[0x27]	1070153	1			T1	59		T2	2617		T3	1408
valid_sources[0x28]	1844356	1			T1	19		T2	2537		T3	1288
valid_sources[0x29]	1076520	1			T2	2887		T3	1373		T13	2517
valid_sources[0x2a]	3159166	1			T1	167		T2	2777		T3	1337
valid_sources[0x2b]	1073531	1			T1	60		T2	2649		T3	1314
valid_sources[0x2c]	1075453	1			T1	61		T2	2831		T3	1313
valid_sources[0x2d]	1291008	1			T1	16		T2	2580		T3	1322
valid_sources[0x2e]	1075956	1			T1	76		T2	2766		T3	1300
valid_sources[0x2f]	1083492	1			T1	83		T2	2779		T3	1285
valid_sources[0x30]	1142548	1			T1	56		T2	2523		T3	1342
valid_sources[0x31]	1074167	1			T1	75		T2	2645		T3	1434
valid_sources[0x32]	1539882	1			T1	161		T2	2454		T3	1297
valid_sources[0x33]	1205076	1			T1	194		T2	2316		T3	1373
valid_sources[0x34]	1069336	1			T1	47		T2	2675		T3	1330
valid_sources[0x35]	1075560	1			T1	60		T2	2463		T3	1350
valid_sources[0x36]	1080799	1			T1	91		T2	2739		T3	1236
valid_sources[0x37]	1747820	1			T1	61		T2	2855		T3	1311
valid_sources[0x38]	1072771	1			T1	34		T2	2670		T3	1290
valid_sources[0x39]	1074245	1			T1	247		T2	2517		T3	1365
valid_sources[0x3a]	1128711	1			T1	102		T2	2803		T3	1329
valid_sources[0x3b]	1072876	1			T1	62		T2	2637		T3	1282
valid_sources[0x3c]	1111051	1			T1	53		T2	2546		T3	1319
valid_sources[0x3d]	1204363	1			T1	131		T2	2718		T3	1214
valid_sources[0x3e]	1072005	1			T1	29		T2	2613		T3	1281
valid_sources[0x3f]	1561150	1			T1	89		T2	2792		T3	1292
valid_sources[0x40]	4141332	1			T1	78		T2	2787		T3	1322
valid_sources[0x41]	1073950	1			T1	1		T2	2980		T3	1286
valid_sources[0x42]	1082888	1			T1	46		T2	2793		T3	1278
valid_sources[0x43]	1139615	1			T1	73		T2	2447		T3	1276
valid_sources[0x44]	1731398	1			T1	31		T2	2813		T3	1316
valid_sources[0x45]	1111592	1			T1	63		T2	2487		T3	1297
valid_sources[0x46]	1070203	1			T1	200		T2	2558		T3	1344
valid_sources[0x47]	1138628	1			T1	52		T2	2478		T3	1272
valid_sources[0x48]	1744775	1			T1	86		T2	2676		T3	1338
valid_sources[0x49]	1981111	1			T1	81		T2	2361		T3	1371
valid_sources[0x4a]	1169711	1			T1	61		T2	2523		T3	1263
valid_sources[0x4b]	1071150	1			T1	39		T2	2549		T3	1349
valid_sources[0x4c]	1078009	1			T1	63		T2	2812		T3	1349
valid_sources[0x4d]	1073157	1			T1	82		T2	2497		T3	1292
valid_sources[0x4e]	1245974	1			T1	208		T2	2677		T3	1315
valid_sources[0x4f]	1083286	1			T1	76		T2	2822		T3	1241
valid_sources[0x50]	1077219	1			T1	99		T2	2482		T3	1343
valid_sources[0x51]	2010189	1			T1	113		T2	2628		T3	1299
valid_sources[0x52]	1075831	1			T1	254		T2	2641		T3	1329
valid_sources[0x53]	1070650	1			T1	26		T2	2560		T3	1305
valid_sources[0x54]	1079732	1			T1	177		T2	2426		T3	1304
valid_sources[0x55]	1081842	1			T1	188		T2	3045		T3	1404
valid_sources[0x56]	1079297	1			T1	70		T2	2762		T3	1274
valid_sources[0x57]	1738504	1			T1	28		T2	2489		T3	1326
valid_sources[0x58]	1070390	1			T1	64		T2	2562		T3	1300
valid_sources[0x59]	2004088	1			T1	11		T2	2572		T3	1312
valid_sources[0x5a]	1068825	1			T1	79		T2	2462		T3	1341
valid_sources[0x5b]	1105520	1			T1	128		T2	2791		T3	1270
valid_sources[0x5c]	1071050	1			T1	6		T2	2625		T3	1305
valid_sources[0x5d]	1072931	1			T1	231		T2	2593		T3	1304
valid_sources[0x5e]	1618086	1			T1	170		T2	2572		T3	1247
valid_sources[0x5f]	2063340	1			T1	115		T2	2544		T3	1265
valid_sources[0x60]	1073097	1			T1	207		T2	2738		T3	1376
valid_sources[0x61]	1079270	1			T1	126		T2	2710		T3	1357
valid_sources[0x62]	2027344	1			T1	98		T2	2986		T3	1369
valid_sources[0x63]	1097336	1			T1	127		T2	2406		T3	1312
valid_sources[0x64]	1091270	1			T1	58		T2	2626		T3	1313
valid_sources[0x65]	1072523	1			T1	142		T2	2686		T3	1358
valid_sources[0x66]	1966756	1			T1	164		T2	2556		T3	1261
valid_sources[0x67]	1181903	1			T1	178		T2	2631		T3	1335
valid_sources[0x68]	2105754	1			T1	52		T2	2645		T3	1314
valid_sources[0x69]	2152459	1			T1	31		T2	2442		T3	1378
valid_sources[0x6a]	1073190	1			T1	57		T2	2579		T3	1304
valid_sources[0x6b]	1515407	1			T1	193		T2	2538		T3	1192
valid_sources[0x6c]	1190893	1			T1	69		T2	2570		T3	1286
valid_sources[0x6d]	4920587	1			T1	68		T2	2593		T3	1216
valid_sources[0x6e]	1116977	1			T1	136		T2	2402		T3	1312
valid_sources[0x6f]	1189359	1			T1	65		T2	2486		T3	1348
valid_sources[0x70]	1131259	1			T1	63		T2	2457		T3	1369
valid_sources[0x71]	1097222	1			T1	168		T2	2431		T3	1332
valid_sources[0x72]	1069172	1			T1	18		T2	2503		T3	1262
valid_sources[0x73]	1547586	1			T1	95		T2	2886		T3	1247
valid_sources[0x74]	1130204	1			T1	14		T2	2738		T3	1361
valid_sources[0x75]	1077977	1			T1	197		T2	2786		T3	1312
valid_sources[0x76]	2349919	1			T1	92		T2	2721		T3	1354
valid_sources[0x77]	1993484	1			T1	199		T2	2645		T3	1364
valid_sources[0x78]	1076156	1			T1	204		T2	2552		T3	1301
valid_sources[0x79]	1077378	1			T1	168		T2	2587		T3	1271
valid_sources[0x7a]	1096261	1			T1	201		T2	2495		T3	1313
valid_sources[0x7b]	1077657	1			T1	89		T2	2596		T3	1382
valid_sources[0x7c]	1071529	1			T1	16		T2	2775		T3	1388
valid_sources[0x7d]	1154482	1			T1	158		T2	2783		T3	1268
valid_sources[0x7e]	1070863	1			T1	27		T2	2656		T3	1273
valid_sources[0x7f]	1074536	1			T1	91		T2	2713		T3	1283
valid_sources[0x80]	1076387	1			T1	179		T2	2637		T3	1215

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72146581

1

T1

14261

T2

100460

T3

74135

values[0x0]

all_enables

biggest_size

49962873

1

T1

3099

T2

87400

T3

119730

values[0x1]

all_enables

biggest_size

43089362

1

T1

3189

T2

73257

T3

120236