Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

206046393

1

T1

3589

T2

409580

T3

22826

full_word

165281917

1

T1

20549

T2

261117

T3

314101

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	371328050	1			T1	24138		T2	670697		T3	336927
auto[TlIntgErrCmd]	81	1			T121	6		T122	2		T123	5
auto[TlIntgErrData]	85	1			T121	6		T122	5		T123	5
auto[TlIntgErrBoth]	94	1			T121	8		T122	3		T123	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

195430991

1

T1

16260

T2

343631

T3

93393

auto[1]

175897319

1

T1

7878

T2

327066

T3

243534

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	123260441	1			T1	1999		T2	243171		T3	19258
auto[TlIntgErrNone]	partial	auto[1]	82785710	1			T1	1590		T2	166409		T3	3568
auto[TlIntgErrNone]	full_word	auto[0]	72170435	1			T1	14261		T2	100460		T3	74135
auto[TlIntgErrNone]	full_word	auto[1]	93111464	1			T1	6288		T2	160657		T3	239966
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T121	2		T122	1		T123	2
auto[TlIntgErrCmd]	partial	auto[1]	36	1			T121	4		T122	1		T123	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T176	1		T177	1		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T179	1		T180	1		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1			T121	1		T122	4		T123	1
auto[TlIntgErrData]	partial	auto[1]	37	1			T121	5		T122	1		T123	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T123	1		T181	1		T182	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T123	1		T183	2		T180	2
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T121	2		T122	2		T123	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T121	5		T123	8		T181	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T121	1		T122	1		T184	1