Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2064132544	234545	0	0
entropy_period_rd_A	2064132544	1923	0	0
intr_enable_rd_A	2064132544	2419	0	0
prefix_0_rd_A	2064132544	1749	0	0
prefix_10_rd_A	2064132544	1864	0	0
prefix_1_rd_A	2064132544	1866	0	0
prefix_2_rd_A	2064132544	1915	0	0
prefix_3_rd_A	2064132544	1887	0	0
prefix_4_rd_A	2064132544	1924	0	0
prefix_5_rd_A	2064132544	1908	0	0
prefix_6_rd_A	2064132544	1961	0	0
prefix_7_rd_A	2064132544	1948	0	0
prefix_8_rd_A	2064132544	1952	0	0
prefix_9_rd_A	2064132544	1837	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	234545	0	0
T36	797891	113707	0	0
T37	0	22194	0	0
T56	0	95645	0	0
T121	0	3	0	0
T123	0	5	0	0
T127	0	34	0	0
T128	0	5	0	0
T129	0	6	0	0
T130	0	3	0	0
T131	0	220	0	0
T132	35038	0	0	0
T133	625847	0	0	0
T134	764782	0	0	0
T135	189340	0	0	0
T136	1469	0	0	0
T137	708606	0	0	0
T138	395595	0	0	0
T139	955535	0	0	0
T140	90001	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1923	0	0
T37	558000	58	0	0
T99	0	35	0	0
T100	0	14	0	0
T101	0	59	0	0
T104	0	14	0	0
T128	0	28	0	0
T149	0	14	0	0
T150	0	25	0	0
T151	0	34	0	0
T152	0	4	0	0
T153	424815	0	0	0
T154	125859	0	0	0
T155	2307	0	0	0
T156	25730	0	0	0
T157	1602	0	0	0
T158	1773	0	0	0
T159	993741	0	0	0
T160	66462	0	0	0
T161	679141	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	2419	0	0
T37	558000	78	0	0
T99	0	46	0	0
T100	0	15	0	0
T101	0	101	0	0
T128	0	20	0	0
T149	0	3	0	0
T153	424815	0	0	0
T154	125859	0	0	0
T155	2307	0	0	0
T156	25730	0	0	0
T157	1602	0	0	0
T158	1773	0	0	0
T159	993741	0	0	0
T160	66462	0	0	0
T161	679141	0	0	0
T162	0	29	0	0
T163	0	18	0	0
T164	0	14	0	0
T165	0	4	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1749	0	0
T37	558000	46	0	0
T99	0	26	0	0
T100	0	6	0	0
T101	0	58	0	0
T104	0	1	0	0
T128	0	14	0	0
T149	0	10	0	0
T150	0	12	0	0
T153	424815	0	0	0
T154	125859	0	0	0
T155	2307	0	0	0
T156	25730	0	0	0
T157	1602	0	0	0
T158	1773	0	0	0
T159	993741	0	0	0
T160	66462	0	0	0
T161	679141	0	0	0
T163	0	32	0	0
T165	0	10	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1864	0	0
T37	558000	60	0	0
T99	0	23	0	0
T100	0	10	0	0
T101	0	69	0	0
T104	0	10	0	0
T128	0	13	0	0
T149	0	23	0	0
T150	0	25	0	0
T153	424815	0	0	0
T154	125859	0	0	0
T155	2307	0	0	0
T156	25730	0	0	0
T157	1602	0	0	0
T158	1773	0	0	0
T159	993741	0	0	0
T160	66462	0	0	0
T161	679141	0	0	0
T163	0	1	0	0
T165	0	16	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1866	0	0
T37	558000	47	0	0
T99	0	27	0	0
T100	0	5	0	0
T101	0	63	0	0
T104	0	2	0	0
T128	0	18	0	0
T150	0	14	0	0
T151	0	53	0	0
T152	0	26	0	0
T153	424815	0	0	0
T154	125859	0	0	0
T155	2307	0	0	0
T156	25730	0	0	0
T157	1602	0	0	0
T158	1773	0	0	0
T159	993741	0	0	0
T160	66462	0	0	0
T161	679141	0	0	0
T163	0	26	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1915	0	0
T37	558000	54	0	0
T99	0	31	0	0
T100	0	9	0	0
T101	0	46	0	0
T104	0	2	0	0
T128	0	23	0	0
T149	0	29	0	0
T150	0	18	0	0
T153	424815	0	0	0
T154	125859	0	0	0
T155	2307	0	0	0
T156	25730	0	0	0
T157	1602	0	0	0
T158	1773	0	0	0
T159	993741	0	0	0
T160	66462	0	0	0
T161	679141	0	0	0
T163	0	33	0	0
T165	0	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1887	0	0
T37	558000	105	0	0
T99	0	34	0	0
T100	0	10	0	0
T101	0	87	0	0
T104	0	10	0	0
T128	0	19	0	0
T149	0	22	0	0
T150	0	18	0	0
T153	424815	0	0	0
T154	125859	0	0	0
T155	2307	0	0	0
T156	25730	0	0	0
T157	1602	0	0	0
T158	1773	0	0	0
T159	993741	0	0	0
T160	66462	0	0	0
T161	679141	0	0	0
T163	0	24	0	0
T165	0	13	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1924	0	0
T37	558000	51	0	0
T99	0	25	0	0
T100	0	9	0	0
T101	0	44	0	0
T128	0	19	0	0
T149	0	12	0	0
T150	0	6	0	0
T151	0	90	0	0
T153	424815	0	0	0
T154	125859	0	0	0
T155	2307	0	0	0
T156	25730	0	0	0
T157	1602	0	0	0
T158	1773	0	0	0
T159	993741	0	0	0
T160	66462	0	0	0
T161	679141	0	0	0
T163	0	30	0	0
T165	0	15	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1908	0	0
T37	558000	64	0	0
T99	0	31	0	0
T100	0	10	0	0
T101	0	53	0	0
T104	0	8	0	0
T128	0	18	0	0
T149	0	3	0	0
T150	0	13	0	0
T153	424815	0	0	0
T154	125859	0	0	0
T155	2307	0	0	0
T156	25730	0	0	0
T157	1602	0	0	0
T158	1773	0	0	0
T159	993741	0	0	0
T160	66462	0	0	0
T161	679141	0	0	0
T163	0	10	0	0
T165	0	11	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1961	0	0
T37	558000	77	0	0
T99	0	36	0	0
T100	0	10	0	0
T101	0	61	0	0
T128	0	14	0	0
T149	0	32	0	0
T150	0	16	0	0
T151	0	32	0	0
T153	424815	0	0	0
T154	125859	0	0	0
T155	2307	0	0	0
T156	25730	0	0	0
T157	1602	0	0	0
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T160	66462	0	0	0
T161	679141	0	0	0
T163	0	36	0	0
T165	0	26	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1948	0	0
T37	558000	82	0	0
T99	0	21	0	0
T100	0	16	0	0
T101	0	57	0	0
T104	0	1	0	0
T128	0	18	0	0
T149	0	9	0	0
T150	0	11	0	0
T153	424815	0	0	0
T154	125859	0	0	0
T155	2307	0	0	0
T156	25730	0	0	0
T157	1602	0	0	0
T158	1773	0	0	0
T159	993741	0	0	0
T160	66462	0	0	0
T161	679141	0	0	0
T163	0	18	0	0
T165	0	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1952	0	0
T37	558000	58	0	0
T99	0	34	0	0
T100	0	10	0	0
T101	0	59	0	0
T104	0	6	0	0
T128	0	16	0	0
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T150	0	5	0	0
T153	424815	0	0	0
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T160	66462	0	0	0
T161	679141	0	0	0
T163	0	29	0	0
T165	0	11	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064132544	1837	0	0
T37	558000	64	0	0
T99	0	28	0	0
T100	0	12	0	0
T101	0	58	0	0
T104	0	1	0	0
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T158	1773	0	0	0
T159	993741	0	0	0
T160	66462	0	0	0
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T163	0	23	0	0