Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

207225931

1

T1

665

T2

861

T3

43124

full_word

167531247

1

T1

1419

T2

1425

T3

73087

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	374756868	1			T1	2084		T2	2286		T3	116211
auto[TlIntgErrCmd]	115	1			T118	10		T119	5		T120	12
auto[TlIntgErrData]	110	1			T118	6		T119	3		T120	3
auto[TlIntgErrBoth]	85	1			T118	4		T119	2		T120	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197287910

1

T1

1087

T2

1187

T3

78588

auto[1]

177469268

1

T1

997

T2

1099

T3

37623

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	124388239	1			T1	383		T2	469		T3	25998
auto[TlIntgErrNone]	partial	auto[1]	82837406	1			T1	282		T2	392		T3	17126
auto[TlIntgErrNone]	full_word	auto[0]	72899534	1			T1	704		T2	718		T3	52590
auto[TlIntgErrNone]	full_word	auto[1]	94631689	1			T1	715		T2	707		T3	20497
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T118	7		T119	4		T120	6
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T118	3		T119	1		T120	6
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T177	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T147	1		T149	2		T179	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T118	3		T125	3		T132	6
auto[TlIntgErrData]	partial	auto[1]	57	1			T118	2		T119	3		T120	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T118	1		T149	1		T180	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T120	1		T125	1		T149	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T118	2		T119	2		T120	3
auto[TlIntgErrBoth]	partial	auto[1]	40	1			T118	2		T120	2		T132	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T180	1		T177	1		T175	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T149	1		T181	1		-	-