Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2038142355	86784	0	0
entropy_period_rd_A	2038142355	1945	0	0
intr_enable_rd_A	2038142355	2737	0	0
prefix_0_rd_A	2038142355	1914	0	0
prefix_10_rd_A	2038142355	1739	0	0
prefix_1_rd_A	2038142355	1927	0	0
prefix_2_rd_A	2038142355	1901	0	0
prefix_3_rd_A	2038142355	1852	0	0
prefix_4_rd_A	2038142355	1907	0	0
prefix_5_rd_A	2038142355	1894	0	0
prefix_6_rd_A	2038142355	1854	0	0
prefix_7_rd_A	2038142355	1872	0	0
prefix_8_rd_A	2038142355	1794	0	0
prefix_9_rd_A	2038142355	1851	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	86784	0	0
T61	648668	57887	0	0
T62	0	25479	0	0
T63	0	175	0	0
T118	0	1	0	0
T119	0	4	0	0
T120	0	3	0	0
T121	0	120	0	0
T126	0	145	0	0
T128	0	266	0	0
T130	0	41	0	0
T133	266254	0	0	0
T134	527755	0	0	0
T135	26202	0	0	0
T136	468371	0	0	0
T137	16336	0	0	0
T138	893668	0	0	0
T139	510361	0	0	0
T140	104571	0	0	0
T141	106190	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1945	0	0
T99	4438	3	0	0
T100	11968	53	0	0
T115	4591	22	0	0
T118	22947	155	0	0
T119	11265	29	0	0
T120	23914	123	0	0
T146	24580	232	0	0
T147	23926	117	0	0
T148	6346	24	0	0
T149	24648	129	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	2737	0	0
T99	4438	7	0	0
T100	11968	74	0	0
T115	4591	6	0	0
T118	22947	132	0	0
T119	11265	44	0	0
T120	23914	142	0	0
T146	24580	205	0	0
T150	911	13	0	0
T151	1086	26	0	0
T152	1558	22	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1914	0	0
T99	4438	11	0	0
T100	11968	57	0	0
T115	4591	14	0	0
T118	22947	71	0	0
T119	11265	10	0	0
T120	23914	72	0	0
T146	24580	245	0	0
T147	23926	95	0	0
T148	6346	33	0	0
T153	1705	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1739	0	0
T99	4438	4	0	0
T100	11968	48	0	0
T115	4591	7	0	0
T118	22947	91	0	0
T119	11265	21	0	0
T120	23914	85	0	0
T146	24580	202	0	0
T147	23926	91	0	0
T148	6346	20	0	0
T149	24648	76	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1927	0	0
T99	4438	2	0	0
T100	11968	70	0	0
T115	4591	12	0	0
T118	22947	90	0	0
T119	11265	18	0	0
T120	23914	92	0	0
T146	24580	241	0	0
T147	23926	72	0	0
T148	6346	12	0	0
T154	2191	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1901	0	0
T99	4438	3	0	0
T100	11968	54	0	0
T115	4591	13	0	0
T118	22947	97	0	0
T119	11265	19	0	0
T120	23914	89	0	0
T146	24580	213	0	0
T147	23926	94	0	0
T148	6346	5	0	0
T154	2191	5	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1852	0	0
T99	4438	13	0	0
T100	11968	63	0	0
T115	4591	11	0	0
T118	22947	95	0	0
T119	11265	35	0	0
T120	23914	83	0	0
T146	24580	208	0	0
T147	23926	64	0	0
T148	6346	5	0	0
T154	2191	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1907	0	0
T99	4438	6	0	0
T100	11968	40	0	0
T115	4591	11	0	0
T118	22947	71	0	0
T119	11265	29	0	0
T120	23914	98	0	0
T146	24580	193	0	0
T147	23926	80	0	0
T148	6346	33	0	0
T153	1705	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1894	0	0
T99	4438	3	0	0
T100	11968	56	0	0
T115	4591	15	0	0
T118	22947	84	0	0
T119	11265	13	0	0
T120	23914	84	0	0
T146	24580	218	0	0
T147	23926	90	0	0
T148	6346	18	0	0
T153	1705	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1854	0	0
T99	4438	16	0	0
T100	11968	61	0	0
T115	4591	17	0	0
T118	22947	77	0	0
T119	11265	23	0	0
T120	23914	90	0	0
T146	24580	186	0	0
T147	23926	96	0	0
T148	6346	4	0	0
T153	1705	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1872	0	0
T99	4438	7	0	0
T100	11968	47	0	0
T115	4591	10	0	0
T118	22947	88	0	0
T119	11265	18	0	0
T120	23914	96	0	0
T146	24580	204	0	0
T147	23926	62	0	0
T148	6346	19	0	0
T154	2191	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1794	0	0
T99	4438	9	0	0
T100	11968	66	0	0
T115	4591	9	0	0
T118	22947	84	0	0
T119	11265	14	0	0
T120	23914	73	0	0
T146	24580	238	0	0
T147	23926	92	0	0
T148	6346	1	0	0
T154	2191	9	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2038142355	1851	0	0
T99	4438	14	0	0
T100	11968	51	0	0
T115	4591	5	0	0
T118	22947	100	0	0
T119	11265	9	0	0
T120	23914	83	0	0
T146	24580	244	0	0
T147	23926	68	0	0
T148	6346	4	0	0
T153	1705	5	0	0