Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41389767	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

50088398

1

T1

675241

T2

9

T3

419

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49517011	1			T1	770798		T2	1		T3	233
values[0x0]	20331376	1			T1	315172		T2	15		T3	204
values[0x1]	21629778	1			T1	339111		T2	16		T3	216

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32128162	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

59350003

1

T1

842628

T2

9

T3

503

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	281212	1			T1	778		T3	1		T4	14
valid_sources[0x01]	591601	1			T1	962		T4	20		T14	40
valid_sources[0x02]	286576	1			T1	789		T3	1		T4	23
valid_sources[0x03]	286544	1			T1	801		T3	1		T4	34
valid_sources[0x04]	283275	1			T1	797		T3	2		T4	40
valid_sources[0x05]	282838	1			T1	779		T3	5		T4	55
valid_sources[0x06]	962225	1			T1	864		T3	5		T4	35
valid_sources[0x07]	282874	1			T1	781		T4	22		T14	76
valid_sources[0x08]	1240502	1			T1	843		T4	19		T5	1
valid_sources[0x09]	400021	1			T1	815		T2	2		T3	3
valid_sources[0x0a]	283998	1			T1	715		T3	8		T4	42
valid_sources[0x0b]	396585	1			T1	786		T3	1		T4	19
valid_sources[0x0c]	284334	1			T1	842		T3	1		T4	43
valid_sources[0x0d]	283947	1			T1	827		T3	1		T4	62
valid_sources[0x0e]	286637	1			T1	789		T3	1		T4	21
valid_sources[0x0f]	288728	1			T1	761		T4	46		T14	87
valid_sources[0x10]	281598	1			T1	853		T3	5		T4	21
valid_sources[0x11]	288592	1			T1	816		T2	2		T3	1
valid_sources[0x12]	449783	1			T1	752		T3	2		T4	19
valid_sources[0x13]	285682	1			T1	823		T3	1		T4	28
valid_sources[0x14]	1020268	1			T1	845		T3	6		T4	13
valid_sources[0x15]	392179	1			T1	936		T3	5		T4	67
valid_sources[0x16]	483588	1			T1	819		T3	4		T4	20
valid_sources[0x17]	283222	1			T1	846		T3	1		T4	42
valid_sources[0x18]	283174	1			T1	802		T3	2		T4	39
valid_sources[0x19]	281096	1			T1	741		T3	1		T4	33
valid_sources[0x1a]	282064	1			T1	786		T3	2		T4	31
valid_sources[0x1b]	283037	1			T1	831		T3	7		T4	34
valid_sources[0x1c]	294435	1			T1	807		T3	5		T4	31
valid_sources[0x1d]	284149	1			T1	856		T3	1		T4	32
valid_sources[0x1e]	312033	1			T1	840		T3	1		T4	36
valid_sources[0x1f]	293805	1			T1	744		T3	2		T4	25
valid_sources[0x20]	281470	1			T1	1565		T3	5		T4	36
valid_sources[0x21]	455316	1			T1	752		T3	1		T4	20
valid_sources[0x22]	316538	1			T1	749		T3	5		T4	37
valid_sources[0x23]	281358	1			T1	810		T3	5		T4	23
valid_sources[0x24]	286265	1			T1	793		T4	37		T5	2
valid_sources[0x25]	284507	1			T1	809		T4	12		T14	60
valid_sources[0x26]	282465	1			T1	807		T4	38		T14	90
valid_sources[0x27]	285074	1			T1	878		T4	12		T14	70
valid_sources[0x28]	336156	1			T1	829		T3	2		T4	31
valid_sources[0x29]	283582	1			T1	843		T3	5		T4	21
valid_sources[0x2a]	283127	1			T1	910		T3	2		T4	11
valid_sources[0x2b]	286374	1			T1	744		T3	2		T4	18
valid_sources[0x2c]	465750	1			T1	828		T3	2		T4	21
valid_sources[0x2d]	299864	1			T1	783		T3	8		T4	19
valid_sources[0x2e]	282631	1			T1	897		T3	1		T4	17
valid_sources[0x2f]	308838	1			T1	798		T3	5		T4	18
valid_sources[0x30]	284041	1			T1	845		T3	6		T4	28
valid_sources[0x31]	292945	1			T1	825		T3	4		T4	27
valid_sources[0x32]	1454418	1			T1	115752		T3	6		T4	31
valid_sources[0x33]	409096	1			T1	842		T3	3		T4	12
valid_sources[0x34]	421802	1			T1	729		T3	1		T4	21
valid_sources[0x35]	285513	1			T1	843		T2	1		T3	4
valid_sources[0x36]	300272	1			T1	1238		T3	5		T4	38
valid_sources[0x37]	281752	1			T1	766		T3	2		T4	11
valid_sources[0x38]	311183	1			T1	831		T3	3		T4	31
valid_sources[0x39]	283781	1			T1	802		T3	4		T4	51
valid_sources[0x3a]	766177	1			T1	833		T3	2		T4	20
valid_sources[0x3b]	283851	1			T1	884		T4	26		T5	2
valid_sources[0x3c]	284072	1			T1	1380		T3	6		T4	17
valid_sources[0x3d]	281907	1			T1	782		T4	25		T14	45
valid_sources[0x3e]	283526	1			T1	919		T4	33		T14	31
valid_sources[0x3f]	285611	1			T1	759		T3	4		T4	37
valid_sources[0x40]	428706	1			T1	879		T3	3		T4	31
valid_sources[0x41]	282242	1			T1	885		T3	3		T4	34
valid_sources[0x42]	279990	1			T1	862		T3	2		T4	17
valid_sources[0x43]	289458	1			T1	846		T3	3		T4	18
valid_sources[0x44]	281706	1			T1	859		T3	3		T4	35
valid_sources[0x45]	348007	1			T1	804		T3	7		T4	41
valid_sources[0x46]	311019	1			T1	816		T4	22		T5	3
valid_sources[0x47]	282654	1			T1	847		T2	6		T3	6
valid_sources[0x48]	282795	1			T1	836		T3	1		T4	40
valid_sources[0x49]	287661	1			T1	1372		T3	5		T4	26
valid_sources[0x4a]	403761	1			T1	912		T4	23		T5	2
valid_sources[0x4b]	282280	1			T1	758		T3	2		T4	26
valid_sources[0x4c]	285094	1			T1	862		T4	13		T5	3
valid_sources[0x4d]	282766	1			T1	946		T4	27		T5	1
valid_sources[0x4e]	1173235	1			T1	1685		T2	3		T3	4
valid_sources[0x4f]	282307	1			T1	1440		T3	3		T4	9
valid_sources[0x50]	305913	1			T1	1648		T3	4		T4	27
valid_sources[0x51]	286072	1			T1	780		T3	1		T4	33
valid_sources[0x52]	283433	1			T1	852		T3	3		T4	13
valid_sources[0x53]	282631	1			T1	1693		T3	1		T4	21
valid_sources[0x54]	290241	1			T1	1600		T3	1		T4	18
valid_sources[0x55]	295351	1			T1	806		T4	31		T14	45
valid_sources[0x56]	291343	1			T1	757		T3	1		T4	38
valid_sources[0x57]	283892	1			T1	785		T4	18		T14	53
valid_sources[0x58]	283610	1			T1	1360		T4	15		T5	2
valid_sources[0x59]	280883	1			T1	865		T4	23		T5	1
valid_sources[0x5a]	300325	1			T1	882		T4	36		T14	59
valid_sources[0x5b]	281400	1			T1	870		T3	1		T4	14
valid_sources[0x5c]	281675	1			T1	871		T3	4		T4	36
valid_sources[0x5d]	431954	1			T1	858		T3	1		T4	20
valid_sources[0x5e]	285608	1			T1	2309		T3	2		T4	15
valid_sources[0x5f]	284006	1			T1	815		T3	2		T4	21
valid_sources[0x60]	283573	1			T1	808		T3	3		T4	45
valid_sources[0x61]	307964	1			T1	856		T3	2		T4	33
valid_sources[0x62]	283936	1			T1	842		T3	7		T4	15
valid_sources[0x63]	304918	1			T1	874		T2	3		T3	4
valid_sources[0x64]	283152	1			T1	816		T3	4		T4	11
valid_sources[0x65]	283936	1			T1	772		T4	24		T5	1
valid_sources[0x66]	282019	1			T1	732		T4	19		T5	1
valid_sources[0x67]	285804	1			T1	806		T4	34		T5	2
valid_sources[0x68]	283934	1			T1	904		T3	1		T4	9
valid_sources[0x69]	304182	1			T1	745		T3	1		T4	21
valid_sources[0x6a]	283575	1			T1	833		T3	4		T4	38
valid_sources[0x6b]	311371	1			T1	779		T3	2		T4	33
valid_sources[0x6c]	284298	1			T1	867		T2	2		T3	1
valid_sources[0x6d]	283493	1			T1	902		T4	18		T5	1
valid_sources[0x6e]	286287	1			T1	1388		T4	15		T5	1
valid_sources[0x6f]	290532	1			T1	776		T3	1		T4	12
valid_sources[0x70]	284595	1			T1	778		T3	4		T4	12
valid_sources[0x71]	283572	1			T1	1177		T3	7		T4	21
valid_sources[0x72]	285403	1			T1	879		T3	8		T4	26
valid_sources[0x73]	281464	1			T1	827		T4	14		T14	38
valid_sources[0x74]	286064	1			T1	782		T3	5		T4	30
valid_sources[0x75]	286669	1			T1	838		T3	4		T4	27
valid_sources[0x76]	283623	1			T1	739		T3	3		T4	18
valid_sources[0x77]	433839	1			T1	752		T3	2		T4	23
valid_sources[0x78]	282594	1			T1	861		T3	4		T4	14
valid_sources[0x79]	282360	1			T1	848		T3	2		T4	11
valid_sources[0x7a]	281977	1			T1	725		T3	2		T4	11
valid_sources[0x7b]	288835	1			T1	977		T4	23		T5	1
valid_sources[0x7c]	283396	1			T1	846		T3	7		T4	17
valid_sources[0x7d]	288026	1			T1	888		T3	2		T4	44
valid_sources[0x7e]	286562	1			T1	1588		T3	3		T4	29
valid_sources[0x7f]	284398	1			T1	868		T3	1		T4	42
valid_sources[0x80]	296050	1			T1	761		T3	6		T4	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24037443

1

T1

309953

T2

1

T3

21

values[0x0]

all_enables

biggest_size

13689509

1

T1

194540

T2

5

T3

194

values[0x1]

all_enables

biggest_size

12361446

1

T1

170748

T2

3

T3

204