Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

41407355

1

T1

749840

T2

23

T3

234

full_word

50089444

1

T1

675241

T2

9

T3

419

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	91496489	1			T1	142508		T2	32		T3	653
auto[TlIntgErrCmd]	100	1			T46	6		T47	4		T116	9
auto[TlIntgErrData]	110	1			T46	9		T47	5		T116	8
auto[TlIntgErrBoth]	100	1			T46	5		T47	11		T116	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49521759

1

T1

770798

T2

1

T3

233

auto[1]

41975040

1

T1

654283

T2

31

T3

420

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25483871	1			T1	460845		T3	212		T4	1704
auto[TlIntgErrNone]	partial	auto[1]	15923198	1			T1	288995		T2	23		T3	22
auto[TlIntgErrNone]	full_word	auto[0]	24037737	1			T1	309953		T2	1		T3	21
auto[TlIntgErrNone]	full_word	auto[1]	26051683	1			T1	365288		T2	8		T3	398
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T46	3		T47	1		T116	6
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T46	2		T47	2		T116	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T46	1		T47	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T135	1		T137	2		T129	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T46	6		T47	1		T116	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T46	3		T47	4		T116	6
auto[TlIntgErrData]	full_word	auto[0]	4	1			T116	1		T138	1		T136	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T181	2		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T46	2		T47	3		T178	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T46	3		T47	5		T116	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T47	1		T138	1		T182	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T47	2		T137	1		T183	1