Unified Coverage Report :: Module :: kmac_core

Module : kmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.80	100.00	100.00		100.00	94.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core	98.80	100.00	100.00		100.00	94.00	100.00

---

Module Instance : tb.dut.u_kmac_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.80	100.00	100.00		100.00	94.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	100.00	100.00	100.00	94.23	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
u_key_index_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
TOTAL		69	69	100.00
CONT_ASSIGN	153	1	1	100.00
ALWAYS	161	3	3	100.00
ALWAYS	166	30	30	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
ALWAYS	268	6	6	100.00
CONT_ASSIGN	287	1	1	100.00
ALWAYS	307	6	6	100.00
ALWAYS	338	6	6	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
ALWAYS	420	6	6	100.00
CONT_ASSIGN	431	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
153	1	1
161	3	3
166	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
176	1	1
178	1	1
180	1	1
181	1	1
183	1	1
190	1	1
191	1	1
193	1	1
194	1	1
196	1	1
197	1	1
199	1	1
201	1	1
207	1	1
208	1	1
210	1	1
212	1	1
217	1	1
218	1	1
220	1	1
226	1	1
227	1	1
240	1	1
241	1	1
			MISSING_ELSE
251	1	1
252	1	1
253	1	1
254	1	1
258	1	1
260	1	1
265	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
274	1	1
			MISSING_ELSE
287	1	1
307	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
372	1	1
394	1	1
420	1	1
421	1	1
422	1	1
423	1	1
424	1	1
425	1	1
431	1	1

---

Cond Coverage for Module : kmac_core

	Total	Covered	Percent
Conditions	28	28	100.00
Logical	28	28	100.00
Non-Logical	0	0
Event	0	0

 LINE       180
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T14
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       207
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T56
1	0	Covered	T1,T3,T4

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       252
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       253
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       254
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       258
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       260
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       265
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       270
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T56

 LINE       394
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       431
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Module : kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	181	Covered	T1,T3,T4
StKmacFlush	208	Covered	T1,T3,T4
StKmacIdle	183	Covered	T1,T2,T3
StKmacMsg	194	Covered	T1,T3,T4
StTerminalError	241	Covered	T5,T6,T7

transitions	Line No.	Covered	Tests
StKey->StKmacMsg	194	Covered	T1,T3,T4
StKey->StTerminalError	241	Covered	T9,T54,T79
StKmacFlush->StKmacIdle	218	Covered	T1,T3,T4
StKmacFlush->StTerminalError	241	Covered	T34
StKmacIdle->StKey	181	Covered	T1,T3,T4
StKmacIdle->StTerminalError	241	Covered	T6,T35,T105
StKmacMsg->StKmacFlush	208	Covered	T1,T3,T4
StKmacMsg->StTerminalError	241	Covered	T5,T7,T106

---

Branch Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
Branches		50	47	94.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	253	2	2	100.00
TERNARY	254	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	2	2	100.00
TERNARY	265	2	2	100.00
IF	161	2	2	100.00
CASE	178	10	10	100.00
IF	240	2	2	100.00
IF	268	4	4	100.00
CASE	307	6	5	83.33
CASE	420	6	5	83.33
CASE	338	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	254	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	260	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (st)
-2-:	180	if ((kmac_en_i && start_i))
-3-:	193	if (sent_blocksize)
-4-:	207	if ((process_i || process_latched))
-5-:	217	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T1,T3,T4
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T1,T3,T4
StKey	-	0	-	-	Covered	T1,T3,T4
StKmacMsg	-	-	1	-	Covered	T1,T3,T4
StKmacMsg	-	-	0	-	Covered	T1,T3,T4
StKmacFlush	-	-	-	1	Covered	T1,T3,T4
StKmacFlush	-	-	-	0	Covered	T1,T3,T4
StTerminalError	-	-	-	-	Covered	T5,T6,T7
default	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	240	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if ((!rst_ni))
-2-:	270	if ((process_i && (!process_o)))
-3-:	272	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T4
Key256	Covered	T1,T3,T4
Key384	Covered	T1,T3,T15
Key512	Covered	T1,T4,T14
default	Not Covered

	LineNo.	Expression
-1-:	420	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T1,T15,T16
L256	Covered	T1,T2,T3
L384	Covered	T1,T3,T16
L512	Covered	T1,T16,T17
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T4
Key256	Covered	T1,T3,T4
Key384	Covered	T1,T3,T15
Key512	Covered	T1,T4,T14
default	Not Covered

---

Assert Coverage for Module : kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	534602206	7061331	0	0
KeyDataStableWhenValid_M	534602206	291107011	0	0
KeyLengthStableWhenValid_M	534602206	291107011	0	0
KmacEnStable_M	534602206	21370	0	0
MaxKeyLenMatchToKey512_A	658	658	0	0
ModeStable_M	534602206	33078	0	0
ProcessLatchedCleared_A	534602206	1	0	0
StrengthStable_M	534602206	39088	0	0
u_state_regs_A	534602206	534462088	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534602206	7061331	0	0
T1	335225	114969	0	0
T2	1125	0	0	0
T3	72251	0	0	0
T4	15257	186	0	0
T5	2289	0	0	0
T14	141115	414	0	0
T15	430475	50819	0	0
T16	38406	138	0	0
T17	65262	59	0	0
T18	102834	5256	0	0
T20	0	3435	0	0
T25	0	6285	0	0
T73	0	83397	0	0

KeyDataStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	534602206	291107011	0	0
T1	335225	226606	0	0
T2	1125	0	0	0
T3	72251	0	0	0
T4	15257	8128	0	0
T5	2289	108	0	0
T14	141115	75492	0	0
T15	430475	323714	0	0
T16	38406	19768	0	0
T17	65262	25925	0	0
T18	102834	445528	0	0
T20	0	143533	0	0
T73	0	161854	0	0

KeyLengthStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	534602206	291107011	0	0
T1	335225	226606	0	0
T2	1125	0	0	0
T3	72251	0	0	0
T4	15257	8128	0	0
T5	2289	108	0	0
T14	141115	75492	0	0
T15	430475	323714	0	0
T16	38406	19768	0	0
T17	65262	25925	0	0
T18	102834	445528	0	0
T20	0	143533	0	0
T73	0	161854	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	534602206	21370	0	0
T1	335225	210	0	0
T2	1125	0	0	0
T3	72251	12	0	0
T4	15257	5	0	0
T5	2289	1	0	0
T14	141115	7	0	0
T15	430475	41	0	0
T16	38406	29	0	0
T17	65262	19	0	0
T18	102834	78	0	0
T20	0	57	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658	658	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	534602206	33078	0	0
T1	335225	346	0	0
T2	1125	0	0	0
T3	72251	11	0	0
T4	15257	5	0	0
T5	2289	1	0	0
T14	141115	7	0	0
T15	430475	41	0	0
T16	38406	30	0	0
T17	65262	21	0	0
T18	102834	137	0	0
T19	0	1	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534602206	1	0	0
T56	30704	1	0	0
T57	15101	0	0	0
T106	2101	0	0	0
T107	1651	0	0	0
T108	26931	0	0	0
T109	148808	0	0	0
T110	1174	0	0	0
T111	83199	0	0	0
T112	6159	0	0	0
T113	994	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	534602206	39088	0	0
T1	335225	343	0	0
T2	1125	1	0	0
T3	72251	14	0	0
T4	15257	2	0	0
T5	2289	3	0	0
T14	141115	7	0	0
T15	430475	52	0	0
T16	38406	44	0	0
T17	65262	25	0	0
T18	102834	136	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534602206	534462088	0	0
T1	335225	335138	0	0
T2	1125	1031	0	0
T3	72251	72181	0	0
T4	15257	15165	0	0
T5	2289	2161	0	0
T14	141115	141036	0	0
T15	430475	430405	0	0
T16	38406	38343	0	0
T17	65262	65197	0	0
T18	102834	102825	0	0