Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	535956313	3086	0	0
entropy_period_rd_A	535956313	2591	0	0
intr_enable_rd_A	535956313	3391	0	0
prefix_0_rd_A	535956313	2833	0	0
prefix_10_rd_A	535956313	2639	0	0
prefix_1_rd_A	535956313	2760	0	0
prefix_2_rd_A	535956313	2655	0	0
prefix_3_rd_A	535956313	2562	0	0
prefix_4_rd_A	535956313	2672	0	0
prefix_5_rd_A	535956313	2530	0	0
prefix_6_rd_A	535956313	2691	0	0
prefix_7_rd_A	535956313	2647	0	0
prefix_8_rd_A	535956313	2707	0	0
prefix_9_rd_A	535956313	2597	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	3086	0	0
T45	3998	2	0	0
T46	22960	3	0	0
T47	24305	1	0	0
T114	13071	97	0	0
T115	3061	6	0	0
T116	9566	1	0	0
T121	2137	4	0	0
T135	8368	3	0	0
T136	7628	1	0	0
T138	23229	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2591	0	0
T47	24305	101	0	0
T82	4219	10	0	0
T84	13640	100	0	0
T86	2335	4	0	0
T138	23229	109	0	0
T151	5557	27	0	0
T152	11043	8	0	0
T153	5261	6	0	0
T154	125392	144	0	0
T155	1540	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	3391	0	0
T47	24305	90	0	0
T82	4219	9	0	0
T84	13640	82	0	0
T138	23229	178	0	0
T151	5557	39	0	0
T152	11043	25	0	0
T153	5261	38	0	0
T156	1148	26	0	0
T157	1541	23	0	0
T158	1159	7	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2833	0	0
T47	24305	95	0	0
T82	4219	26	0	0
T84	13640	69	0	0
T86	2335	1	0	0
T138	23229	77	0	0
T151	5557	25	0	0
T152	11043	55	0	0
T153	5261	24	0	0
T154	125392	174	0	0
T155	1540	1	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2639	0	0
T47	24305	68	0	0
T82	4219	18	0	0
T84	13640	55	0	0
T138	23229	82	0	0
T151	5557	16	0	0
T152	11043	11	0	0
T153	5261	7	0	0
T154	125392	307	0	0
T155	1540	4	0	0
T159	26143	208	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2760	0	0
T47	24305	46	0	0
T82	4219	15	0	0
T84	13640	73	0	0
T86	2335	5	0	0
T138	23229	96	0	0
T151	5557	31	0	0
T152	11043	38	0	0
T153	5261	10	0	0
T154	125392	356	0	0
T155	1540	9	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2655	0	0
T47	24305	84	0	0
T82	4219	22	0	0
T84	13640	55	0	0
T86	2335	7	0	0
T138	23229	91	0	0
T151	5557	51	0	0
T152	11043	2	0	0
T153	5261	2	0	0
T154	125392	308	0	0
T155	1540	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2562	0	0
T47	24305	100	0	0
T82	4219	23	0	0
T84	13640	62	0	0
T86	2335	5	0	0
T138	23229	61	0	0
T151	5557	14	0	0
T152	11043	35	0	0
T153	5261	1	0	0
T154	125392	241	0	0
T155	1540	8	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2672	0	0
T47	24305	106	0	0
T82	4219	8	0	0
T84	13640	38	0	0
T86	2335	5	0	0
T138	23229	79	0	0
T151	5557	62	0	0
T152	11043	55	0	0
T153	5261	21	0	0
T154	125392	229	0	0
T155	1540	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2530	0	0
T47	24305	70	0	0
T82	4219	20	0	0
T84	13640	58	0	0
T86	2335	4	0	0
T138	23229	73	0	0
T151	5557	3	0	0
T152	11043	20	0	0
T154	125392	274	0	0
T155	1540	8	0	0
T159	26143	210	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2691	0	0
T47	24305	76	0	0
T82	4219	18	0	0
T84	13640	41	0	0
T86	2335	1	0	0
T138	23229	80	0	0
T151	5557	5	0	0
T152	11043	22	0	0
T153	5261	21	0	0
T154	125392	258	0	0
T155	1540	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2647	0	0
T47	24305	80	0	0
T82	4219	9	0	0
T84	13640	67	0	0
T114	13071	1	0	0
T138	23229	68	0	0
T151	5557	3	0	0
T152	11043	34	0	0
T153	5261	17	0	0
T154	125392	313	0	0
T155	1540	2	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2707	0	0
T47	24305	69	0	0
T82	4219	13	0	0
T84	13640	49	0	0
T86	2335	5	0	0
T138	23229	91	0	0
T151	5557	9	0	0
T152	11043	40	0	0
T154	125392	265	0	0
T155	1540	4	0	0
T159	26143	223	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535956313	2597	0	0
T47	24305	73	0	0
T82	4219	20	0	0
T84	13640	56	0	0
T86	2335	1	0	0
T138	23229	86	0	0
T151	5557	2	0	0
T152	11043	29	0	0
T153	5261	15	0	0
T154	125392	241	0	0
T155	1540	2	0	0