Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	323	1			T2	8		T10	5		T7	1
all_values[1]	323	1			T2	8		T10	5		T7	1
all_values[2]	323	1			T2	8		T10	5		T7	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

526

1

T2

11

T10

6

T7

3

auto[1]

443

1

T2

13

T10

9

T11

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

594

1

T2

18

T10

9

T7

3

auto[1]

375

1

T2

6

T10

6

T21

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	116	1			T2	1		T10	3		T7	1
all_values[0]	auto[0]	auto[1]	75	1			T2	2		T10	1		T78	4
all_values[0]	auto[1]	auto[0]	82	1			T2	5		T11	4		T21	1
all_values[0]	auto[1]	auto[1]	50	1			T10	1		T21	3		T78	1
all_values[1]	auto[0]	auto[0]	106	1			T2	4		T7	1		T11	1
all_values[1]	auto[0]	auto[1]	59	1			T2	1		T10	1		T21	3
all_values[1]	auto[1]	auto[0]	92	1			T2	2		T10	3		T11	3
all_values[1]	auto[1]	auto[1]	66	1			T2	1		T10	1		T78	2
all_values[2]	auto[0]	auto[0]	105	1			T2	1		T7	1		T11	4
all_values[2]	auto[0]	auto[1]	65	1			T2	2		T10	1		T21	3
all_values[2]	auto[1]	auto[0]	93	1			T2	5		T10	3		T21	1
all_values[2]	auto[1]	auto[1]	60	1			T10	1		T78	5		T84	6