Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
47.57	46.89	61.77	16.56	0.00	45.98	100.00	61.77

Total tests in report: 215

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
43.42	43.42	46.39	46.39	55.45	55.45	16.16	16.16	0.00	0.00	44.93	44.93	96.05	96.05	44.94	44.94	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.2111189812
44.87	1.45	46.86	0.47	58.12	2.66	16.51	0.35	0.00	0.00	45.60	0.67	97.37	1.32	49.64	4.71	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.541609391
45.82	0.95	46.89	0.03	58.56	0.44	16.59	0.09	0.00	0.00	45.75	0.15	97.63	0.26	55.35	5.71	/workspace/coverage/cover_reg_top/20.kmac_intr_test.3870091647
46.68	0.86	46.89	0.00	60.49	1.93	17.16	0.57	0.00	0.00	45.98	0.22	97.63	0.00	58.63	3.28	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.640105310
46.92	0.24	46.89	0.00	60.82	0.33	17.16	0.00	0.00	0.00	45.98	0.00	98.42	0.79	59.20	0.57	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.474167711
47.15	0.23	46.89	0.00	60.82	0.00	17.16	0.00	0.00	0.00	45.98	0.00	100.00	1.58	59.20	0.00	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1415408412
47.28	0.14	46.89	0.00	60.96	0.15	17.25	0.09	0.00	0.00	45.98	0.00	100.00	0.00	59.91	0.71	/workspace/coverage/cover_reg_top/24.kmac_intr_test.2061137647
47.37	0.08	46.89	0.00	60.96	0.00	17.25	0.00	0.00	0.00	45.98	0.00	100.00	0.00	60.49	0.57	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.4218243113
47.43	0.07	46.89	0.00	61.44	0.47	17.25	0.00	0.00	0.00	45.98	0.00	100.00	0.00	60.49	0.00	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.1416970653
47.50	0.06	46.89	0.00	61.44	0.00	17.25	0.00	0.00	0.00	45.98	0.00	100.00	0.00	60.91	0.43	/workspace/coverage/cover_reg_top/13.kmac_intr_test.1953072700
47.55	0.05	46.89	0.00	61.51	0.07	17.25	0.00	0.00	0.00	45.98	0.00	100.00	0.00	61.20	0.29	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.889630125
47.59	0.05	46.89	0.00	61.55	0.04	17.25	0.00	0.00	0.00	45.98	0.00	100.00	0.00	61.48	0.29	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.4141108595
47.63	0.04	46.89	0.00	61.66	0.11	17.25	0.00	0.00	0.00	45.98	0.00	100.00	0.00	61.63	0.14	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.2912683852
47.65	0.02	46.89	0.00	61.66	0.00	17.25	0.00	0.00	0.00	45.98	0.00	100.00	0.00	61.77	0.14	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.156521447
47.66	0.01	46.89	0.00	61.69	0.04	17.29	0.04	0.00	0.00	45.98	0.00	100.00	0.00	61.77	0.00	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1000115487
47.67	0.01	46.89	0.00	61.77	0.07	17.29	0.00	0.00	0.00	45.98	0.00	100.00	0.00	61.77	0.00	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.1058952932

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2612193179
/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1648599931
/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1894097909
/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2272690301
/workspace/coverage/cover_reg_top/0.kmac_csr_rw.1541100259
/workspace/coverage/cover_reg_top/0.kmac_intr_test.2495883198
/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2271107650
/workspace/coverage/cover_reg_top/0.kmac_mem_walk.3655905061
/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1121478685
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3713230792
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.877411225
/workspace/coverage/cover_reg_top/0.kmac_tl_errors.688498658
/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1823491364
/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2487386245
/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2686949620
/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2870270628
/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2875383817
/workspace/coverage/cover_reg_top/1.kmac_csr_rw.2432842532
/workspace/coverage/cover_reg_top/1.kmac_intr_test.2823325729
/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3683243588
/workspace/coverage/cover_reg_top/1.kmac_mem_walk.1704048083
/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3999487859
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2383344929
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2658209495
/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.306568100
/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2305641347
/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3305726559
/workspace/coverage/cover_reg_top/10.kmac_intr_test.2616232201
/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3384450115
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1057261092
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3212860467
/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.255391978
/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1452006645
/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2468068851
/workspace/coverage/cover_reg_top/11.kmac_intr_test.751934580
/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.4115111126
/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2026302877
/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2223815001
/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2455345424
/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1089330791
/workspace/coverage/cover_reg_top/12.kmac_csr_rw.3049047418
/workspace/coverage/cover_reg_top/12.kmac_intr_test.1031308027
/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.680631092
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.936049541
/workspace/coverage/cover_reg_top/12.kmac_tl_errors.2553857287
/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3020419559
/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1166481338
/workspace/coverage/cover_reg_top/13.kmac_csr_rw.4125085041
/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2346453150
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1353777231
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3657440333
/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1684712362
/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3360599373
/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.68205543
/workspace/coverage/cover_reg_top/14.kmac_csr_rw.3914757148
/workspace/coverage/cover_reg_top/14.kmac_intr_test.4051562536
/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2271370981
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.691425402
/workspace/coverage/cover_reg_top/14.kmac_tl_errors.255879292
/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1691844906
/workspace/coverage/cover_reg_top/15.kmac_csr_rw.3735844849
/workspace/coverage/cover_reg_top/15.kmac_intr_test.3126913153
/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.4070317831
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3864391044
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3681320284
/workspace/coverage/cover_reg_top/15.kmac_tl_errors.3327607277
/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2429176123
/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1526143473
/workspace/coverage/cover_reg_top/16.kmac_csr_rw.290105094
/workspace/coverage/cover_reg_top/16.kmac_intr_test.2812362898
/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.675638326
/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4092706916
/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.874800372
/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2392663873
/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3508864098
/workspace/coverage/cover_reg_top/17.kmac_csr_rw.3155314265
/workspace/coverage/cover_reg_top/17.kmac_intr_test.486468955
/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1254997124
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1375427244
/workspace/coverage/cover_reg_top/17.kmac_tl_errors.1387803935
/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3557767390
/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3124068838
/workspace/coverage/cover_reg_top/18.kmac_csr_rw.640752857
/workspace/coverage/cover_reg_top/18.kmac_intr_test.819370701
/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2258602892
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3326223535
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1796355909
/workspace/coverage/cover_reg_top/18.kmac_tl_errors.1283520469
/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.317082571
/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1214315540
/workspace/coverage/cover_reg_top/19.kmac_csr_rw.373787616
/workspace/coverage/cover_reg_top/19.kmac_intr_test.2856218643
/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1993933161
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4277981636
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3558931444
/workspace/coverage/cover_reg_top/19.kmac_tl_errors.772691630
/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.804980316
/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2858714595
/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3928485454
/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3569333392
/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3903574590
/workspace/coverage/cover_reg_top/2.kmac_csr_rw.3204656863
/workspace/coverage/cover_reg_top/2.kmac_intr_test.2062167778
/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1642172443
/workspace/coverage/cover_reg_top/2.kmac_mem_walk.577213531
/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3816868790
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3505670302
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.704377007
/workspace/coverage/cover_reg_top/2.kmac_tl_errors.1654348438
/workspace/coverage/cover_reg_top/21.kmac_intr_test.3108009044
/workspace/coverage/cover_reg_top/22.kmac_intr_test.240838591
/workspace/coverage/cover_reg_top/23.kmac_intr_test.2813435721
/workspace/coverage/cover_reg_top/25.kmac_intr_test.2511510926
/workspace/coverage/cover_reg_top/26.kmac_intr_test.3107338370
/workspace/coverage/cover_reg_top/27.kmac_intr_test.767020400
/workspace/coverage/cover_reg_top/28.kmac_intr_test.358638401
/workspace/coverage/cover_reg_top/29.kmac_intr_test.901920287
/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1581047337
/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.338695496
/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3217951850
/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.4007498509
/workspace/coverage/cover_reg_top/3.kmac_csr_rw.3343145357
/workspace/coverage/cover_reg_top/3.kmac_intr_test.3164055756
/workspace/coverage/cover_reg_top/3.kmac_mem_walk.1659854560
/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2224110981
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2693485597
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.4157866703
/workspace/coverage/cover_reg_top/3.kmac_tl_errors.2662826523
/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.600262924
/workspace/coverage/cover_reg_top/30.kmac_intr_test.4187715238
/workspace/coverage/cover_reg_top/31.kmac_intr_test.2043515484
/workspace/coverage/cover_reg_top/32.kmac_intr_test.2719997043
/workspace/coverage/cover_reg_top/33.kmac_intr_test.130896404
/workspace/coverage/cover_reg_top/34.kmac_intr_test.1434502410
/workspace/coverage/cover_reg_top/35.kmac_intr_test.3420213213
/workspace/coverage/cover_reg_top/36.kmac_intr_test.3136186522
/workspace/coverage/cover_reg_top/37.kmac_intr_test.2617597874
/workspace/coverage/cover_reg_top/38.kmac_intr_test.1229354711
/workspace/coverage/cover_reg_top/39.kmac_intr_test.1651336167
/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.320917745
/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.4033032898
/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.669232794
/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1702554507
/workspace/coverage/cover_reg_top/4.kmac_csr_rw.50054304
/workspace/coverage/cover_reg_top/4.kmac_intr_test.3997971613
/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3588659418
/workspace/coverage/cover_reg_top/4.kmac_mem_walk.1552165858
/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.271356215
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3761603666
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1890138792
/workspace/coverage/cover_reg_top/4.kmac_tl_errors.1000614432
/workspace/coverage/cover_reg_top/40.kmac_intr_test.504262862
/workspace/coverage/cover_reg_top/41.kmac_intr_test.1088588654
/workspace/coverage/cover_reg_top/42.kmac_intr_test.1722795157
/workspace/coverage/cover_reg_top/43.kmac_intr_test.4213836389
/workspace/coverage/cover_reg_top/44.kmac_intr_test.4066347304
/workspace/coverage/cover_reg_top/45.kmac_intr_test.263382138
/workspace/coverage/cover_reg_top/46.kmac_intr_test.2438873009
/workspace/coverage/cover_reg_top/47.kmac_intr_test.3559960328
/workspace/coverage/cover_reg_top/48.kmac_intr_test.697271745
/workspace/coverage/cover_reg_top/49.kmac_intr_test.2358047082
/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2628020490
/workspace/coverage/cover_reg_top/5.kmac_csr_rw.2643023670
/workspace/coverage/cover_reg_top/5.kmac_intr_test.3315207828
/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3920272
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.373834436
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2134322455
/workspace/coverage/cover_reg_top/5.kmac_tl_errors.482747907
/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2218702959
/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3136598471
/workspace/coverage/cover_reg_top/6.kmac_csr_rw.1144421337
/workspace/coverage/cover_reg_top/6.kmac_intr_test.1654982170
/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2538599537
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3158868312
/workspace/coverage/cover_reg_top/6.kmac_tl_errors.3690381062
/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3964823141
/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.124543080
/workspace/coverage/cover_reg_top/7.kmac_csr_rw.2772101798
/workspace/coverage/cover_reg_top/7.kmac_intr_test.1652007882
/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.129421880
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2226611174
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.4124493660
/workspace/coverage/cover_reg_top/7.kmac_tl_errors.3725266611
/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2577068171
/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1272363876
/workspace/coverage/cover_reg_top/8.kmac_csr_rw.1588080028
/workspace/coverage/cover_reg_top/8.kmac_intr_test.2203457013
/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2378595092
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2555492533
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2287234860
/workspace/coverage/cover_reg_top/8.kmac_tl_errors.696787930
/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1378104175
/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2780125605
/workspace/coverage/cover_reg_top/9.kmac_csr_rw.2877255378
/workspace/coverage/cover_reg_top/9.kmac_intr_test.3119974813
/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.237597331
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1622037454
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1850226092
/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.959070291

Total test records in report: 215

tests.html | tests1.html | tests2.html | tests3.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.2432842532	Aug 14 05:12:25 PM PDT 24	Aug 14 05:12:26 PM PDT 24	15945685 ps
T2	/workspace/coverage/cover_reg_top/43.kmac_intr_test.4213836389	Aug 14 05:13:16 PM PDT 24	Aug 14 05:13:17 PM PDT 24	24798902 ps
T3	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.2111189812	Aug 14 05:12:37 PM PDT 24	Aug 14 05:12:43 PM PDT 24	396715335 ps
T10	/workspace/coverage/cover_reg_top/20.kmac_intr_test.3870091647	Aug 14 05:13:14 PM PDT 24	Aug 14 05:13:15 PM PDT 24	13635250 ps
T6	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2538599537	Aug 14 05:12:48 PM PDT 24	Aug 14 05:12:51 PM PDT 24	101899862 ps
T7	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.541609391	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:10 PM PDT 24	537350524 ps
T4	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.874800372	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:09 PM PDT 24	72936434 ps
T11	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2719997043	Aug 14 05:13:14 PM PDT 24	Aug 14 05:13:15 PM PDT 24	13873113 ps
T5	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1526143473	Aug 14 05:13:09 PM PDT 24	Aug 14 05:13:12 PM PDT 24	58908255 ps
T8	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2870270628	Aug 14 05:12:23 PM PDT 24	Aug 14 05:12:24 PM PDT 24	14864078 ps
T21	/workspace/coverage/cover_reg_top/36.kmac_intr_test.3136186522	Aug 14 05:13:16 PM PDT 24	Aug 14 05:13:17 PM PDT 24	13296386 ps
T12	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1166481338	Aug 14 05:13:11 PM PDT 24	Aug 14 05:13:12 PM PDT 24	55523287 ps
T9	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1353777231	Aug 14 05:13:05 PM PDT 24	Aug 14 05:13:06 PM PDT 24	103167112 ps
T13	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.1000614432	Aug 14 05:12:39 PM PDT 24	Aug 14 05:12:41 PM PDT 24	385295196 ps
T22	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.50054304	Aug 14 05:12:42 PM PDT 24	Aug 14 05:12:43 PM PDT 24	16162785 ps
T14	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.688498658	Aug 14 05:12:20 PM PDT 24	Aug 14 05:12:22 PM PDT 24	621326739 ps
T15	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1214315540	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:08 PM PDT 24	446874329 ps
T16	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.1387803935	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:09 PM PDT 24	129571093 ps
T55	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1993933161	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:09 PM PDT 24	92224050 ps
T26	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.474167711	Aug 14 05:13:08 PM PDT 24	Aug 14 05:13:11 PM PDT 24	495928955 ps
T81	/workspace/coverage/cover_reg_top/0.kmac_intr_test.2495883198	Aug 14 05:12:23 PM PDT 24	Aug 14 05:12:24 PM PDT 24	15811162 ps
T27	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3713230792	Aug 14 05:12:21 PM PDT 24	Aug 14 05:12:23 PM PDT 24	110720123 ps
T23	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3964823141	Aug 14 05:12:48 PM PDT 24	Aug 14 05:12:53 PM PDT 24	306545822 ps
T56	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1121478685	Aug 14 05:12:22 PM PDT 24	Aug 14 05:12:24 PM PDT 24	59856943 ps
T17	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1642172443	Aug 14 05:12:38 PM PDT 24	Aug 14 05:12:40 PM PDT 24	271218379 ps
T78	/workspace/coverage/cover_reg_top/13.kmac_intr_test.1953072700	Aug 14 05:13:05 PM PDT 24	Aug 14 05:13:06 PM PDT 24	68648736 ps
T25	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.959070291	Aug 14 05:12:54 PM PDT 24	Aug 14 05:12:57 PM PDT 24	410124606 ps
T28	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.3735844849	Aug 14 05:13:09 PM PDT 24	Aug 14 05:13:10 PM PDT 24	24704447 ps
T85	/workspace/coverage/cover_reg_top/15.kmac_intr_test.3126913153	Aug 14 05:13:07 PM PDT 24	Aug 14 05:13:08 PM PDT 24	42321961 ps
T24	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.804980316	Aug 14 05:13:07 PM PDT 24	Aug 14 05:13:12 PM PDT 24	374999860 ps
T18	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2875383817	Aug 14 05:12:29 PM PDT 24	Aug 14 05:12:31 PM PDT 24	191972682 ps
T60	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2134322455	Aug 14 05:12:54 PM PDT 24	Aug 14 05:12:57 PM PDT 24	107045084 ps
T29	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3928485454	Aug 14 05:12:30 PM PDT 24	Aug 14 05:12:46 PM PDT 24	1133021165 ps
T57	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3657440333	Aug 14 05:13:04 PM PDT 24	Aug 14 05:13:07 PM PDT 24	498684620 ps
T58	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2487386245	Aug 14 05:12:25 PM PDT 24	Aug 14 05:12:30 PM PDT 24	260286641 ps
T30	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1648599931	Aug 14 05:12:20 PM PDT 24	Aug 14 05:12:35 PM PDT 24	297445089 ps
T63	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3326223535	Aug 14 05:13:05 PM PDT 24	Aug 14 05:13:06 PM PDT 24	40412728 ps
T84	/workspace/coverage/cover_reg_top/24.kmac_intr_test.2061137647	Aug 14 05:13:15 PM PDT 24	Aug 14 05:13:16 PM PDT 24	41740770 ps
T95	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3305726559	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:57 PM PDT 24	89619679 ps
T31	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3158868312	Aug 14 05:12:48 PM PDT 24	Aug 14 05:12:49 PM PDT 24	319124823 ps
T96	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3997971613	Aug 14 05:12:41 PM PDT 24	Aug 14 05:12:42 PM PDT 24	43067257 ps
T32	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.936049541	Aug 14 05:13:01 PM PDT 24	Aug 14 05:13:02 PM PDT 24	265721183 ps
T19	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.696787930	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:58 PM PDT 24	261327766 ps
T20	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.124543080	Aug 14 05:12:53 PM PDT 24	Aug 14 05:12:55 PM PDT 24	132766270 ps
T82	/workspace/coverage/cover_reg_top/28.kmac_intr_test.358638401	Aug 14 05:13:13 PM PDT 24	Aug 14 05:13:14 PM PDT 24	22314753 ps
T61	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2223815001	Aug 14 05:12:54 PM PDT 24	Aug 14 05:12:56 PM PDT 24	50760506 ps
T83	/workspace/coverage/cover_reg_top/49.kmac_intr_test.2358047082	Aug 14 05:13:17 PM PDT 24	Aug 14 05:13:18 PM PDT 24	46779996 ps
T86	/workspace/coverage/cover_reg_top/5.kmac_intr_test.3315207828	Aug 14 05:12:49 PM PDT 24	Aug 14 05:12:50 PM PDT 24	50798298 ps
T97	/workspace/coverage/cover_reg_top/29.kmac_intr_test.901920287	Aug 14 05:13:14 PM PDT 24	Aug 14 05:13:15 PM PDT 24	40360720 ps
T98	/workspace/coverage/cover_reg_top/3.kmac_intr_test.3164055756	Aug 14 05:12:42 PM PDT 24	Aug 14 05:12:43 PM PDT 24	16226005 ps
T99	/workspace/coverage/cover_reg_top/46.kmac_intr_test.2438873009	Aug 14 05:13:16 PM PDT 24	Aug 14 05:13:17 PM PDT 24	74593583 ps
T59	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.640105310	Aug 14 05:13:05 PM PDT 24	Aug 14 05:13:08 PM PDT 24	183057983 ps
T100	/workspace/coverage/cover_reg_top/8.kmac_intr_test.2203457013	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:57 PM PDT 24	14443641 ps
T101	/workspace/coverage/cover_reg_top/11.kmac_intr_test.751934580	Aug 14 05:12:59 PM PDT 24	Aug 14 05:13:00 PM PDT 24	43589999 ps
T102	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.4157866703	Aug 14 05:12:40 PM PDT 24	Aug 14 05:12:41 PM PDT 24	56598668 ps
T103	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4092706916	Aug 14 05:13:08 PM PDT 24	Aug 14 05:13:10 PM PDT 24	42808008 ps
T77	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1000115487	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:58 PM PDT 24	153230621 ps
T104	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1581047337	Aug 14 05:12:39 PM PDT 24	Aug 14 05:12:48 PM PDT 24	527799286 ps
T105	/workspace/coverage/cover_reg_top/45.kmac_intr_test.263382138	Aug 14 05:13:13 PM PDT 24	Aug 14 05:13:14 PM PDT 24	19026560 ps
T106	/workspace/coverage/cover_reg_top/10.kmac_intr_test.2616232201	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:56 PM PDT 24	53105914 ps
T80	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1622037454	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:57 PM PDT 24	41891008 ps
T107	/workspace/coverage/cover_reg_top/31.kmac_intr_test.2043515484	Aug 14 05:13:14 PM PDT 24	Aug 14 05:13:14 PM PDT 24	14517316 ps
T108	/workspace/coverage/cover_reg_top/40.kmac_intr_test.504262862	Aug 14 05:13:17 PM PDT 24	Aug 14 05:13:17 PM PDT 24	40417064 ps
T79	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3816868790	Aug 14 05:12:40 PM PDT 24	Aug 14 05:12:42 PM PDT 24	111113603 ps
T109	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.680631092	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:57 PM PDT 24	134126988 ps
T62	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1890138792	Aug 14 05:12:39 PM PDT 24	Aug 14 05:12:41 PM PDT 24	249439014 ps
T110	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.271356215	Aug 14 05:12:48 PM PDT 24	Aug 14 05:12:50 PM PDT 24	27022699 ps
T111	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.889630125	Aug 14 05:12:50 PM PDT 24	Aug 14 05:12:52 PM PDT 24	111508331 ps
T112	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.129421880	Aug 14 05:12:48 PM PDT 24	Aug 14 05:12:50 PM PDT 24	150101820 ps
T113	/workspace/coverage/cover_reg_top/42.kmac_intr_test.1722795157	Aug 14 05:13:13 PM PDT 24	Aug 14 05:13:14 PM PDT 24	22478260 ps
T90	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.317082571	Aug 14 05:13:07 PM PDT 24	Aug 14 05:13:12 PM PDT 24	1047860086 ps
T114	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2258602892	Aug 14 05:13:09 PM PDT 24	Aug 14 05:13:11 PM PDT 24	79398925 ps
T115	/workspace/coverage/cover_reg_top/39.kmac_intr_test.1651336167	Aug 14 05:13:16 PM PDT 24	Aug 14 05:13:16 PM PDT 24	15992934 ps
T116	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.691425402	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:07 PM PDT 24	52292462 ps
T117	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.4115111126	Aug 14 05:12:57 PM PDT 24	Aug 14 05:12:58 PM PDT 24	79085704 ps
T118	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.2772101798	Aug 14 05:12:46 PM PDT 24	Aug 14 05:12:47 PM PDT 24	86064099 ps
T119	/workspace/coverage/cover_reg_top/18.kmac_intr_test.819370701	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:06 PM PDT 24	158886233 ps
T120	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2271370981	Aug 14 05:13:08 PM PDT 24	Aug 14 05:13:11 PM PDT 24	104113460 ps
T121	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1796355909	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:08 PM PDT 24	289368990 ps
T122	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.338695496	Aug 14 05:12:40 PM PDT 24	Aug 14 05:13:02 PM PDT 24	4798315431 ps
T66	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.2662826523	Aug 14 05:12:47 PM PDT 24	Aug 14 05:12:50 PM PDT 24	84133927 ps
T123	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2658209495	Aug 14 05:12:22 PM PDT 24	Aug 14 05:12:24 PM PDT 24	47144713 ps
T124	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2026302877	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:57 PM PDT 24	28228108 ps
T125	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2577068171	Aug 14 05:12:54 PM PDT 24	Aug 14 05:12:57 PM PDT 24	1389742275 ps
T126	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3558931444	Aug 14 05:13:07 PM PDT 24	Aug 14 05:13:09 PM PDT 24	120373053 ps
T127	/workspace/coverage/cover_reg_top/16.kmac_intr_test.2812362898	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:07 PM PDT 24	36608590 ps
T128	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.704377007	Aug 14 05:12:32 PM PDT 24	Aug 14 05:12:34 PM PDT 24	181802154 ps
T129	/workspace/coverage/cover_reg_top/14.kmac_intr_test.4051562536	Aug 14 05:13:09 PM PDT 24	Aug 14 05:13:10 PM PDT 24	15960159 ps
T130	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3920272	Aug 14 05:12:47 PM PDT 24	Aug 14 05:12:50 PM PDT 24	360141615 ps
T131	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.320917745	Aug 14 05:12:50 PM PDT 24	Aug 14 05:12:59 PM PDT 24	897213008 ps
T64	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.482747907	Aug 14 05:12:47 PM PDT 24	Aug 14 05:12:50 PM PDT 24	370821445 ps
T132	/workspace/coverage/cover_reg_top/35.kmac_intr_test.3420213213	Aug 14 05:13:17 PM PDT 24	Aug 14 05:13:18 PM PDT 24	36209650 ps
T133	/workspace/coverage/cover_reg_top/2.kmac_intr_test.2062167778	Aug 14 05:12:31 PM PDT 24	Aug 14 05:12:32 PM PDT 24	13258549 ps
T72	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3508864098	Aug 14 05:13:07 PM PDT 24	Aug 14 05:13:09 PM PDT 24	94902523 ps
T134	/workspace/coverage/cover_reg_top/44.kmac_intr_test.4066347304	Aug 14 05:13:17 PM PDT 24	Aug 14 05:13:18 PM PDT 24	37082146 ps
T135	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2555492533	Aug 14 05:12:54 PM PDT 24	Aug 14 05:12:55 PM PDT 24	71626458 ps
T136	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3903574590	Aug 14 05:12:39 PM PDT 24	Aug 14 05:12:41 PM PDT 24	55405996 ps
T92	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3360599373	Aug 14 05:13:09 PM PDT 24	Aug 14 05:13:12 PM PDT 24	1000577001 ps
T137	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3569333392	Aug 14 05:12:29 PM PDT 24	Aug 14 05:12:30 PM PDT 24	36234239 ps
T138	/workspace/coverage/cover_reg_top/33.kmac_intr_test.130896404	Aug 14 05:13:15 PM PDT 24	Aug 14 05:13:16 PM PDT 24	15485293 ps
T139	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2780125605	Aug 14 05:12:57 PM PDT 24	Aug 14 05:12:59 PM PDT 24	126444956 ps
T140	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1452006645	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:57 PM PDT 24	33997812 ps
T74	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1823491364	Aug 14 05:12:21 PM PDT 24	Aug 14 05:12:24 PM PDT 24	557083708 ps
T141	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2392663873	Aug 14 05:13:05 PM PDT 24	Aug 14 05:13:08 PM PDT 24	428685828 ps
T142	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.877411225	Aug 14 05:12:22 PM PDT 24	Aug 14 05:12:24 PM PDT 24	360352838 ps
T143	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2346453150	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:08 PM PDT 24	416170226 ps
T144	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.1588080028	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:57 PM PDT 24	49481251 ps
T145	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2224110981	Aug 14 05:12:39 PM PDT 24	Aug 14 05:12:42 PM PDT 24	411772024 ps
T146	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1254997124	Aug 14 05:13:08 PM PDT 24	Aug 14 05:13:10 PM PDT 24	73964410 ps
T68	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1702554507	Aug 14 05:12:47 PM PDT 24	Aug 14 05:12:48 PM PDT 24	23985887 ps
T33	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2271107650	Aug 14 05:12:22 PM PDT 24	Aug 14 05:12:23 PM PDT 24	106638693 ps
T34	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2383344929	Aug 14 05:12:23 PM PDT 24	Aug 14 05:12:25 PM PDT 24	52493675 ps
T35	/workspace/coverage/cover_reg_top/47.kmac_intr_test.3559960328	Aug 14 05:13:20 PM PDT 24	Aug 14 05:13:21 PM PDT 24	10894468 ps
T36	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.373834436	Aug 14 05:12:49 PM PDT 24	Aug 14 05:12:50 PM PDT 24	205179052 ps
T37	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3212860467	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:57 PM PDT 24	109934305 ps
T38	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2378595092	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:59 PM PDT 24	178030282 ps
T39	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.600262924	Aug 14 05:12:41 PM PDT 24	Aug 14 05:12:44 PM PDT 24	452356943 ps
T40	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.3914757148	Aug 14 05:13:05 PM PDT 24	Aug 14 05:13:06 PM PDT 24	72301233 ps
T41	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.675638326	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:09 PM PDT 24	96781559 ps
T42	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1272363876	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:57 PM PDT 24	204093191 ps
T147	/workspace/coverage/cover_reg_top/9.kmac_intr_test.3119974813	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:57 PM PDT 24	13234086 ps
T69	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.2912683852	Aug 14 05:12:22 PM PDT 24	Aug 14 05:12:26 PM PDT 24	365091329 ps
T148	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2272690301	Aug 14 05:12:23 PM PDT 24	Aug 14 05:12:26 PM PDT 24	39167617 ps
T149	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3999487859	Aug 14 05:12:23 PM PDT 24	Aug 14 05:12:25 PM PDT 24	144317695 ps
T150	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1894097909	Aug 14 05:12:26 PM PDT 24	Aug 14 05:12:27 PM PDT 24	57166365 ps
T151	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4277981636	Aug 14 05:13:07 PM PDT 24	Aug 14 05:13:08 PM PDT 24	59414777 ps
T152	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.3049047418	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:56 PM PDT 24	22861911 ps
T153	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2628020490	Aug 14 05:12:49 PM PDT 24	Aug 14 05:12:51 PM PDT 24	80983759 ps
T154	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.4070317831	Aug 14 05:13:08 PM PDT 24	Aug 14 05:13:10 PM PDT 24	260155984 ps
T155	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2858714595	Aug 14 05:12:42 PM PDT 24	Aug 14 05:12:47 PM PDT 24	203112521 ps
T156	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1375427244	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:08 PM PDT 24	80602080 ps
T157	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2305641347	Aug 14 05:12:58 PM PDT 24	Aug 14 05:12:59 PM PDT 24	42833708 ps
T158	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3384450115	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:58 PM PDT 24	76249324 ps
T159	/workspace/coverage/cover_reg_top/38.kmac_intr_test.1229354711	Aug 14 05:13:14 PM PDT 24	Aug 14 05:13:15 PM PDT 24	19230311 ps
T71	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.68205543	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:08 PM PDT 24	94693281 ps
T160	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1089330791	Aug 14 05:13:05 PM PDT 24	Aug 14 05:13:07 PM PDT 24	295542043 ps
T161	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3761603666	Aug 14 05:12:41 PM PDT 24	Aug 14 05:12:43 PM PDT 24	62564263 ps
T162	/workspace/coverage/cover_reg_top/1.kmac_intr_test.2823325729	Aug 14 05:12:25 PM PDT 24	Aug 14 05:12:26 PM PDT 24	44267170 ps
T163	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.3343145357	Aug 14 05:12:41 PM PDT 24	Aug 14 05:12:43 PM PDT 24	32099634 ps
T164	/workspace/coverage/cover_reg_top/23.kmac_intr_test.2813435721	Aug 14 05:13:15 PM PDT 24	Aug 14 05:13:16 PM PDT 24	13562138 ps
T165	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.2643023670	Aug 14 05:12:48 PM PDT 24	Aug 14 05:12:50 PM PDT 24	93514007 ps
T166	/workspace/coverage/cover_reg_top/19.kmac_intr_test.2856218643	Aug 14 05:13:07 PM PDT 24	Aug 14 05:13:08 PM PDT 24	15580098 ps
T67	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.3690381062	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:57 PM PDT 24	146221088 ps
T70	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.1654348438	Aug 14 05:12:36 PM PDT 24	Aug 14 05:12:39 PM PDT 24	389540917 ps
T88	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.4141108595	Aug 14 05:12:39 PM PDT 24	Aug 14 05:12:42 PM PDT 24	100656585 ps
T167	/workspace/coverage/cover_reg_top/6.kmac_intr_test.1654982170	Aug 14 05:12:48 PM PDT 24	Aug 14 05:12:49 PM PDT 24	31168711 ps
T89	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3020419559	Aug 14 05:12:57 PM PDT 24	Aug 14 05:13:00 PM PDT 24	162163940 ps
T168	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.4124493660	Aug 14 05:12:54 PM PDT 24	Aug 14 05:12:56 PM PDT 24	43107041 ps
T169	/workspace/coverage/cover_reg_top/30.kmac_intr_test.4187715238	Aug 14 05:13:17 PM PDT 24	Aug 14 05:13:18 PM PDT 24	15645832 ps
T170	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.290105094	Aug 14 05:13:08 PM PDT 24	Aug 14 05:13:09 PM PDT 24	56863028 ps
T171	/workspace/coverage/cover_reg_top/17.kmac_intr_test.486468955	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:07 PM PDT 24	36488071 ps
T172	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.1704048083	Aug 14 05:12:21 PM PDT 24	Aug 14 05:12:22 PM PDT 24	12398642 ps
T173	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3217951850	Aug 14 05:12:41 PM PDT 24	Aug 14 05:12:42 PM PDT 24	25472140 ps
T174	/workspace/coverage/cover_reg_top/12.kmac_intr_test.1031308027	Aug 14 05:12:57 PM PDT 24	Aug 14 05:12:58 PM PDT 24	15525824 ps
T175	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2693485597	Aug 14 05:12:41 PM PDT 24	Aug 14 05:12:42 PM PDT 24	55370350 ps
T176	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.1659854560	Aug 14 05:12:38 PM PDT 24	Aug 14 05:12:39 PM PDT 24	13458170 ps
T177	/workspace/coverage/cover_reg_top/41.kmac_intr_test.1088588654	Aug 14 05:13:15 PM PDT 24	Aug 14 05:13:16 PM PDT 24	14367425 ps
T178	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.2553857287	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:57 PM PDT 24	200773469 ps
T179	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2287234860	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:57 PM PDT 24	48870920 ps
T75	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.1283520469	Aug 14 05:13:09 PM PDT 24	Aug 14 05:13:11 PM PDT 24	46537523 ps
T94	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2429176123	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:10 PM PDT 24	362038541 ps
T43	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1415408412	Aug 14 05:12:39 PM PDT 24	Aug 14 05:12:41 PM PDT 24	42210447 ps
T46	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.373787616	Aug 14 05:13:07 PM PDT 24	Aug 14 05:13:08 PM PDT 24	46591172 ps
T47	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.255879292	Aug 14 05:13:10 PM PDT 24	Aug 14 05:13:12 PM PDT 24	26736082 ps
T48	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.156521447	Aug 14 05:13:05 PM PDT 24	Aug 14 05:13:09 PM PDT 24	207475842 ps
T49	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.306568100	Aug 14 05:12:23 PM PDT 24	Aug 14 05:12:26 PM PDT 24	185300728 ps
T50	/workspace/coverage/cover_reg_top/22.kmac_intr_test.240838591	Aug 14 05:13:16 PM PDT 24	Aug 14 05:13:17 PM PDT 24	13288594 ps
T51	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3681320284	Aug 14 05:13:05 PM PDT 24	Aug 14 05:13:07 PM PDT 24	366371587 ps
T52	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1850226092	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:58 PM PDT 24	121589070 ps
T53	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.255391978	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:59 PM PDT 24	149016222 ps
T54	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.2877255378	Aug 14 05:12:58 PM PDT 24	Aug 14 05:13:00 PM PDT 24	27147065 ps
T180	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3136598471	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:57 PM PDT 24	41864410 ps
T44	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3588659418	Aug 14 05:12:39 PM PDT 24	Aug 14 05:12:40 PM PDT 24	58568181 ps
T181	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.1541100259	Aug 14 05:12:23 PM PDT 24	Aug 14 05:12:24 PM PDT 24	30714723 ps
T91	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.4218243113	Aug 14 05:12:56 PM PDT 24	Aug 14 05:13:01 PM PDT 24	413387904 ps
T182	/workspace/coverage/cover_reg_top/37.kmac_intr_test.2617597874	Aug 14 05:13:15 PM PDT 24	Aug 14 05:13:16 PM PDT 24	13203814 ps
T45	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3683243588	Aug 14 05:12:26 PM PDT 24	Aug 14 05:12:27 PM PDT 24	109703890 ps
T183	/workspace/coverage/cover_reg_top/25.kmac_intr_test.2511510926	Aug 14 05:13:12 PM PDT 24	Aug 14 05:13:13 PM PDT 24	25733719 ps
T184	/workspace/coverage/cover_reg_top/48.kmac_intr_test.697271745	Aug 14 05:13:16 PM PDT 24	Aug 14 05:13:17 PM PDT 24	17346326 ps
T185	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.3725266611	Aug 14 05:12:50 PM PDT 24	Aug 14 05:12:53 PM PDT 24	101624068 ps
T93	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2218702959	Aug 14 05:12:50 PM PDT 24	Aug 14 05:12:55 PM PDT 24	836912916 ps
T76	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1684712362	Aug 14 05:13:04 PM PDT 24	Aug 14 05:13:07 PM PDT 24	226291777 ps
T186	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1057261092	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:57 PM PDT 24	21028710 ps
T187	/workspace/coverage/cover_reg_top/34.kmac_intr_test.1434502410	Aug 14 05:13:21 PM PDT 24	Aug 14 05:13:22 PM PDT 24	14080065 ps
T65	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.1058952932	Aug 14 05:12:57 PM PDT 24	Aug 14 05:12:59 PM PDT 24	36233110 ps
T188	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2226611174	Aug 14 05:12:48 PM PDT 24	Aug 14 05:12:50 PM PDT 24	75681713 ps
T189	/workspace/coverage/cover_reg_top/26.kmac_intr_test.3107338370	Aug 14 05:13:14 PM PDT 24	Aug 14 05:13:15 PM PDT 24	20157635 ps
T190	/workspace/coverage/cover_reg_top/7.kmac_intr_test.1652007882	Aug 14 05:12:46 PM PDT 24	Aug 14 05:12:47 PM PDT 24	14395139 ps
T191	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.4033032898	Aug 14 05:12:51 PM PDT 24	Aug 14 05:13:01 PM PDT 24	739260476 ps
T192	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.669232794	Aug 14 05:12:41 PM PDT 24	Aug 14 05:12:43 PM PDT 24	112066395 ps
T193	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2612193179	Aug 14 05:12:22 PM PDT 24	Aug 14 05:12:27 PM PDT 24	408368904 ps
T73	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.772691630	Aug 14 05:13:07 PM PDT 24	Aug 14 05:13:11 PM PDT 24	245406775 ps
T194	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.4125085041	Aug 14 05:13:05 PM PDT 24	Aug 14 05:13:06 PM PDT 24	57524065 ps
T195	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1691844906	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:08 PM PDT 24	266499738 ps
T196	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.237597331	Aug 14 05:12:57 PM PDT 24	Aug 14 05:13:00 PM PDT 24	124772670 ps
T197	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.1416970653	Aug 14 05:12:59 PM PDT 24	Aug 14 05:13:02 PM PDT 24	128111899 ps
T198	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3505670302	Aug 14 05:12:32 PM PDT 24	Aug 14 05:12:33 PM PDT 24	66895196 ps
T199	/workspace/coverage/cover_reg_top/27.kmac_intr_test.767020400	Aug 14 05:13:15 PM PDT 24	Aug 14 05:13:16 PM PDT 24	55481208 ps
T200	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.3655905061	Aug 14 05:12:22 PM PDT 24	Aug 14 05:12:23 PM PDT 24	14253045 ps
T201	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2455345424	Aug 14 05:12:56 PM PDT 24	Aug 14 05:12:58 PM PDT 24	263556777 ps
T202	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.1144421337	Aug 14 05:12:55 PM PDT 24	Aug 14 05:12:56 PM PDT 24	26516942 ps
T203	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.3327607277	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:10 PM PDT 24	121008155 ps
T204	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.3204656863	Aug 14 05:12:30 PM PDT 24	Aug 14 05:12:31 PM PDT 24	24800361 ps
T205	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3124068838	Aug 14 05:13:04 PM PDT 24	Aug 14 05:13:06 PM PDT 24	113704903 ps
T206	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.1552165858	Aug 14 05:12:39 PM PDT 24	Aug 14 05:12:40 PM PDT 24	31466269 ps
T207	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.640752857	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:07 PM PDT 24	21106555 ps
T208	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.577213531	Aug 14 05:12:33 PM PDT 24	Aug 14 05:12:34 PM PDT 24	19495629 ps
T209	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3557767390	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:10 PM PDT 24	211776816 ps
T210	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.4007498509	Aug 14 05:12:40 PM PDT 24	Aug 14 05:12:42 PM PDT 24	79588944 ps
T211	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.3155314265	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:07 PM PDT 24	61386607 ps
T212	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2468068851	Aug 14 05:12:57 PM PDT 24	Aug 14 05:12:58 PM PDT 24	13267831 ps
T213	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3864391044	Aug 14 05:13:06 PM PDT 24	Aug 14 05:13:07 PM PDT 24	295707026 ps
T87	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1378104175	Aug 14 05:12:55 PM PDT 24	Aug 14 05:13:00 PM PDT 24	368112435 ps
T214	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3108009044	Aug 14 05:13:15 PM PDT 24	Aug 14 05:13:16 PM PDT 24	45296602 ps
T215	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2686949620	Aug 14 05:12:25 PM PDT 24	Aug 14 05:12:45 PM PDT 24	1313578243 ps

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.2111189812
Short name	T3
Test name
Test status
Simulation time	396715335 ps
CPU time	5.38 seconds
Started	Aug 14 05:12:37 PM PDT 24
Finished	Aug 14 05:12:43 PM PDT 24
Peak memory	207004 kb
Host	smart-8e52a814-b6bd-473c-bf78-4f48c3459be5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111189812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.21111 89812 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.541609391
Short name	T7
Test name
Test status
Simulation time	537350524 ps
CPU time	3.62 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:10 PM PDT 24
Peak memory	215052 kb
Host	smart-d4538604-4cc5-41d9-b816-e959c83d6d79
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541609391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.541609391 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.3870091647
Short name	T10
Test name
Test status
Simulation time	13635250 ps
CPU time	0.74 seconds
Started	Aug 14 05:13:14 PM PDT 24
Finished	Aug 14 05:13:15 PM PDT 24
Peak memory	206412 kb
Host	smart-6c3478a6-9b7d-4ad0-b948-c824f7b00a69
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870091647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3870091647 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.640105310
Short name	T59
Test name
Test status
Simulation time	183057983 ps
CPU time	2.64 seconds
Started	Aug 14 05:13:05 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	223616 kb
Host	smart-2a6bd335-e377-4e5e-8b68-1ec40f94c3d2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640105310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac _shadow_reg_errors_with_csr_rw.640105310 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.474167711
Short name	T26
Test name
Test status
Simulation time	495928955 ps
CPU time	2.94 seconds
Started	Aug 14 05:13:08 PM PDT 24
Finished	Aug 14 05:13:11 PM PDT 24
Peak memory	223264 kb
Host	smart-02482271-9951-4e17-87ba-0700a6d24a73
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474167711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac _shadow_reg_errors_with_csr_rw.474167711 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1415408412
Short name	T43
Test name
Test status
Simulation time	42210447 ps
CPU time	1.2 seconds
Started	Aug 14 05:12:39 PM PDT 24
Finished	Aug 14 05:12:41 PM PDT 24
Peak memory	214856 kb
Host	smart-25afdc20-25c1-4f9e-bf0e-e414143626fd
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415408412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.1415408412 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.2061137647
Short name	T84
Test name
Test status
Simulation time	41740770 ps
CPU time	0.75 seconds
Started	Aug 14 05:13:15 PM PDT 24
Finished	Aug 14 05:13:16 PM PDT 24
Peak memory	206496 kb
Host	smart-deedb9f8-559a-4821-8aa9-f6d35364f68a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061137647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2061137647 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.4218243113
Short name	T91
Test name
Test status
Simulation time	413387904 ps
CPU time	4.59 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:13:01 PM PDT 24
Peak memory	215000 kb
Host	smart-2f749fb8-ea13-4740-a4e8-9c411117e02a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218243113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.4218 243113 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.1416970653
Short name	T197
Test name
Test status
Simulation time	128111899 ps
CPU time	2.05 seconds
Started	Aug 14 05:12:59 PM PDT 24
Finished	Aug 14 05:13:02 PM PDT 24
Peak memory	223228 kb
Host	smart-532a19d0-bd2b-4f41-ab63-e050a976cb76
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416970653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1416970653 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.1953072700
Short name	T78
Test name
Test status
Simulation time	68648736 ps
CPU time	0.81 seconds
Started	Aug 14 05:13:05 PM PDT 24
Finished	Aug 14 05:13:06 PM PDT 24
Peak memory	206508 kb
Host	smart-41deb962-cb24-4231-8b02-a7ecc68e50f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953072700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1953072700 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.889630125
Short name	T111
Test name
Test status
Simulation time	111508331 ps
CPU time	2.77 seconds
Started	Aug 14 05:12:50 PM PDT 24
Finished	Aug 14 05:12:52 PM PDT 24
Peak memory	215420 kb
Host	smart-852851c6-7406-4c88-8b1c-4a1ef603c3f4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889630125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_ shadow_reg_errors_with_csr_rw.889630125 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.4141108595
Short name	T88
Test name
Test status
Simulation time	100656585 ps
CPU time	2.69 seconds
Started	Aug 14 05:12:39 PM PDT 24
Finished	Aug 14 05:12:42 PM PDT 24
Peak memory	206808 kb
Host	smart-5d2956ef-3b20-4349-a4a2-680971cf1c90
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141108595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.41411 08595 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.2912683852
Short name	T69
Test name
Test status
Simulation time	365091329 ps
CPU time	3.47 seconds
Started	Aug 14 05:12:22 PM PDT 24
Finished	Aug 14 05:12:26 PM PDT 24
Peak memory	215008 kb
Host	smart-82dcb44d-7b4c-4d77-a584-5996747f46a5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912683852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2912683852 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.156521447
Short name	T48
Test name
Test status
Simulation time	207475842 ps
CPU time	4.56 seconds
Started	Aug 14 05:13:05 PM PDT 24
Finished	Aug 14 05:13:09 PM PDT 24
Peak memory	215048 kb
Host	smart-4371f834-619c-49cc-8155-66eafa00091c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156521447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.15652 1447 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1000115487
Short name	T77
Test name
Test status
Simulation time	153230621 ps
CPU time	1.21 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:58 PM PDT 24
Peak memory	215508 kb
Host	smart-98ac33b8-829f-4c6c-924c-614c9abaa722
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000115487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.1000115487 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.1058952932
Short name	T65
Test name
Test status
Simulation time	36233110 ps
CPU time	2.26 seconds
Started	Aug 14 05:12:57 PM PDT 24
Finished	Aug 14 05:12:59 PM PDT 24
Peak memory	218796 kb
Host	smart-2bf2c59e-fca5-4e7a-baa7-53e4addcd085
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058952932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1058952932 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2612193179
Short name	T193
Test name
Test status
Simulation time	408368904 ps
CPU time	4.83 seconds
Started	Aug 14 05:12:22 PM PDT 24
Finished	Aug 14 05:12:27 PM PDT 24
Peak memory	206592 kb
Host	smart-bcffe6c1-e927-4d5d-ac6c-9b752a660a7c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612193179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2612193 179 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1648599931
Short name	T30
Test name
Test status
Simulation time	297445089 ps
CPU time	15.04 seconds
Started	Aug 14 05:12:20 PM PDT 24
Finished	Aug 14 05:12:35 PM PDT 24
Peak memory	206704 kb
Host	smart-f50e59b1-a34f-4b44-92b7-56491c0cb26e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648599931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1648599 931 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1894097909
Short name	T150
Test name
Test status
Simulation time	57166365 ps
CPU time	1.06 seconds
Started	Aug 14 05:12:26 PM PDT 24
Finished	Aug 14 05:12:27 PM PDT 24
Peak memory	206652 kb
Host	smart-27c38f1d-f52c-4b6b-b098-6a77528babff
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894097909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1894097 909 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2272690301
Short name	T148
Test name
Test status
Simulation time	39167617 ps
CPU time	2.53 seconds
Started	Aug 14 05:12:23 PM PDT 24
Finished	Aug 14 05:12:26 PM PDT 24
Peak memory	217296 kb
Host	smart-f5ef1b84-2eb1-4916-93f8-09149f50b02f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272690301 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.2272690301 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.1541100259
Short name	T181
Test name
Test status
Simulation time	30714723 ps
CPU time	1.13 seconds
Started	Aug 14 05:12:23 PM PDT 24
Finished	Aug 14 05:12:24 PM PDT 24
Peak memory	206528 kb
Host	smart-37dcd30b-fc73-4ca5-bf1b-33281eb07753
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541100259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.1541100259 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.2495883198
Short name	T81
Test name
Test status
Simulation time	15811162 ps
CPU time	0.77 seconds
Started	Aug 14 05:12:23 PM PDT 24
Finished	Aug 14 05:12:24 PM PDT 24
Peak memory	206488 kb
Host	smart-58c7ee84-130d-48b5-af42-b48aae2becfc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495883198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2495883198 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2271107650
Short name	T33
Test name
Test status
Simulation time	106638693 ps
CPU time	1.22 seconds
Started	Aug 14 05:12:22 PM PDT 24
Finished	Aug 14 05:12:23 PM PDT 24
Peak memory	214940 kb
Host	smart-6b21c135-66df-4e65-a7fd-db76f86228f0
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271107650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.2271107650 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.3655905061
Short name	T200
Test name
Test status
Simulation time	14253045 ps
CPU time	0.69 seconds
Started	Aug 14 05:12:22 PM PDT 24
Finished	Aug 14 05:12:23 PM PDT 24
Peak memory	206516 kb
Host	smart-de8d43d7-6b05-4c3b-ac0f-0bdca3b1c731
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655905061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3655905061 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1121478685
Short name	T56
Test name
Test status
Simulation time	59856943 ps
CPU time	1.64 seconds
Started	Aug 14 05:12:22 PM PDT 24
Finished	Aug 14 05:12:24 PM PDT 24
Peak memory	215236 kb
Host	smart-857ff55b-8efe-4a95-b810-ae5efa609fb3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121478685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.1121478685 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3713230792
Short name	T27
Test name
Test status
Simulation time	110720123 ps
CPU time	1.47 seconds
Started	Aug 14 05:12:21 PM PDT 24
Finished	Aug 14 05:12:23 PM PDT 24
Peak memory	215356 kb
Host	smart-10490640-9f4c-42a3-ac7f-5a44a906e316
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713230792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.3713230792 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.877411225
Short name	T142
Test name
Test status
Simulation time	360352838 ps
CPU time	2.12 seconds
Started	Aug 14 05:12:22 PM PDT 24
Finished	Aug 14 05:12:24 PM PDT 24
Peak memory	215440 kb
Host	smart-7877c7ae-8ff2-4b7b-972f-0792dac2f029
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877411225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_ shadow_reg_errors_with_csr_rw.877411225 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.688498658
Short name	T14
Test name
Test status
Simulation time	621326739 ps
CPU time	1.97 seconds
Started	Aug 14 05:12:20 PM PDT 24
Finished	Aug 14 05:12:22 PM PDT 24
Peak memory	215028 kb
Host	smart-4b432e8a-2253-40fa-af37-6e28dee94867
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688498658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.688498658 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1823491364
Short name	T74
Test name
Test status
Simulation time	557083708 ps
CPU time	2.98 seconds
Started	Aug 14 05:12:21 PM PDT 24
Finished	Aug 14 05:12:24 PM PDT 24
Peak memory	215000 kb
Host	smart-9febebe9-b5de-43a9-823c-a39aac9a47fa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823491364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.18234 91364 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2487386245
Short name	T58
Test name
Test status
Simulation time	260286641 ps
CPU time	4.26 seconds
Started	Aug 14 05:12:25 PM PDT 24
Finished	Aug 14 05:12:30 PM PDT 24
Peak memory	206684 kb
Host	smart-0919e0f0-3baf-4d2a-86e5-268877e9b5ca
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487386245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2487386 245 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2686949620
Short name	T215
Test name
Test status
Simulation time	1313578243 ps
CPU time	19.31 seconds
Started	Aug 14 05:12:25 PM PDT 24
Finished	Aug 14 05:12:45 PM PDT 24
Peak memory	206660 kb
Host	smart-0d55810e-525f-49f4-a49b-1bd80f6de8a2
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686949620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2686949 620 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2870270628
Short name	T8
Test name
Test status
Simulation time	14864078 ps
CPU time	0.96 seconds
Started	Aug 14 05:12:23 PM PDT 24
Finished	Aug 14 05:12:24 PM PDT 24
Peak memory	206440 kb
Host	smart-48df4eaa-a67c-40cd-845f-1851ccdfd328
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870270628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2870270 628 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2875383817
Short name	T18
Test name
Test status
Simulation time	191972682 ps
CPU time	1.76 seconds
Started	Aug 14 05:12:29 PM PDT 24
Finished	Aug 14 05:12:31 PM PDT 24
Peak memory	223192 kb
Host	smart-0be0c419-feac-4ec0-aa70-f4c3ffd5cb33
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875383817 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.2875383817 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.2432842532
Short name	T1
Test name
Test status
Simulation time	15945685 ps
CPU time	1.11 seconds
Started	Aug 14 05:12:25 PM PDT 24
Finished	Aug 14 05:12:26 PM PDT 24
Peak memory	214936 kb
Host	smart-5b5c00e0-d8a7-4d84-a0c0-7fa3ecf33a84
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432842532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2432842532 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.2823325729
Short name	T162
Test name
Test status
Simulation time	44267170 ps
CPU time	0.73 seconds
Started	Aug 14 05:12:25 PM PDT 24
Finished	Aug 14 05:12:26 PM PDT 24
Peak memory	206488 kb
Host	smart-21a4558e-f164-4aca-9a31-1f5ab17a03e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823325729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2823325729 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3683243588
Short name	T45
Test name
Test status
Simulation time	109703890 ps
CPU time	1.18 seconds
Started	Aug 14 05:12:26 PM PDT 24
Finished	Aug 14 05:12:27 PM PDT 24
Peak memory	214808 kb
Host	smart-31e0508a-cafd-4da1-a9e1-4319df208f8e
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683243588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.3683243588 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.1704048083
Short name	T172
Test name
Test status
Simulation time	12398642 ps
CPU time	0.73 seconds
Started	Aug 14 05:12:21 PM PDT 24
Finished	Aug 14 05:12:22 PM PDT 24
Peak memory	206668 kb
Host	smart-3c78da82-9cf3-44a0-bfe0-a953309aabae
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704048083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1704048083 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3999487859
Short name	T149
Test name
Test status
Simulation time	144317695 ps
CPU time	1.42 seconds
Started	Aug 14 05:12:23 PM PDT 24
Finished	Aug 14 05:12:25 PM PDT 24
Peak memory	215236 kb
Host	smart-e9488d68-27c4-419a-9a12-cf0d0bb5a155
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999487859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr _outstanding.3999487859 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2383344929
Short name	T34
Test name
Test status
Simulation time	52493675 ps
CPU time	1.41 seconds
Started	Aug 14 05:12:23 PM PDT 24
Finished	Aug 14 05:12:25 PM PDT 24
Peak memory	215440 kb
Host	smart-f727f1cc-687c-44ca-a8aa-f93e6f59a85d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383344929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_ errors.2383344929 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2658209495
Short name	T123
Test name
Test status
Simulation time	47144713 ps
CPU time	1.87 seconds
Started	Aug 14 05:12:22 PM PDT 24
Finished	Aug 14 05:12:24 PM PDT 24
Peak memory	215368 kb
Host	smart-64fe768f-7783-425d-8eb4-461702bac7f3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658209495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac _shadow_reg_errors_with_csr_rw.2658209495 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.306568100
Short name	T49
Test name
Test status
Simulation time	185300728 ps
CPU time	2.74 seconds
Started	Aug 14 05:12:23 PM PDT 24
Finished	Aug 14 05:12:26 PM PDT 24
Peak memory	217752 kb
Host	smart-ece59231-dc62-49fe-9099-1d3f24148c08
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306568100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.306568 100 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2305641347
Short name	T157
Test name
Test status
Simulation time	42833708 ps
CPU time	1.59 seconds
Started	Aug 14 05:12:58 PM PDT 24
Finished	Aug 14 05:12:59 PM PDT 24
Peak memory	222744 kb
Host	smart-af2d3da6-4ac0-4b19-b675-3aca9dad1e8f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305641347 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.2305641347 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3305726559
Short name	T95
Test name
Test status
Simulation time	89619679 ps
CPU time	0.92 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	206444 kb
Host	smart-633c9a49-edda-4941-8ea0-7167c7fedd8b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305726559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.3305726559 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.2616232201
Short name	T106
Test name
Test status
Simulation time	53105914 ps
CPU time	0.78 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:56 PM PDT 24
Peak memory	206496 kb
Host	smart-3b94af13-91b3-4d1c-be8c-65fffb216d2f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616232201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2616232201 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3384450115
Short name	T158
Test name
Test status
Simulation time	76249324 ps
CPU time	1.39 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:58 PM PDT 24
Peak memory	215240 kb
Host	smart-17a4c6db-4452-4b99-9999-167f5028248d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384450115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.3384450115 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1057261092
Short name	T186
Test name
Test status
Simulation time	21028710 ps
CPU time	0.91 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	206644 kb
Host	smart-af3568a2-077b-4462-8775-600e2ca77c17
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057261092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg _errors.1057261092 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3212860467
Short name	T37
Test name
Test status
Simulation time	109934305 ps
CPU time	1.62 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	215200 kb
Host	smart-1ff8ea2a-17d5-40ac-b599-c888fdd51a87
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212860467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma c_shadow_reg_errors_with_csr_rw.3212860467 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.255391978
Short name	T53
Test name
Test status
Simulation time	149016222 ps
CPU time	2.89 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:59 PM PDT 24
Peak memory	215044 kb
Host	smart-4a6d99ec-3b3a-4aeb-ae65-a902075dff11
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255391978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.25539 1978 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1452006645
Short name	T140
Test name
Test status
Simulation time	33997812 ps
CPU time	2.15 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	223188 kb
Host	smart-c529c92f-d389-459b-a596-c7116cf3f6cd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452006645 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1452006645 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2468068851
Short name	T212
Test name
Test status
Simulation time	13267831 ps
CPU time	0.92 seconds
Started	Aug 14 05:12:57 PM PDT 24
Finished	Aug 14 05:12:58 PM PDT 24
Peak memory	206512 kb
Host	smart-7c3066ab-1587-47a7-b08f-fa706d966ece
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468068851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2468068851 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.751934580
Short name	T101
Test name
Test status
Simulation time	43589999 ps
CPU time	0.75 seconds
Started	Aug 14 05:12:59 PM PDT 24
Finished	Aug 14 05:13:00 PM PDT 24
Peak memory	206492 kb
Host	smart-e5a60c59-01aa-4571-8f38-db2891f47637
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751934580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.751934580 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.4115111126
Short name	T117
Test name
Test status
Simulation time	79085704 ps
CPU time	1.43 seconds
Started	Aug 14 05:12:57 PM PDT 24
Finished	Aug 14 05:12:58 PM PDT 24
Peak memory	214924 kb
Host	smart-5100426f-a8e1-44f5-a335-98336ab6c6a3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115111126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs r_outstanding.4115111126 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2026302877
Short name	T124
Test name
Test status
Simulation time	28228108 ps
CPU time	1.05 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	215368 kb
Host	smart-db929848-ca7f-48fe-975b-0ad4cbf90697
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026302877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg _errors.2026302877 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2223815001
Short name	T61
Test name
Test status
Simulation time	50760506 ps
CPU time	1.54 seconds
Started	Aug 14 05:12:54 PM PDT 24
Finished	Aug 14 05:12:56 PM PDT 24
Peak memory	223684 kb
Host	smart-76fde940-68b6-4b47-a11a-09620628114d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223815001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma c_shadow_reg_errors_with_csr_rw.2223815001 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2455345424
Short name	T201
Test name
Test status
Simulation time	263556777 ps
CPU time	1.91 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:58 PM PDT 24
Peak memory	215000 kb
Host	smart-9bae59ea-126a-4362-be98-c9aa2e11d9e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455345424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2455345424 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1089330791
Short name	T160
Test name
Test status
Simulation time	295542043 ps
CPU time	2.4 seconds
Started	Aug 14 05:13:05 PM PDT 24
Finished	Aug 14 05:13:07 PM PDT 24
Peak memory	223244 kb
Host	smart-a7c5e88c-745b-47d2-9cbb-2035d61f8f18
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089330791 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1089330791 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.3049047418
Short name	T152
Test name
Test status
Simulation time	22861911 ps
CPU time	0.96 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:56 PM PDT 24
Peak memory	206460 kb
Host	smart-6d616142-f483-441e-aaaf-033ea2c0bac4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049047418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3049047418 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.1031308027
Short name	T174
Test name
Test status
Simulation time	15525824 ps
CPU time	0.78 seconds
Started	Aug 14 05:12:57 PM PDT 24
Finished	Aug 14 05:12:58 PM PDT 24
Peak memory	206508 kb
Host	smart-3fb3ba41-116b-4bfb-a1c7-786dfa66e88f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031308027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1031308027 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.680631092
Short name	T109
Test name
Test status
Simulation time	134126988 ps
CPU time	2.05 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	215004 kb
Host	smart-db6401a7-e486-4b1c-9c97-44f0ff1245c6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680631092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr _outstanding.680631092 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.936049541
Short name	T32
Test name
Test status
Simulation time	265721183 ps
CPU time	1.63 seconds
Started	Aug 14 05:13:01 PM PDT 24
Finished	Aug 14 05:13:02 PM PDT 24
Peak memory	214992 kb
Host	smart-abcdee00-3df9-4fe8-876c-1d2500642850
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936049541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac _shadow_reg_errors_with_csr_rw.936049541 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.2553857287
Short name	T178
Test name
Test status
Simulation time	200773469 ps
CPU time	1.89 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	215040 kb
Host	smart-c47bff7a-b885-4f8b-865e-49248477842f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553857287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2553857287 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3020419559
Short name	T89
Test name
Test status
Simulation time	162163940 ps
CPU time	2.82 seconds
Started	Aug 14 05:12:57 PM PDT 24
Finished	Aug 14 05:13:00 PM PDT 24
Peak memory	214996 kb
Host	smart-418cccfc-3d89-40d5-bae0-d60b1bc176ec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020419559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3020 419559 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1166481338
Short name	T12
Test name
Test status
Simulation time	55523287 ps
CPU time	1.7 seconds
Started	Aug 14 05:13:11 PM PDT 24
Finished	Aug 14 05:13:12 PM PDT 24
Peak memory	215016 kb
Host	smart-001e847b-5c15-4f45-82d5-29a2a871831c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166481338 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.1166481338 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.4125085041
Short name	T194
Test name
Test status
Simulation time	57524065 ps
CPU time	1.18 seconds
Started	Aug 14 05:13:05 PM PDT 24
Finished	Aug 14 05:13:06 PM PDT 24
Peak memory	206748 kb
Host	smart-7c171c3e-a002-4220-962b-7734837d854b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125085041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.4125085041 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2346453150
Short name	T143
Test name
Test status
Simulation time	416170226 ps
CPU time	2.17 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	215140 kb
Host	smart-c9a3d951-0121-43b0-b762-53144f2fd25d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346453150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs r_outstanding.2346453150 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1353777231
Short name	T9
Test name
Test status
Simulation time	103167112 ps
CPU time	1.06 seconds
Started	Aug 14 05:13:05 PM PDT 24
Finished	Aug 14 05:13:06 PM PDT 24
Peak memory	215060 kb
Host	smart-f4014b9e-4315-4b2d-ab44-b890ccb88b93
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353777231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.1353777231 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3657440333
Short name	T57
Test name
Test status
Simulation time	498684620 ps
CPU time	2.9 seconds
Started	Aug 14 05:13:04 PM PDT 24
Finished	Aug 14 05:13:07 PM PDT 24
Peak memory	223608 kb
Host	smart-22702cbe-7950-4b01-98e5-d023a6d26f10
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657440333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.3657440333 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1684712362
Short name	T76
Test name
Test status
Simulation time	226291777 ps
CPU time	3.27 seconds
Started	Aug 14 05:13:04 PM PDT 24
Finished	Aug 14 05:13:07 PM PDT 24
Peak memory	215008 kb
Host	smart-13899014-c726-4dd6-a54d-9d8a5b3c2e65
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684712362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1684712362 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3360599373
Short name	T92
Test name
Test status
Simulation time	1000577001 ps
CPU time	2.69 seconds
Started	Aug 14 05:13:09 PM PDT 24
Finished	Aug 14 05:13:12 PM PDT 24
Peak memory	217472 kb
Host	smart-d8154821-34fb-4e7c-ba1a-c502c51aa391
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360599373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3360 599373 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.68205543
Short name	T71
Test name
Test status
Simulation time	94693281 ps
CPU time	1.62 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	222760 kb
Host	smart-bc9ffdc8-323d-4b63-bd01-d9fa81665b7d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68205543 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.68205543 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.3914757148
Short name	T40
Test name
Test status
Simulation time	72301233 ps
CPU time	0.93 seconds
Started	Aug 14 05:13:05 PM PDT 24
Finished	Aug 14 05:13:06 PM PDT 24
Peak memory	206512 kb
Host	smart-1802f6ca-ff32-4eb9-ba01-baed91fa9551
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914757148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.3914757148 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.4051562536
Short name	T129
Test name
Test status
Simulation time	15960159 ps
CPU time	0.77 seconds
Started	Aug 14 05:13:09 PM PDT 24
Finished	Aug 14 05:13:10 PM PDT 24
Peak memory	206496 kb
Host	smart-2f5b7167-1439-4964-ae42-f9017ceafa72
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051562536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.4051562536 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2271370981
Short name	T120
Test name
Test status
Simulation time	104113460 ps
CPU time	2.54 seconds
Started	Aug 14 05:13:08 PM PDT 24
Finished	Aug 14 05:13:11 PM PDT 24
Peak memory	215320 kb
Host	smart-538e600e-9962-4b01-8b52-b3165ec4dccb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271370981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs r_outstanding.2271370981 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.691425402
Short name	T116
Test name
Test status
Simulation time	52292462 ps
CPU time	1.25 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:07 PM PDT 24
Peak memory	215712 kb
Host	smart-6cbc9c8e-dc23-4633-b306-6c780516a36e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691425402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_ errors.691425402 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.255879292
Short name	T47
Test name
Test status
Simulation time	26736082 ps
CPU time	1.59 seconds
Started	Aug 14 05:13:10 PM PDT 24
Finished	Aug 14 05:13:12 PM PDT 24
Peak memory	216836 kb
Host	smart-125d5f46-3333-494f-8097-abf72d05af76
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255879292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.255879292 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1691844906
Short name	T195
Test name
Test status
Simulation time	266499738 ps
CPU time	2.37 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	216092 kb
Host	smart-eaab5f52-8ccb-482e-bc60-bc331110a553
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691844906 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1691844906 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.3735844849
Short name	T28
Test name
Test status
Simulation time	24704447 ps
CPU time	0.93 seconds
Started	Aug 14 05:13:09 PM PDT 24
Finished	Aug 14 05:13:10 PM PDT 24
Peak memory	206444 kb
Host	smart-3f1ec73a-e8b7-4ee1-854b-e7211a6fddd6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735844849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3735844849 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.3126913153
Short name	T85
Test name
Test status
Simulation time	42321961 ps
CPU time	0.75 seconds
Started	Aug 14 05:13:07 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	206492 kb
Host	smart-79562cc2-fabd-41f2-879f-3862d7857007
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126913153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3126913153 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.4070317831
Short name	T154
Test name
Test status
Simulation time	260155984 ps
CPU time	1.69 seconds
Started	Aug 14 05:13:08 PM PDT 24
Finished	Aug 14 05:13:10 PM PDT 24
Peak memory	215364 kb
Host	smart-b77ea0ce-ad3e-406a-8f0d-161a0a7155bc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070317831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs r_outstanding.4070317831 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3864391044
Short name	T213
Test name
Test status
Simulation time	295707026 ps
CPU time	1.11 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:07 PM PDT 24
Peak memory	215460 kb
Host	smart-45775537-af89-4e5b-9288-3bd9a9a4bee0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864391044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.3864391044 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3681320284
Short name	T51
Test name
Test status
Simulation time	366371587 ps
CPU time	2.59 seconds
Started	Aug 14 05:13:05 PM PDT 24
Finished	Aug 14 05:13:07 PM PDT 24
Peak memory	215504 kb
Host	smart-cc4d57c0-d651-4fd2-ba9b-118bd065aab7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681320284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma c_shadow_reg_errors_with_csr_rw.3681320284 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.3327607277
Short name	T203
Test name
Test status
Simulation time	121008155 ps
CPU time	3.52 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:10 PM PDT 24
Peak memory	214988 kb
Host	smart-b93122a4-e413-4611-afcf-db42bed985bc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327607277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3327607277 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2429176123
Short name	T94
Test name
Test status
Simulation time	362038541 ps
CPU time	4.13 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:10 PM PDT 24
Peak memory	215224 kb
Host	smart-c6f505f1-2a87-4ff6-a133-7dedbc66c34d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429176123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2429 176123 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1526143473
Short name	T5
Test name
Test status
Simulation time	58908255 ps
CPU time	2.1 seconds
Started	Aug 14 05:13:09 PM PDT 24
Finished	Aug 14 05:13:12 PM PDT 24
Peak memory	217096 kb
Host	smart-b5ecae30-4820-458e-8b17-0f72ca3857de
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526143473 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.1526143473 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.290105094
Short name	T170
Test name
Test status
Simulation time	56863028 ps
CPU time	0.91 seconds
Started	Aug 14 05:13:08 PM PDT 24
Finished	Aug 14 05:13:09 PM PDT 24
Peak memory	206536 kb
Host	smart-03bac779-8d53-43ca-8dc5-9e8886d3e3be
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290105094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.290105094 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.2812362898
Short name	T127
Test name
Test status
Simulation time	36608590 ps
CPU time	0.73 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:07 PM PDT 24
Peak memory	206516 kb
Host	smart-08a5c6e7-7bc0-4edb-a59b-509322fbab1e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812362898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2812362898 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.675638326
Short name	T41
Test name
Test status
Simulation time	96781559 ps
CPU time	2.64 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:09 PM PDT 24
Peak memory	215444 kb
Host	smart-6f47031d-4b52-47ce-bb38-62fab21acc39
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675638326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr _outstanding.675638326 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4092706916
Short name	T103
Test name
Test status
Simulation time	42808008 ps
CPU time	1.27 seconds
Started	Aug 14 05:13:08 PM PDT 24
Finished	Aug 14 05:13:10 PM PDT 24
Peak memory	215424 kb
Host	smart-349014e0-8160-4ec5-b4e1-69d83f43864c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092706916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg _errors.4092706916 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.874800372
Short name	T4
Test name
Test status
Simulation time	72936434 ps
CPU time	2.02 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:09 PM PDT 24
Peak memory	215468 kb
Host	smart-3db42b4a-98fc-4478-ad0a-55324cee3703
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874800372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac _shadow_reg_errors_with_csr_rw.874800372 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2392663873
Short name	T141
Test name
Test status
Simulation time	428685828 ps
CPU time	2.78 seconds
Started	Aug 14 05:13:05 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	217956 kb
Host	smart-b28dc49c-40f1-4a85-850c-1d4fe29c975d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392663873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2392 663873 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3508864098
Short name	T72
Test name
Test status
Simulation time	94902523 ps
CPU time	1.94 seconds
Started	Aug 14 05:13:07 PM PDT 24
Finished	Aug 14 05:13:09 PM PDT 24
Peak memory	216048 kb
Host	smart-438571a3-6fe4-4532-aa0a-413f8da3f01a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508864098 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.3508864098 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.3155314265
Short name	T211
Test name
Test status
Simulation time	61386607 ps
CPU time	1.13 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:07 PM PDT 24
Peak memory	214924 kb
Host	smart-68b9761d-4b6e-4f3c-8b76-a7b71644bfa8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155314265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.3155314265 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.486468955
Short name	T171
Test name
Test status
Simulation time	36488071 ps
CPU time	0.76 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:07 PM PDT 24
Peak memory	206504 kb
Host	smart-87dcb634-324f-4bd8-bb14-c1f9ef6c5da4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486468955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.486468955 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1254997124
Short name	T146
Test name
Test status
Simulation time	73964410 ps
CPU time	2.07 seconds
Started	Aug 14 05:13:08 PM PDT 24
Finished	Aug 14 05:13:10 PM PDT 24
Peak memory	214880 kb
Host	smart-055fa547-5be3-4685-8c46-db3fa10a9c7a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254997124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.1254997124 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1375427244
Short name	T156
Test name
Test status
Simulation time	80602080 ps
CPU time	1.76 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	215364 kb
Host	smart-dfaaa39e-15d6-476d-b48b-88ee39c3e969
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375427244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg _errors.1375427244 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.1387803935
Short name	T16
Test name
Test status
Simulation time	129571093 ps
CPU time	3.13 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:09 PM PDT 24
Peak memory	214892 kb
Host	smart-e68540d6-9622-4e46-84f1-e09c2bba9546
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387803935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1387803935 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3557767390
Short name	T209
Test name
Test status
Simulation time	211776816 ps
CPU time	3.08 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:10 PM PDT 24
Peak memory	207008 kb
Host	smart-59596d37-6e00-4add-bb65-78516560d25d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557767390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3557 767390 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3124068838
Short name	T205
Test name
Test status
Simulation time	113704903 ps
CPU time	1.5 seconds
Started	Aug 14 05:13:04 PM PDT 24
Finished	Aug 14 05:13:06 PM PDT 24
Peak memory	215024 kb
Host	smart-c2f8695f-d7c5-44de-bd78-9fb957c91878
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124068838 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.3124068838 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.640752857
Short name	T207
Test name
Test status
Simulation time	21106555 ps
CPU time	0.95 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:07 PM PDT 24
Peak memory	206500 kb
Host	smart-31717911-4806-4eee-95f3-6c3a3d392988
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640752857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.640752857 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.819370701
Short name	T119
Test name
Test status
Simulation time	158886233 ps
CPU time	0.8 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:06 PM PDT 24
Peak memory	206448 kb
Host	smart-2623a6f9-7b55-4911-ae4d-a82fd877b6be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819370701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.819370701 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2258602892
Short name	T114
Test name
Test status
Simulation time	79398925 ps
CPU time	2.01 seconds
Started	Aug 14 05:13:09 PM PDT 24
Finished	Aug 14 05:13:11 PM PDT 24
Peak memory	215016 kb
Host	smart-69e05ed9-60c1-43f2-b6d7-ff06b5c535e9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258602892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.2258602892 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3326223535
Short name	T63
Test name
Test status
Simulation time	40412728 ps
CPU time	1.28 seconds
Started	Aug 14 05:13:05 PM PDT 24
Finished	Aug 14 05:13:06 PM PDT 24
Peak memory	215512 kb
Host	smart-aa3fa769-ab72-4429-831a-70d7dc392d0e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326223535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.3326223535 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1796355909
Short name	T121
Test name
Test status
Simulation time	289368990 ps
CPU time	2.05 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	223316 kb
Host	smart-7e9be5e5-fffa-4d44-801d-a702ae06b442
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796355909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.1796355909 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.1283520469
Short name	T75
Test name
Test status
Simulation time	46537523 ps
CPU time	1.54 seconds
Started	Aug 14 05:13:09 PM PDT 24
Finished	Aug 14 05:13:11 PM PDT 24
Peak memory	215060 kb
Host	smart-5bd04374-7eb4-4562-8765-734893796fb6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283520469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1283520469 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.317082571
Short name	T90
Test name
Test status
Simulation time	1047860086 ps
CPU time	5.2 seconds
Started	Aug 14 05:13:07 PM PDT 24
Finished	Aug 14 05:13:12 PM PDT 24
Peak memory	215108 kb
Host	smart-29473aa3-b484-4e3b-8bed-24f18b20faa4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317082571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.31708 2571 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1214315540
Short name	T15
Test name
Test status
Simulation time	446874329 ps
CPU time	1.87 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	215620 kb
Host	smart-26a53902-8803-4b8f-91ba-6e9334f14f64
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214315540 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.1214315540 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.373787616
Short name	T46
Test name
Test status
Simulation time	46591172 ps
CPU time	1.1 seconds
Started	Aug 14 05:13:07 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	206740 kb
Host	smart-b5da1a2d-afcc-46a1-a600-bc99c70fb995
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373787616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.373787616 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.2856218643
Short name	T166
Test name
Test status
Simulation time	15580098 ps
CPU time	0.78 seconds
Started	Aug 14 05:13:07 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	206496 kb
Host	smart-1952713c-ff2a-4409-a8ac-02b3075e0552
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856218643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2856218643 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1993933161
Short name	T55
Test name
Test status
Simulation time	92224050 ps
CPU time	2.46 seconds
Started	Aug 14 05:13:06 PM PDT 24
Finished	Aug 14 05:13:09 PM PDT 24
Peak memory	215072 kb
Host	smart-14138431-811d-426e-a98c-8c2019998565
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993933161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs r_outstanding.1993933161 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4277981636
Short name	T151
Test name
Test status
Simulation time	59414777 ps
CPU time	1.05 seconds
Started	Aug 14 05:13:07 PM PDT 24
Finished	Aug 14 05:13:08 PM PDT 24
Peak memory	215480 kb
Host	smart-63db80f7-05d6-41c7-8a7e-7f5dbad86450
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277981636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.4277981636 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3558931444
Short name	T126
Test name
Test status
Simulation time	120373053 ps
CPU time	1.97 seconds
Started	Aug 14 05:13:07 PM PDT 24
Finished	Aug 14 05:13:09 PM PDT 24
Peak memory	223264 kb
Host	smart-c875fd34-75a1-4391-9ca5-d863fea5c693
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558931444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma c_shadow_reg_errors_with_csr_rw.3558931444 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.772691630
Short name	T73
Test name
Test status
Simulation time	245406775 ps
CPU time	3.64 seconds
Started	Aug 14 05:13:07 PM PDT 24
Finished	Aug 14 05:13:11 PM PDT 24
Peak memory	215016 kb
Host	smart-dcd1ae6a-ac7e-4148-87ed-6944be8a5dba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772691630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.772691630 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.804980316
Short name	T24
Test name
Test status
Simulation time	374999860 ps
CPU time	4.57 seconds
Started	Aug 14 05:13:07 PM PDT 24
Finished	Aug 14 05:13:12 PM PDT 24
Peak memory	214964 kb
Host	smart-034edb0b-e69b-42c9-a07f-1bc4de599ac8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804980316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.80498 0316 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2858714595
Short name	T155
Test name
Test status
Simulation time	203112521 ps
CPU time	4.94 seconds
Started	Aug 14 05:12:42 PM PDT 24
Finished	Aug 14 05:12:47 PM PDT 24
Peak memory	206696 kb
Host	smart-9c9fe233-a0c9-4136-9e77-381ebc670447
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858714595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2858714 595 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3928485454
Short name	T29
Test name
Test status
Simulation time	1133021165 ps
CPU time	15.52 seconds
Started	Aug 14 05:12:30 PM PDT 24
Finished	Aug 14 05:12:46 PM PDT 24
Peak memory	206768 kb
Host	smart-eb9cc17c-ea4d-43a0-833c-7619c4606a92
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928485454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.3928485 454 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3569333392
Short name	T137
Test name
Test status
Simulation time	36234239 ps
CPU time	1.17 seconds
Started	Aug 14 05:12:29 PM PDT 24
Finished	Aug 14 05:12:30 PM PDT 24
Peak memory	206948 kb
Host	smart-66033b6a-6644-47f7-85c4-e92973dcce55
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569333392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3569333 392 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3903574590
Short name	T136
Test name
Test status
Simulation time	55405996 ps
CPU time	1.8 seconds
Started	Aug 14 05:12:39 PM PDT 24
Finished	Aug 14 05:12:41 PM PDT 24
Peak memory	223240 kb
Host	smart-110afdb0-14d7-4f7c-a955-1b0ced9d2640
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903574590 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.3903574590 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.3204656863
Short name	T204
Test name
Test status
Simulation time	24800361 ps
CPU time	0.91 seconds
Started	Aug 14 05:12:30 PM PDT 24
Finished	Aug 14 05:12:31 PM PDT 24
Peak memory	206444 kb
Host	smart-de7b4e7b-5207-490b-a55d-4242fa90ce3b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204656863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3204656863 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.2062167778
Short name	T133
Test name
Test status
Simulation time	13258549 ps
CPU time	0.77 seconds
Started	Aug 14 05:12:31 PM PDT 24
Finished	Aug 14 05:12:32 PM PDT 24
Peak memory	206408 kb
Host	smart-ba30feb4-4957-4299-a7a8-3883d0cba323
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062167778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2062167778 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1642172443
Short name	T17
Test name
Test status
Simulation time	271218379 ps
CPU time	1.34 seconds
Started	Aug 14 05:12:38 PM PDT 24
Finished	Aug 14 05:12:40 PM PDT 24
Peak memory	214876 kb
Host	smart-362810a0-9f6b-446a-8412-7c087c73d907
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642172443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.1642172443 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.577213531
Short name	T208
Test name
Test status
Simulation time	19495629 ps
CPU time	0.72 seconds
Started	Aug 14 05:12:33 PM PDT 24
Finished	Aug 14 05:12:34 PM PDT 24
Peak memory	206472 kb
Host	smart-d037ca53-e697-47c5-8751-24f1dc2f0f5c
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577213531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.577213531 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3816868790
Short name	T79
Test name
Test status
Simulation time	111113603 ps
CPU time	1.67 seconds
Started	Aug 14 05:12:40 PM PDT 24
Finished	Aug 14 05:12:42 PM PDT 24
Peak memory	215320 kb
Host	smart-a9c92620-34ba-4c1e-8e27-0f3e3532af70
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816868790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr _outstanding.3816868790 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3505670302
Short name	T198
Test name
Test status
Simulation time	66895196 ps
CPU time	0.95 seconds
Started	Aug 14 05:12:32 PM PDT 24
Finished	Aug 14 05:12:33 PM PDT 24
Peak memory	206868 kb
Host	smart-defdfeee-f2aa-429f-ad3f-858d95914c74
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505670302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_ errors.3505670302 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.704377007
Short name	T128
Test name
Test status
Simulation time	181802154 ps
CPU time	2.6 seconds
Started	Aug 14 05:12:32 PM PDT 24
Finished	Aug 14 05:12:34 PM PDT 24
Peak memory	223500 kb
Host	smart-ce44fa45-a400-4a95-a781-c8bd2ecbebb0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704377007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_ shadow_reg_errors_with_csr_rw.704377007 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.1654348438
Short name	T70
Test name
Test status
Simulation time	389540917 ps
CPU time	2.56 seconds
Started	Aug 14 05:12:36 PM PDT 24
Finished	Aug 14 05:12:39 PM PDT 24
Peak memory	215000 kb
Host	smart-21e6748b-f043-402d-b91b-c99938bff84e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654348438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1654348438 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3108009044
Short name	T214
Test name
Test status
Simulation time	45296602 ps
CPU time	0.8 seconds
Started	Aug 14 05:13:15 PM PDT 24
Finished	Aug 14 05:13:16 PM PDT 24
Peak memory	206516 kb
Host	smart-ceac4a9d-15e2-4faf-bf33-fb4e7de960b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108009044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3108009044 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.240838591
Short name	T50
Test name
Test status
Simulation time	13288594 ps
CPU time	0.78 seconds
Started	Aug 14 05:13:16 PM PDT 24
Finished	Aug 14 05:13:17 PM PDT 24
Peak memory	206500 kb
Host	smart-c6d127d6-a1dc-48e1-bbf0-c3453aa3ea1d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240838591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.240838591 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.2813435721
Short name	T164
Test name
Test status
Simulation time	13562138 ps
CPU time	0.76 seconds
Started	Aug 14 05:13:15 PM PDT 24
Finished	Aug 14 05:13:16 PM PDT 24
Peak memory	206424 kb
Host	smart-b6e5ce5f-c03f-4a67-96e4-a3e1063bf665
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813435721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2813435721 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.2511510926
Short name	T183
Test name
Test status
Simulation time	25733719 ps
CPU time	0.78 seconds
Started	Aug 14 05:13:12 PM PDT 24
Finished	Aug 14 05:13:13 PM PDT 24
Peak memory	206472 kb
Host	smart-114d87b1-b6f3-4b49-80a2-c6373281f28e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511510926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2511510926 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.3107338370
Short name	T189
Test name
Test status
Simulation time	20157635 ps
CPU time	0.74 seconds
Started	Aug 14 05:13:14 PM PDT 24
Finished	Aug 14 05:13:15 PM PDT 24
Peak memory	206496 kb
Host	smart-02ccf555-8bf4-41de-9678-2d47510e2f43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107338370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3107338370 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.767020400
Short name	T199
Test name
Test status
Simulation time	55481208 ps
CPU time	0.78 seconds
Started	Aug 14 05:13:15 PM PDT 24
Finished	Aug 14 05:13:16 PM PDT 24
Peak memory	206460 kb
Host	smart-1545a4d9-c32e-4578-881e-2a2b296f6c5c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767020400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.767020400 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.358638401
Short name	T82
Test name
Test status
Simulation time	22314753 ps
CPU time	0.76 seconds
Started	Aug 14 05:13:13 PM PDT 24
Finished	Aug 14 05:13:14 PM PDT 24
Peak memory	206528 kb
Host	smart-abc0667c-483c-472d-960a-c36e1f6bfeea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358638401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.358638401 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.901920287
Short name	T97
Test name
Test status
Simulation time	40360720 ps
CPU time	0.75 seconds
Started	Aug 14 05:13:14 PM PDT 24
Finished	Aug 14 05:13:15 PM PDT 24
Peak memory	206412 kb
Host	smart-3de85fda-c897-42f9-bb00-5fa6c6cb3e79
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901920287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.901920287 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1581047337
Short name	T104
Test name
Test status
Simulation time	527799286 ps
CPU time	8.52 seconds
Started	Aug 14 05:12:39 PM PDT 24
Finished	Aug 14 05:12:48 PM PDT 24
Peak memory	214948 kb
Host	smart-6c8c3ef8-a475-4c04-8d42-342f4cc3d4d5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581047337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1581047 337 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.338695496
Short name	T122
Test name
Test status
Simulation time	4798315431 ps
CPU time	21.37 seconds
Started	Aug 14 05:12:40 PM PDT 24
Finished	Aug 14 05:13:02 PM PDT 24
Peak memory	214980 kb
Host	smart-13e8b73f-74df-4de6-aa0f-3523ebfff606
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338695496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.33869549 6 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3217951850
Short name	T173
Test name
Test status
Simulation time	25472140 ps
CPU time	0.92 seconds
Started	Aug 14 05:12:41 PM PDT 24
Finished	Aug 14 05:12:42 PM PDT 24
Peak memory	206504 kb
Host	smart-bbbceda1-c44d-4858-b238-bdf0067c8506
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217951850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3217951 850 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.4007498509
Short name	T210
Test name
Test status
Simulation time	79588944 ps
CPU time	1.67 seconds
Started	Aug 14 05:12:40 PM PDT 24
Finished	Aug 14 05:12:42 PM PDT 24
Peak memory	214984 kb
Host	smart-1096820a-ccda-43a1-a931-26eef0490c2d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007498509 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.4007498509 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.3343145357
Short name	T163
Test name
Test status
Simulation time	32099634 ps
CPU time	1.12 seconds
Started	Aug 14 05:12:41 PM PDT 24
Finished	Aug 14 05:12:43 PM PDT 24
Peak memory	214888 kb
Host	smart-42a37b6c-d6c9-4330-9e61-e30bdec2317e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343145357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3343145357 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.3164055756
Short name	T98
Test name
Test status
Simulation time	16226005 ps
CPU time	0.79 seconds
Started	Aug 14 05:12:42 PM PDT 24
Finished	Aug 14 05:12:43 PM PDT 24
Peak memory	206488 kb
Host	smart-46c1f623-afc2-409c-a7cb-9a8dfe3a658b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164055756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3164055756 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.1659854560
Short name	T176
Test name
Test status
Simulation time	13458170 ps
CPU time	0.75 seconds
Started	Aug 14 05:12:38 PM PDT 24
Finished	Aug 14 05:12:39 PM PDT 24
Peak memory	206520 kb
Host	smart-9964aa50-a9b3-472e-9835-c453fd94356d
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659854560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1659854560 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2224110981
Short name	T145
Test name
Test status
Simulation time	411772024 ps
CPU time	2.41 seconds
Started	Aug 14 05:12:39 PM PDT 24
Finished	Aug 14 05:12:42 PM PDT 24
Peak memory	215284 kb
Host	smart-e79c20ae-7745-4525-aebf-50e68f543d23
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224110981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.2224110981 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2693485597
Short name	T175
Test name
Test status
Simulation time	55370350 ps
CPU time	0.82 seconds
Started	Aug 14 05:12:41 PM PDT 24
Finished	Aug 14 05:12:42 PM PDT 24
Peak memory	206676 kb
Host	smart-406a7b1a-9e72-4b76-be0b-0e0658a72774
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693485597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_ errors.2693485597 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.4157866703
Short name	T102
Test name
Test status
Simulation time	56598668 ps
CPU time	1.55 seconds
Started	Aug 14 05:12:40 PM PDT 24
Finished	Aug 14 05:12:41 PM PDT 24
Peak memory	214972 kb
Host	smart-79af3a50-3277-402a-be27-e9b3c77ab846
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157866703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.4157866703 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.2662826523
Short name	T66
Test name
Test status
Simulation time	84133927 ps
CPU time	2.7 seconds
Started	Aug 14 05:12:47 PM PDT 24
Finished	Aug 14 05:12:50 PM PDT 24
Peak memory	215052 kb
Host	smart-fd67d255-5d01-4123-9741-f8ad0cd9af69
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662826523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2662826523 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.600262924
Short name	T39
Test name
Test status
Simulation time	452356943 ps
CPU time	2.67 seconds
Started	Aug 14 05:12:41 PM PDT 24
Finished	Aug 14 05:12:44 PM PDT 24
Peak memory	215028 kb
Host	smart-d6e25e07-8e5a-4545-9eb8-f32d2c0c9ab8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600262924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.600262 924 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.4187715238
Short name	T169
Test name
Test status
Simulation time	15645832 ps
CPU time	0.78 seconds
Started	Aug 14 05:13:17 PM PDT 24
Finished	Aug 14 05:13:18 PM PDT 24
Peak memory	206408 kb
Host	smart-0003fd3b-ab77-405e-a60f-c3d50d7dd072
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187715238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.4187715238 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.2043515484
Short name	T107
Test name
Test status
Simulation time	14517316 ps
CPU time	0.78 seconds
Started	Aug 14 05:13:14 PM PDT 24
Finished	Aug 14 05:13:14 PM PDT 24
Peak memory	206524 kb
Host	smart-e510c398-71b0-44a1-87b0-8dbe33c26349
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043515484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.2043515484 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2719997043
Short name	T11
Test name
Test status
Simulation time	13873113 ps
CPU time	0.77 seconds
Started	Aug 14 05:13:14 PM PDT 24
Finished	Aug 14 05:13:15 PM PDT 24
Peak memory	206500 kb
Host	smart-e9811871-1b22-4941-ac2d-a0000b2b591b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719997043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2719997043 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.130896404
Short name	T138
Test name
Test status
Simulation time	15485293 ps
CPU time	0.76 seconds
Started	Aug 14 05:13:15 PM PDT 24
Finished	Aug 14 05:13:16 PM PDT 24
Peak memory	206496 kb
Host	smart-05cfe1c2-6956-4921-999d-89dcc28db8bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130896404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.130896404 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.1434502410
Short name	T187
Test name
Test status
Simulation time	14080065 ps
CPU time	0.76 seconds
Started	Aug 14 05:13:21 PM PDT 24
Finished	Aug 14 05:13:22 PM PDT 24
Peak memory	206496 kb
Host	smart-476185b6-ca5d-449c-97a7-bd6098ef21bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434502410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1434502410 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.3420213213
Short name	T132
Test name
Test status
Simulation time	36209650 ps
CPU time	0.72 seconds
Started	Aug 14 05:13:17 PM PDT 24
Finished	Aug 14 05:13:18 PM PDT 24
Peak memory	206512 kb
Host	smart-d006be71-976d-458e-895d-6af488319871
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420213213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3420213213 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.3136186522
Short name	T21
Test name
Test status
Simulation time	13296386 ps
CPU time	0.78 seconds
Started	Aug 14 05:13:16 PM PDT 24
Finished	Aug 14 05:13:17 PM PDT 24
Peak memory	206456 kb
Host	smart-9a2adfbd-8fd5-415e-b82c-e6b8e93eb615
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136186522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3136186522 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.2617597874
Short name	T182
Test name
Test status
Simulation time	13203814 ps
CPU time	0.83 seconds
Started	Aug 14 05:13:15 PM PDT 24
Finished	Aug 14 05:13:16 PM PDT 24
Peak memory	206492 kb
Host	smart-73a81a71-a192-4bbb-9af2-595e06c7f755
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617597874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2617597874 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.1229354711
Short name	T159
Test name
Test status
Simulation time	19230311 ps
CPU time	0.78 seconds
Started	Aug 14 05:13:14 PM PDT 24
Finished	Aug 14 05:13:15 PM PDT 24
Peak memory	206444 kb
Host	smart-36c14819-4f6c-44dd-8a1b-5950a4248029
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229354711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1229354711 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.1651336167
Short name	T115
Test name
Test status
Simulation time	15992934 ps
CPU time	0.79 seconds
Started	Aug 14 05:13:16 PM PDT 24
Finished	Aug 14 05:13:16 PM PDT 24
Peak memory	206536 kb
Host	smart-98642f8e-1fdc-4676-9770-1482f0a5ab24
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651336167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1651336167 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.320917745
Short name	T131
Test name
Test status
Simulation time	897213008 ps
CPU time	8.2 seconds
Started	Aug 14 05:12:50 PM PDT 24
Finished	Aug 14 05:12:59 PM PDT 24
Peak memory	214956 kb
Host	smart-e769d2b0-ca0f-4112-9438-dfc28161ea71
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320917745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.32091774 5 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.4033032898
Short name	T191
Test name
Test status
Simulation time	739260476 ps
CPU time	10.54 seconds
Started	Aug 14 05:12:51 PM PDT 24
Finished	Aug 14 05:13:01 PM PDT 24
Peak memory	206692 kb
Host	smart-76f8f49d-325c-4e10-aad6-39549fec81f7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033032898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.4033032 898 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.669232794
Short name	T192
Test name
Test status
Simulation time	112066395 ps
CPU time	1.11 seconds
Started	Aug 14 05:12:41 PM PDT 24
Finished	Aug 14 05:12:43 PM PDT 24
Peak memory	206740 kb
Host	smart-c2b8810c-7ffb-479a-8cbb-63715b060f35
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669232794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.66923279 4 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1702554507
Short name	T68
Test name
Test status
Simulation time	23985887 ps
CPU time	1.48 seconds
Started	Aug 14 05:12:47 PM PDT 24
Finished	Aug 14 05:12:48 PM PDT 24
Peak memory	223172 kb
Host	smart-f5685b1a-ffcd-4dac-843f-7739600ec86d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702554507 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.1702554507 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.50054304
Short name	T22
Test name
Test status
Simulation time	16162785 ps
CPU time	0.94 seconds
Started	Aug 14 05:12:42 PM PDT 24
Finished	Aug 14 05:12:43 PM PDT 24
Peak memory	206436 kb
Host	smart-57a7c3c0-f2d4-4b86-a7fe-4227a9d7c7c5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50054304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.50054304 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3997971613
Short name	T96
Test name
Test status
Simulation time	43067257 ps
CPU time	0.77 seconds
Started	Aug 14 05:12:41 PM PDT 24
Finished	Aug 14 05:12:42 PM PDT 24
Peak memory	206492 kb
Host	smart-50e6c61c-503c-4185-b4ab-336ed6d18067
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997971613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3997971613 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3588659418
Short name	T44
Test name
Test status
Simulation time	58568181 ps
CPU time	1.26 seconds
Started	Aug 14 05:12:39 PM PDT 24
Finished	Aug 14 05:12:40 PM PDT 24
Peak memory	214900 kb
Host	smart-3457c9b4-03c9-48b3-88f0-1361469914e4
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588659418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.3588659418 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.1552165858
Short name	T206
Test name
Test status
Simulation time	31466269 ps
CPU time	0.81 seconds
Started	Aug 14 05:12:39 PM PDT 24
Finished	Aug 14 05:12:40 PM PDT 24
Peak memory	206492 kb
Host	smart-ce322264-a160-4f02-909d-07a0887f04bf
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552165858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1552165858 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.271356215
Short name	T110
Test name
Test status
Simulation time	27022699 ps
CPU time	1.49 seconds
Started	Aug 14 05:12:48 PM PDT 24
Finished	Aug 14 05:12:50 PM PDT 24
Peak memory	215392 kb
Host	smart-0e21f0a1-53fb-4109-ba36-dc0f9abf17c7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271356215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_ outstanding.271356215 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3761603666
Short name	T161
Test name
Test status
Simulation time	62564263 ps
CPU time	1.22 seconds
Started	Aug 14 05:12:41 PM PDT 24
Finished	Aug 14 05:12:43 PM PDT 24
Peak memory	215416 kb
Host	smart-a05388f8-11b1-4362-a47d-cf85ae8113ab
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761603666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.3761603666 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1890138792
Short name	T62
Test name
Test status
Simulation time	249439014 ps
CPU time	1.77 seconds
Started	Aug 14 05:12:39 PM PDT 24
Finished	Aug 14 05:12:41 PM PDT 24
Peak memory	215472 kb
Host	smart-87cb517a-84c9-4334-a244-f3c59b3f8a10
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890138792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.1890138792 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.1000614432
Short name	T13
Test name
Test status
Simulation time	385295196 ps
CPU time	1.97 seconds
Started	Aug 14 05:12:39 PM PDT 24
Finished	Aug 14 05:12:41 PM PDT 24
Peak memory	217544 kb
Host	smart-fa77f40e-4103-4c74-bb88-c2ded69b7a35
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000614432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.1000614432 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.504262862
Short name	T108
Test name
Test status
Simulation time	40417064 ps
CPU time	0.75 seconds
Started	Aug 14 05:13:17 PM PDT 24
Finished	Aug 14 05:13:17 PM PDT 24
Peak memory	206484 kb
Host	smart-6d63ff31-aa6c-474d-9c6b-039904736abf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504262862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.504262862 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.1088588654
Short name	T177
Test name
Test status
Simulation time	14367425 ps
CPU time	0.8 seconds
Started	Aug 14 05:13:15 PM PDT 24
Finished	Aug 14 05:13:16 PM PDT 24
Peak memory	206496 kb
Host	smart-cb2a0117-a3c2-4c13-bbb9-39be04d9ae75
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088588654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1088588654 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.1722795157
Short name	T113
Test name
Test status
Simulation time	22478260 ps
CPU time	0.75 seconds
Started	Aug 14 05:13:13 PM PDT 24
Finished	Aug 14 05:13:14 PM PDT 24
Peak memory	206488 kb
Host	smart-1744db74-f5ac-4f6f-a05f-45f3c72b3ee4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722795157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1722795157 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.4213836389
Short name	T2
Test name
Test status
Simulation time	24798902 ps
CPU time	0.79 seconds
Started	Aug 14 05:13:16 PM PDT 24
Finished	Aug 14 05:13:17 PM PDT 24
Peak memory	206456 kb
Host	smart-47aa0b4d-4c58-418b-8d56-c0f8572b8601
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213836389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.4213836389 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.4066347304
Short name	T134
Test name
Test status
Simulation time	37082146 ps
CPU time	0.75 seconds
Started	Aug 14 05:13:17 PM PDT 24
Finished	Aug 14 05:13:18 PM PDT 24
Peak memory	206408 kb
Host	smart-e857f784-32a4-4e36-8ae5-816e20928ec8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066347304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.4066347304 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.263382138
Short name	T105
Test name
Test status
Simulation time	19026560 ps
CPU time	0.74 seconds
Started	Aug 14 05:13:13 PM PDT 24
Finished	Aug 14 05:13:14 PM PDT 24
Peak memory	206524 kb
Host	smart-14875674-20ec-49e7-8773-468ce2440d76
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263382138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.263382138 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.2438873009
Short name	T99
Test name
Test status
Simulation time	74593583 ps
CPU time	0.84 seconds
Started	Aug 14 05:13:16 PM PDT 24
Finished	Aug 14 05:13:17 PM PDT 24
Peak memory	206516 kb
Host	smart-4fd9c69d-37f9-47ca-b351-5045d97c9313
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438873009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2438873009 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.3559960328
Short name	T35
Test name
Test status
Simulation time	10894468 ps
CPU time	0.72 seconds
Started	Aug 14 05:13:20 PM PDT 24
Finished	Aug 14 05:13:21 PM PDT 24
Peak memory	206496 kb
Host	smart-c4242f36-7b9f-4604-95da-00cb4ffc83d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559960328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3559960328 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.697271745
Short name	T184
Test name
Test status
Simulation time	17346326 ps
CPU time	0.78 seconds
Started	Aug 14 05:13:16 PM PDT 24
Finished	Aug 14 05:13:17 PM PDT 24
Peak memory	206480 kb
Host	smart-46fdede0-06d1-4dd7-8bd5-e40542534d8d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697271745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.697271745 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.2358047082
Short name	T83
Test name
Test status
Simulation time	46779996 ps
CPU time	0.77 seconds
Started	Aug 14 05:13:17 PM PDT 24
Finished	Aug 14 05:13:18 PM PDT 24
Peak memory	206508 kb
Host	smart-6cd425f6-a6bb-483c-89d4-9f4ed9118933
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358047082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2358047082 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2628020490
Short name	T153
Test name
Test status
Simulation time	80983759 ps
CPU time	1.73 seconds
Started	Aug 14 05:12:49 PM PDT 24
Finished	Aug 14 05:12:51 PM PDT 24
Peak memory	223128 kb
Host	smart-7012e679-9d30-4e03-8097-085387d8c17f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628020490 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.2628020490 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.2643023670
Short name	T165
Test name
Test status
Simulation time	93514007 ps
CPU time	1.14 seconds
Started	Aug 14 05:12:48 PM PDT 24
Finished	Aug 14 05:12:50 PM PDT 24
Peak memory	206776 kb
Host	smart-f8857d06-91f8-40b6-960b-a93b3d51f0b9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643023670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2643023670 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.3315207828
Short name	T86
Test name
Test status
Simulation time	50798298 ps
CPU time	0.82 seconds
Started	Aug 14 05:12:49 PM PDT 24
Finished	Aug 14 05:12:50 PM PDT 24
Peak memory	206540 kb
Host	smart-20c4b40c-a808-4fc6-8420-699a46ed0e75
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315207828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3315207828 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3920272
Short name	T130
Test name
Test status
Simulation time	360141615 ps
CPU time	2.5 seconds
Started	Aug 14 05:12:47 PM PDT 24
Finished	Aug 14 05:12:50 PM PDT 24
Peak memory	215276 kb
Host	smart-24cb4e39-68c7-4e8e-83e3-57f9f988af17
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_ou tstanding.3920272 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.373834436
Short name	T36
Test name
Test status
Simulation time	205179052 ps
CPU time	1.31 seconds
Started	Aug 14 05:12:49 PM PDT 24
Finished	Aug 14 05:12:50 PM PDT 24
Peak memory	215432 kb
Host	smart-1a30f81e-aa58-4dcb-ae66-035f392b7dea
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373834436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e rrors.373834436 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2134322455
Short name	T60
Test name
Test status
Simulation time	107045084 ps
CPU time	2.9 seconds
Started	Aug 14 05:12:54 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	215472 kb
Host	smart-e4b6ebf2-a46b-46c9-b858-1935c4aa1a25
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134322455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.2134322455 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.482747907
Short name	T64
Test name
Test status
Simulation time	370821445 ps
CPU time	2.76 seconds
Started	Aug 14 05:12:47 PM PDT 24
Finished	Aug 14 05:12:50 PM PDT 24
Peak memory	215044 kb
Host	smart-ca5eb22e-6332-48c7-9c3a-397ed513e3c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482747907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.482747907 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2218702959
Short name	T93
Test name
Test status
Simulation time	836912916 ps
CPU time	4.75 seconds
Started	Aug 14 05:12:50 PM PDT 24
Finished	Aug 14 05:12:55 PM PDT 24
Peak memory	215008 kb
Host	smart-b6ab3725-e3f9-4bfc-bce0-e478df592086
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218702959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.22187 02959 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3136598471
Short name	T180
Test name
Test status
Simulation time	41864410 ps
CPU time	1.75 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	215512 kb
Host	smart-145b0652-a6c9-4eea-b099-47cc93152893
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136598471 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3136598471 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.1144421337
Short name	T202
Test name
Test status
Simulation time	26516942 ps
CPU time	1.11 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:56 PM PDT 24
Peak memory	214892 kb
Host	smart-672e88fc-3b13-469d-9e1c-4482486eba24
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144421337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1144421337 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.1654982170
Short name	T167
Test name
Test status
Simulation time	31168711 ps
CPU time	0.77 seconds
Started	Aug 14 05:12:48 PM PDT 24
Finished	Aug 14 05:12:49 PM PDT 24
Peak memory	206492 kb
Host	smart-f344c09f-c30d-4213-a89b-546025b20338
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654982170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1654982170 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2538599537
Short name	T6
Test name
Test status
Simulation time	101899862 ps
CPU time	2.56 seconds
Started	Aug 14 05:12:48 PM PDT 24
Finished	Aug 14 05:12:51 PM PDT 24
Peak memory	215276 kb
Host	smart-e8e4dcd9-0c02-49aa-aa4f-ed4c35ae25e0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538599537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr _outstanding.2538599537 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3158868312
Short name	T31
Test name
Test status
Simulation time	319124823 ps
CPU time	1.07 seconds
Started	Aug 14 05:12:48 PM PDT 24
Finished	Aug 14 05:12:49 PM PDT 24
Peak memory	215428 kb
Host	smart-d9d71fec-f9f3-4d11-91c5-ddeab41dbbcb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158868312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.3158868312 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.3690381062
Short name	T67
Test name
Test status
Simulation time	146221088 ps
CPU time	2.42 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	215040 kb
Host	smart-3ad2d0a1-4f95-48e9-889f-35bf1d62e0e3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690381062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3690381062 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3964823141
Short name	T23
Test name
Test status
Simulation time	306545822 ps
CPU time	4.78 seconds
Started	Aug 14 05:12:48 PM PDT 24
Finished	Aug 14 05:12:53 PM PDT 24
Peak memory	214944 kb
Host	smart-a03631bc-efba-41c0-9af5-417f4f61059b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964823141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.39648 23141 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.124543080
Short name	T20
Test name
Test status
Simulation time	132766270 ps
CPU time	1.59 seconds
Started	Aug 14 05:12:53 PM PDT 24
Finished	Aug 14 05:12:55 PM PDT 24
Peak memory	223140 kb
Host	smart-5402a5c6-173b-47a1-8473-0c20de3f5284
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124543080 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.124543080 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.2772101798
Short name	T118
Test name
Test status
Simulation time	86064099 ps
CPU time	1.03 seconds
Started	Aug 14 05:12:46 PM PDT 24
Finished	Aug 14 05:12:47 PM PDT 24
Peak memory	206680 kb
Host	smart-30d74bae-1cfe-4617-b558-baf03d9b6dcd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772101798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2772101798 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.1652007882
Short name	T190
Test name
Test status
Simulation time	14395139 ps
CPU time	0.77 seconds
Started	Aug 14 05:12:46 PM PDT 24
Finished	Aug 14 05:12:47 PM PDT 24
Peak memory	206476 kb
Host	smart-b075f509-9750-4f31-8863-42118e88cff2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652007882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1652007882 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.129421880
Short name	T112
Test name
Test status
Simulation time	150101820 ps
CPU time	2.15 seconds
Started	Aug 14 05:12:48 PM PDT 24
Finished	Aug 14 05:12:50 PM PDT 24
Peak memory	215168 kb
Host	smart-dd282f21-2f55-4832-8fa8-d1da0b398e8c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129421880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_ outstanding.129421880 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2226611174
Short name	T188
Test name
Test status
Simulation time	75681713 ps
CPU time	1.03 seconds
Started	Aug 14 05:12:48 PM PDT 24
Finished	Aug 14 05:12:50 PM PDT 24
Peak memory	215252 kb
Host	smart-1075bcb6-fa46-4a64-b874-b66be723e72c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226611174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.2226611174 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.4124493660
Short name	T168
Test name
Test status
Simulation time	43107041 ps
CPU time	2.22 seconds
Started	Aug 14 05:12:54 PM PDT 24
Finished	Aug 14 05:12:56 PM PDT 24
Peak memory	215116 kb
Host	smart-9a354373-fcee-4783-b44d-ab715f157d37
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124493660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.4124493660 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.3725266611
Short name	T185
Test name
Test status
Simulation time	101624068 ps
CPU time	2.38 seconds
Started	Aug 14 05:12:50 PM PDT 24
Finished	Aug 14 05:12:53 PM PDT 24
Peak memory	215036 kb
Host	smart-cef5db5e-84a9-4dac-93bf-999fe8aa458e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725266611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3725266611 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2577068171
Short name	T125
Test name
Test status
Simulation time	1389742275 ps
CPU time	3.07 seconds
Started	Aug 14 05:12:54 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	217384 kb
Host	smart-774f5e16-b537-4737-9919-b6bf2ca8d8c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577068171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.25770 68171 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1272363876
Short name	T42
Test name
Test status
Simulation time	204093191 ps
CPU time	1.6 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	221692 kb
Host	smart-d8e57b55-907d-430a-ac26-42e76bf89fbe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272363876 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.1272363876 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.1588080028
Short name	T144
Test name
Test status
Simulation time	49481251 ps
CPU time	1.07 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	214828 kb
Host	smart-7b22e820-f313-44db-93a5-152f89dc46b0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588080028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1588080028 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.2203457013
Short name	T100
Test name
Test status
Simulation time	14443641 ps
CPU time	0.78 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	206532 kb
Host	smart-aa2c1e1a-2aff-443e-a383-1fa6e3c6946e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203457013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2203457013 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2378595092
Short name	T38
Test name
Test status
Simulation time	178030282 ps
CPU time	2.5 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:59 PM PDT 24
Peak memory	215412 kb
Host	smart-c5e19828-af73-4789-8d20-985eb3f81202
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378595092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr _outstanding.2378595092 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2555492533
Short name	T135
Test name
Test status
Simulation time	71626458 ps
CPU time	1.12 seconds
Started	Aug 14 05:12:54 PM PDT 24
Finished	Aug 14 05:12:55 PM PDT 24
Peak memory	215492 kb
Host	smart-add5790c-45ba-4313-bc4f-efb1ac187037
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555492533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_ errors.2555492533 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2287234860
Short name	T179
Test name
Test status
Simulation time	48870920 ps
CPU time	2.36 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	215492 kb
Host	smart-fda95ffc-1626-405f-a18f-3cfcf1484a3c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287234860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.2287234860 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.696787930
Short name	T19
Test name
Test status
Simulation time	261327766 ps
CPU time	1.59 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:58 PM PDT 24
Peak memory	215084 kb
Host	smart-303b4418-d83b-4598-be2a-4601d3b4c5e3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696787930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.696787930 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1378104175
Short name	T87
Test name
Test status
Simulation time	368112435 ps
CPU time	4.12 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:13:00 PM PDT 24
Peak memory	206828 kb
Host	smart-03886464-799f-4d32-b9db-3e66c96b69e8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378104175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.13781 04175 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2780125605
Short name	T139
Test name
Test status
Simulation time	126444956 ps
CPU time	2.27 seconds
Started	Aug 14 05:12:57 PM PDT 24
Finished	Aug 14 05:12:59 PM PDT 24
Peak memory	217108 kb
Host	smart-d4e29071-dcfa-44ce-a08a-2c0877ff1861
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780125605 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2780125605 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.2877255378
Short name	T54
Test name
Test status
Simulation time	27147065 ps
CPU time	1.16 seconds
Started	Aug 14 05:12:58 PM PDT 24
Finished	Aug 14 05:13:00 PM PDT 24
Peak memory	206560 kb
Host	smart-ff9e84a1-694f-40ee-b510-3385df74b867
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877255378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2877255378 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.3119974813
Short name	T147
Test name
Test status
Simulation time	13234086 ps
CPU time	0.77 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	206492 kb
Host	smart-d64a3068-bae1-4d4b-bb6d-8f7eadbac78d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119974813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3119974813 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.237597331
Short name	T196
Test name
Test status
Simulation time	124772670 ps
CPU time	2.34 seconds
Started	Aug 14 05:12:57 PM PDT 24
Finished	Aug 14 05:13:00 PM PDT 24
Peak memory	214936 kb
Host	smart-1426d073-cbc4-45bf-87d2-f0ee21c9d695
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237597331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_ outstanding.237597331 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1622037454
Short name	T80
Test name
Test status
Simulation time	41891008 ps
CPU time	0.95 seconds
Started	Aug 14 05:12:56 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	206624 kb
Host	smart-7aab80f4-4991-4e25-ada6-d4bafde0dcab
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622037454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.1622037454 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1850226092
Short name	T52
Test name
Test status
Simulation time	121589070 ps
CPU time	2.83 seconds
Started	Aug 14 05:12:55 PM PDT 24
Finished	Aug 14 05:12:58 PM PDT 24
Peak memory	215472 kb
Host	smart-fef7ef28-d6a7-44a6-979f-08ddb67a5e93
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850226092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.1850226092 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.959070291
Short name	T25
Test name
Test status
Simulation time	410124606 ps
CPU time	2.81 seconds
Started	Aug 14 05:12:54 PM PDT 24
Finished	Aug 14 05:12:57 PM PDT 24
Peak memory	217640 kb
Host	smart-fe56e537-2c1b-4b55-b17d-09fbcf613e08
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959070291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.959070 291 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest