Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 266 1 T2 7 T10 4 T11 4
all_values[1] 266 1 T2 7 T10 4 T11 4
all_values[2] 266 1 T2 7 T10 4 T11 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 456 1 T2 9 T10 5 T11 6
auto[1] 342 1 T2 12 T10 7 T11 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 384 1 T2 11 T10 3 T11 8
auto[1] 414 1 T2 10 T10 9 T11 4


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 478 1 T2 12 T10 6 T11 9
auto[1] 320 1 T2 9 T10 6 T11 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 55 1 T10 1 T81 2 T78 1
all_values[0] auto[0] auto[0] auto[1] 27 1 T78 2 T82 1 T83 1
all_values[0] auto[0] auto[1] auto[0] 48 1 T2 3 T10 1 T11 4
all_values[0] auto[0] auto[1] auto[1] 23 1 T10 1 T21 1 T84 5
all_values[0] auto[1] auto[0] auto[1] 74 1 T2 2 T10 1 T21 2
all_values[0] auto[1] auto[1] auto[1] 39 1 T2 2 T81 1 T85 1
all_values[1] auto[0] auto[0] auto[0] 87 1 T2 2 T11 1 T21 3
all_values[1] auto[0] auto[1] auto[0] 83 1 T2 2 T10 1 T11 1
all_values[1] auto[1] auto[0] auto[1] 57 1 T2 2 T10 2 T11 1
all_values[1] auto[1] auto[1] auto[1] 39 1 T2 1 T10 1 T11 1
all_values[2] auto[0] auto[0] auto[0] 64 1 T2 2 T11 2 T21 1
all_values[2] auto[0] auto[0] auto[1] 23 1 T11 1 T21 1 T78 1
all_values[2] auto[0] auto[1] auto[0] 47 1 T2 2 T81 2 T85 1
all_values[2] auto[0] auto[1] auto[1] 21 1 T2 1 T10 2 T81 1
all_values[2] auto[1] auto[0] auto[1] 69 1 T2 1 T10 1 T11 1
all_values[2] auto[1] auto[1] auto[1] 42 1 T2 1 T10 1 T21 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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