Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	579142877	56125	0	0
RunThenComplete_M	579142877	738677	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	56125	0	0
T1	476532	63	0	0
T2	2586	3	0	0
T3	5314	3	0	0
T4	2529	0	0	0
T11	49807	8	0	0
T12	2377	3	0	0
T13	86036	21	0	0
T14	30058	2	0	0
T15	6021	3	0	0
T16	0	2	0	0
T17	0	105	0	0
T18	1756	0	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	738677	0	0
T1	476532	348	0	0
T2	2586	10	0	0
T3	5314	10	0	0
T4	2529	2	0	0
T11	49807	24	0	0
T12	2377	10	0	0
T13	86036	119	0	0
T14	30058	11	0	0
T15	6021	10	0	0
T16	0	11	0	0
T18	1756	0	0	0