Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.19	96.27	93.33	63.67	100.00	93.85	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	97.24	96.27	93.33	100.00	100.00	93.85	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.24	96.27	93.33	100.00	100.00	93.85	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.34	95.89	92.27	100.00	66.94	94.11	98.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	86.94	90.00	77.78			80.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	81.44	91.14	87.72		40.00	88.35	100.00
u_errchk	91.37	97.22	96.67		66.67	96.30	100.00
u_kmac_core	93.72	98.75	92.86	100.00	87.50	92.31	90.91
u_msgfifo	97.75	100.00	95.00		100.00	93.75	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.98	99.19	96.97	100.00		98.72	100.00
u_sha3	92.16	91.91	88.51	100.00	80.56	92.00	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.88	89.88	81.09			88.54	100.00
u_tlul_adapter_msgfifo	80.11	87.12	74.69			77.38	81.25

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	346	0	0
ALWAYS	346	2	2	100.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
ALWAYS	429	9	9	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
ALWAYS	488	6	6	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	537	0	0
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
ALWAYS	561	5	5	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
ALWAYS	651	5	5	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	687	7	5	71.43
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	728	1	0	0.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
ALWAYS	765	3	3	100.00
ALWAYS	769	28	28	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	923	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1034	1	1	100.00
CONT_ASSIGN	1035	1	1	100.00
CONT_ASSIGN	1037	1	1	100.00
CONT_ASSIGN	1040	0	0
ALWAYS	1161	0	0
ALWAYS	1161	2	2	100.00
CONT_ASSIGN	1315	1	0	0.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1405	1	1	100.00
CONT_ASSIGN	1412	1	1	100.00
CONT_ASSIGN	1417	1	1	100.00
ALWAYS	1423	6	5	83.33
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
ALWAYS	1446	4	4	100.00
CONT_ASSIGN	1452	1	1	100.00
ALWAYS	1475	4	4	100.00
ALWAYS	1485	3	3	100.00
CONT_ASSIGN	1496	1	1	100.00
CONT_ASSIGN	1500	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T6,T9

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T9,T10

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T46,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T11
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T19,T20

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T24,T48

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T4,T13

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T48,T49,T50
1	Covered	T1,T2,T3

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T51,T31,T25
0	0	1	0	Not Covered
0	1	0	0	Covered	T11,T4,T5
1	0	0	0	Covered	T16,T36,T37

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T6,T9,T10
0	1	0	0	Unreachable
1	0	0	0	Covered	T6,T9,T10

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T6,T9,T10
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T6,T9,T10
0	0	1	0	0	0	Covered	T6,T9,T10
0	1	0	0	0	0	Covered	T6,T9,T10
1	0	0	0	0	0	Covered	T6,T9,T10

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T14,T16
1	Covered	T1,T2,T3

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T13,T21,T22
1	Covered	T1,T2,T3

 LINE       1029
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1162
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T53,T54
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T53,T54

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T53,T54
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T53,T54

 LINE       1434
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T6,T9,T10
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T6,T9,T10
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	64	90.14
Total Bits	6534	4160	63.67
Total Bits 0->1	3267	2080	63.67
Total Bits 1->0	3267	2080	63.67

Ports	71	64	90.14
Port Bits	6534	4160	63.67
Port Bits 0->1	3267	2080	63.67
Port Bits 1->0	3267	2080	63.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T18	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T11,T4	Yes	T1,T11,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T55,T39,T56	Yes	T55,T39,T56	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T18,T4,T5	Yes	T18,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T18,T4,T5	Yes	T18,T4,T5	OUTPUT
keymgr_key_i.key[0][3:0]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][6:4]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][7]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][8]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][10:9]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][11]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][12]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][14:13]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][19:15]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][20]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][21]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][23:22]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][24]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][29:25]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][30]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][32:31]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][33]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][37:34]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][38]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][40:39]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][41]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][42]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][44:43]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][45]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][50:46]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][51]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][52]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][54:53]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][58:55]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][59]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][63:60]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][65:64]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][66]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][67]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][71:68]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][72]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][73]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][76:74]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][77]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][82:78]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][84:83]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][85]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][86]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][92:87]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][93]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][97:94]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][98]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][103:99]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][104]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][109:105]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][110]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][112:111]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][113]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][114]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][115]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][116]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][119:117]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][120]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][121]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][122]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][126:123]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][127]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][128]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][129]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][136:130]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][137]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][138]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][139]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][146:140]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][147]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][150:148]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][151]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][154:152]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][155]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][164:156]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][165]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][172:166]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][174:173]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][180:175]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][182:181]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][184:183]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][185]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][195:186]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][196]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][200:197]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][201]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][205:202]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][206]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][209:207]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][210]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][211]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][212]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][213]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][215:214]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][220:216]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][221]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][226:222]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][227]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][230:228]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][232:231]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][233]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][234]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][236:235]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][238:237]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][240:239]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][241]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][242]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][243]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][246:244]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][247]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][249:248]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][250]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][252:251]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][253]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][255:254]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][0]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][3:1]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][4]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][6:5]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][7]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][8]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][9]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][10]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][11]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][12]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][13]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][19:14]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][20]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][24:21]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][25]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][35:26]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][36]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][40:37]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][42:41]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][43]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][44]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][49:45]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][50]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][53:51]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][54]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][55]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][56]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][61:57]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][62]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][64:63]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][65]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][66]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][67]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][72:68]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][73]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][80:74]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][81]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][84:82]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][85]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][86]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][87]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][92:88]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][93]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][94]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][95]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][97:96]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][98]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][99]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][101:100]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][102]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][111:103]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][112]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][114:113]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][115]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][122:116]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][123]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][125:124]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][126]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][127]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][128]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][129]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][130]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][131]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][132]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][133]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][134]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][135]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][138:136]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][139]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][140]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][141]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][148:142]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][149]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][150]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][151]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][152]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][153]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][154]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][156:155]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][157]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][159:158]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][160]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][161]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][162]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][163]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][164]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][166:165]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][167]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][170:168]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][171]	Yes	Yes	T1,T13,T57	Yes	T1,T13,T57	INPUT
keymgr_key_i.key[1][172]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][173]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][174]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][175]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][177:176]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][178]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][180:179]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][181]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][182]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][184:183]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][188:185]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][189]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][190]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][191]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][192]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][193]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][195:194]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][196]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][198:197]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][199]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][200]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][201]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][202]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][203]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][204]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][205]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][206]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][207]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][210:208]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][211]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][212]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][213]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][214]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][215]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][216]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][217]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][218]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][219]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][220]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][221]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][222]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][223]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][224]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][225]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][226]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][228:227]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][229]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][230]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][231]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][232]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][233]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][234]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][235]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][238:236]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][239]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][240]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][241]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][242]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][243]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][251:244]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][252]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][253]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][254]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][255]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.valid	Yes	Yes	T1,T13,T16	Yes	T1,T4,T13	INPUT
app_i[0].last	Yes	Yes	T11,T4,T13	Yes	T11,T4,T13	INPUT
app_i[0].strb[7:0]	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	INPUT
app_i[0].data[63:0]	Yes	Yes	T11,T4,T13	Yes	T11,T4,T13	INPUT
app_i[0].valid	Yes	Yes	T11,T4,T13	Yes	T11,T4,T13	INPUT
app_i[1].last	Yes	Yes	T13,T6,T9	Yes	T13,T21,T6	INPUT
app_i[1].strb[7:0]	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	INPUT
app_i[1].data[63:0]	Yes	Yes	T13,T6,T22	Yes	T13,T21,T6	INPUT
app_i[1].valid	Yes	Yes	T4,T13,T5	Yes	T4,T13,T5	INPUT
app_i[2].last	Yes	Yes	T13,T21,T6	Yes	T13,T21,T6	INPUT
app_i[2].strb[7:0]	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	INPUT
app_i[2].data[63:0]	Yes	Yes	T13,T21,T6	Yes	T13,T21,T6	INPUT
app_i[2].valid	Yes	Yes	T4,T13,T5	Yes	T4,T13,T5	INPUT
app_o[0].error	Yes	Yes	T11,T4,T16	Yes	T11,T4,T16	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T13,T22,T36	Yes	T13,T22,T36	OUTPUT
app_o[0].done	Yes	Yes	T11,T13,T19	Yes	T11,T13,T19	OUTPUT
app_o[0].ready	Yes	Yes	T11,T4,T13	Yes	T11,T4,T13	OUTPUT
app_o[1].error	Yes	Yes	T37,T41,T33	Yes	T37,T41,T33	OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T13,T46,T52	Yes	T13,T46,T52	OUTPUT
app_o[1].done	Yes	Yes	T13,T21,T22	Yes	T13,T21,T22	OUTPUT
app_o[1].ready	Yes	Yes	T13,T21,T22	Yes	T13,T21,T22	OUTPUT
app_o[2].error	Yes	Yes	T36,T37,T33	Yes	T36,T37,T33	OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T13,T21,T46	Yes	T13,T21,T46	OUTPUT
app_o[2].done	Yes	Yes	T13,T21,T22	Yes	T13,T21,T22	OUTPUT
app_o[2].ready	Yes	Yes	T13,T21,T22	Yes	T13,T21,T22	OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	INPUT
intr_kmac_done_o	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	OUTPUT
intr_fifo_empty_o	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
intr_kmac_err_o	Yes	Yes	T11,T5,T19	Yes	T11,T5,T19	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	817	Covered	T1,T2,T3
KmacIdle	785	Covered	T1,T2,T3
KmacKeyBlock	792	Covered	T1,T2,T3
KmacMsgFeed	782	Covered	T1,T2,T3
KmacPrefix	779	Covered	T1,T2,T3
KmacTerminalError	834	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	826	Covered	T1,T2,T3
KmacDigest->KmacTerminalError	848	Covered	T58
KmacIdle->KmacMsgFeed	782	Covered	T1,T14,T16
KmacIdle->KmacPrefix	779	Covered	T1,T2,T3
KmacIdle->KmacTerminalError	848	Covered	T6,T9,T10
KmacKeyBlock->KmacMsgFeed	801	Covered	T1,T2,T3
KmacKeyBlock->KmacTerminalError	848	Covered	T7,T59,T43
KmacMsgFeed->KmacDigest	817	Covered	T1,T2,T3
KmacMsgFeed->KmacIdle	814	Covered	T11,T13,T19
KmacMsgFeed->KmacTerminalError	848	Covered	T4,T5,T44
KmacPrefix->KmacKeyBlock	792	Covered	T1,T2,T3
KmacPrefix->KmacMsgFeed	792	Covered	T13,T21,T22
KmacPrefix->KmacTerminalError	848	Covered	T41,T60,T61

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	426	2	2	100.00
TERNARY	635	4	4	100.00
TERNARY	643	4	4	100.00
TERNARY	648	2	2	100.00
CASE	434	6	5	83.33
IF	488	3	3	100.00
IF	561	3	3	100.00
IF	651	2	2	100.00
CASE	689	6	4	66.67
IF	765	2	2	100.00
CASE	774	15	15	100.00
IF	847	2	2	100.00
TERNARY	1162	2	2	100.00
IF	1423	4	3	75.00
IF	1446	3	3	100.00
IF	1475	3	3	100.00
IF	1485	2	2	100.00

426          assign sw_cmd = (cmd_update) ? cmd_q : CmdNone;
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

635          assign msgfifo_full_seen_d =
                                         
636              msgfifo_full          ? 1'b 1 :
                                       -1-  
                                       ==>  
637              msgfifo_empty_negedge ? 1'b 0 :
                                       -2-  
                                       ==>  
638              msgfifo2kmac_process  ? 1'b 0 : msgfifo_full_seen_q;
                                       -3-  
                                       ==>  
                                       ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T24,T48
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

643          assign msgfifo_empty_gate =
                                        
644              app_active                     ? 1'b 1 :
                                                -1-  
                                                ==>  
645              sha3_fsm != sha3_pkg::StAbsorb ? 1'b 1 :
                                                -2-  
                                                ==>  
646              msgfifo2kmac_process           ? 1'b 1 : ~msgfifo_full_seen_q;
                                                -3-  
                                                ==>  
                                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T4,T13
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

648          assign status_msgfifo_empty = msgfifo_empty_gate ? 1'b 0 : msgfifo_empty;
                                                              -1-  
                                                              ==>  
                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T48,T49,T50

434            unique case (kmac_cmd)
                      -1-  
435              CmdStart: begin
436                sha3_start = 1'b 1;
                   ==>
437              end
438        
439              CmdProcess: begin
440                reg2msgfifo_process = 1'b 1;
                   ==>
441              end
442        
443              CmdManualRun: begin
444                sha3_run = 1'b 1;
                   ==>
445              end
446        
447              CmdDone: begin
448                sha3_done_d = prim_mubi_pkg::MuBi4True;
                   ==>
449              end
450        
451              CmdNone: begin
                 ==>
452                // inactive state
453              end
454        
455              default: begin
                 ==>

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T1,T14,T16
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

488            if (!rst_ni) begin
               -1-  
489              sw_key_data_reg[0] <= '0;
                 ==>
490            end else if (engine_stable) begin
                        -2-  
491              for (int j = 0 ; j < MaxKeyLen/32 ; j++) begin
                 ==>
492                if (reg2hw.key_share0[j].qe) begin
493                  sw_key_data_reg[0][32*j+:32] <= reg2hw.key_share0[j].q;
494                end
495              end // for j
496            end // else if engine_stable
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

561            if (!rst_ni) begin
               -1-  
562              idle_o <= prim_mubi_pkg::MuBi4True;
                 ==>
563            end else if ((sha3_fsm == sha3_pkg::StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)) begin
                        -2-                                           
564              idle_o <= prim_mubi_pkg::MuBi4True;
                 ==>
565            end else begin
566              idle_o <= prim_mubi_pkg::MuBi4False;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

651            if (!rst_ni) begin
               -1-  
652              msgfifo_empty_q     <= 1'b 0;
                 ==>
653              msgfifo_full_seen_q <= 1'b 0;
654            end else begin
655              msgfifo_empty_q     <= msgfifo_empty;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

689            priority case (1'b 1)
                        -1-  
690              // app_err has the highest priority. If SW issues an incorrect command
691              // while app is in active state, the error from AppIntf is passed
692              // through.
693              app_err.valid: begin
694                hw2reg.err_code.d = {app_err.code, app_err.info};
                   ==>
695              end
696        
697              errchecker_err.valid: begin
698                hw2reg.err_code.d = {errchecker_err.code , errchecker_err.info};
                   ==>
699              end
700        
701              sha3_err.valid: begin
702                hw2reg.err_code.d = {sha3_err.code , sha3_err.info};
                   ==>
703              end
704        
705              entropy_err.valid: begin
706                hw2reg.err_code.d = {entropy_err.code, entropy_err.info};
                   ==>
707              end
708        
709              msgfifo_err.valid: begin
710                hw2reg.err_code.d = {msgfifo_err.code, msgfifo_err.info};
                   ==>
711              end
712        
713              default: begin
714                hw2reg.err_code.d = '0;
                   ==>

Branches:

-1-	Status	Tests
app_err.valid	Covered	T11,T4,T5
errchecker_err.valid	Covered	T51,T31,T25
sha3_err.valid	Covered	T16,T36,T37
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

765          `PRIM_FLOP_SPARSE_FSM(u_state_regs, kmac_st_d, kmac_st, kmac_st_e, KmacIdle)
             -1-                                                                            
             ==>                                                                            
             ==>                                                                            

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

774            unique case (kmac_st)
                      -1-  
775              KmacIdle: begin
776                if (kmac_cmd == CmdStart) begin
                   -2-  
777                  // If cSHAKE turned on
778                  if (sha3_pkg::CShake == app_sha3_mode) begin
                     -3-  
779                    kmac_st_d = KmacPrefix;
                       ==>
780                  end else begin
781                    // Jump to Msg feed directly
782                    kmac_st_d = KmacMsgFeed;
                       ==>
783                  end
784                end else begin
785                  kmac_st_d = KmacIdle;
                     ==>
786                end
787              end
788        
789              KmacPrefix: begin
790                // Wait until SHA3 processes one block
791                if (sha3_block_processed) begin
                   -4-  
792                  kmac_st_d = (app_kmac_en) ? KmacKeyBlock : KmacMsgFeed ;
                                               -5-  
                                               ==>  
                                               ==>  
793                end else begin
794                  kmac_st_d = KmacPrefix;
                     ==>
795                end
796              end
797        
798              KmacKeyBlock: begin
799                entropy_in_keyblock = 1'b 1;
800                if (sha3_block_processed) begin
                   -6-  
801                  kmac_st_d = KmacMsgFeed;
                     ==>
802                end else begin
803                  kmac_st_d = KmacKeyBlock;
                     ==>
804                end
805              end
806        
807              KmacMsgFeed: begin
808                // If absorbed, move to Digest
809                if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) &&
                   -7-  
810                  prim_mubi_pkg::mubi4_test_true_strict(sha3_done)) begin
811                  // absorbed and done can be asserted at a cycle if Applications have
812                  // requested the hash operation. kmac_app FSM issues CmdDone command
813                  // if it receives absorbed signal.
814                  kmac_st_d = KmacIdle;
                     ==>
815                end else if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) &&
                            -8-  
816                  prim_mubi_pkg::mubi4_test_false_loose(sha3_done)) begin
817                  kmac_st_d = KmacDigest;
                     ==>
818                end else begin
819                  kmac_st_d = KmacMsgFeed;
                     ==>
820                end
821              end
822        
823              KmacDigest: begin
824                // SW can manually run it, wait till done
825                if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done)) begin
                   -9-  
826                  kmac_st_d = KmacIdle;
                     ==>
827                end else begin
828                  kmac_st_d = KmacDigest;
                     ==>
829                end
830              end
831        
832              KmacTerminalError: begin
833                //this state is terminal
834                kmac_st_d = KmacTerminalError;
                   ==>
835                kmac_state_error = 1'b 1;
836              end
837        
838              default: begin
839                kmac_st_d = KmacTerminalError;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T14,T16
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T13,T21,T22
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T11,T13,T19
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T6,T9,T10

847            if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0])) begin
               -1-  
848              kmac_st_d = KmacTerminalError;
                 ==>
849            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

1162             reg_state_tl[i] = reg_state_valid ? reg_state[i] : 'b0;
                                                   -1-  
                                                   ==>  
                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

1423           if (!rst_ni) begin
               -1-  
1424             status_alert_recov_ctrl_update_err <= 1'b 0;
                 ==>
1425           end else if (alert_recov_operation) begin
                        -2-  
1426             status_alert_recov_ctrl_update_err <= 1'b 1;
                 ==>
1427           end else if (err_processed) begin
                        -3-  
1428             status_alert_recov_ctrl_update_err <= 1'b 0;
                 ==>
1429           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T11,T19,T20
0	0	0	Covered	T1,T2,T3

1446           if (!rst_ni) begin
               -1-  
1447             status_alert_fatal_fault <= 1'b 0;
                 ==>
1448           end else if (alert_fatal) begin
                        -2-  
1449             status_alert_fatal_fault <= 1'b 1;
                 ==>
1450           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

1475           if (!rst_ni) begin
               -1-  
1476             alerts_q[1] <= 1'b0;
                 ==>
1477           end else if (alerts[1]) begin
                        -2-  
1478             // fatal alerts cannot be cleared
1479             alerts_q[1] <= 1'b1;
                 ==>
1480           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

1485           if (!rst_ni) begin
               -1-  
1486             alerts_q[0] <= 1'b0;
                 ==>
1487           end else begin
1488             // recoverable alerts can be cleared so just latch the value
1489             alerts_q[0] <= alerts[0];
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	579142877	579015708	0	0
CmdSparse_M	579142877	314323	0	0
EnMaskingKnown_A	579142877	579015708	0	0
EntropyReadyLatched_A	579142877	55008	0	0
EntrySizeRegSameToEntrySizePkg_A	663	663	0	0
ErrProcessedLatched_A	579142877	458	0	0
FifoEmpty_A	579142877	579015708	0	0
FpvSecCmErrorCheckFsmCheck_A	579142877	70	0	0
FpvSecCmKeccackFsmCheck_A	579142877	70	0	0
FpvSecCmKeyIndexCountCheck_A	579142877	70	0	0
FpvSecCmKmacAppFsmCheck_A	579142877	70	0	0
FpvSecCmKmacCoreFsmCheck_A	579142877	70	0	0
FpvSecCmKmacFsmCheck_A	579142877	70	0	0
FpvSecCmRegWeOnehotCheck_A	579142877	70	0	0
FpvSecCmRoundCountCheck_A	579142877	70	0	0
FpvSecCmSHA3FsmCheck_A	579142877	70	0	0
FpvSecCmSHA3padFsmCheck_A	579142877	70	0	0
FpvSecCmSentMsgCountCheck_A	579142877	70	0	0
KmacCmd_A	579142877	579015708	0	0
KmacDone_A	579142877	579015708	0	0
KmacErr_A	579142877	579015708	0	0
KmacStKnown_A	579142877	579015708	0	0
NumAlerts2_A	663	663	0	0
NumEntriesRegSameToNumEntriesPkg_A	663	663	0	0
PrefixRegSameToPrefixPkg_A	663	663	0	0
SecretKeyDivideBy32_A	663	663	0	0
Sha3AbsorbedPulse_A	579142877	56125	0	0
TlOAReadyKnown_A	579142877	579015708	0	0
TlODValidKnown_A	579142877	579015708	0	0
u_state_regs_A	579142877	579015708	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	314323	0	0
T1	476532	452	0	0
T2	2586	10	0	0
T3	5314	10	0	0
T4	2529	1	0	0
T11	49807	8	0	0
T12	2377	9	0	0
T13	86036	5	0	0
T14	30058	14	0	0
T15	6021	9	0	0
T16	0	15	0	0
T18	1756	0	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	55008	0	0
T1	476532	63	0	0
T2	2586	3	0	0
T3	5314	3	0	0
T4	2529	1	0	0
T11	49807	8	0	0
T12	2377	3	0	0
T13	86036	0	0	0
T14	30058	2	0	0
T15	6021	3	0	0
T16	0	2	0	0
T17	0	101	0	0
T18	1756	0	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	458	0	0
T4	2529	0	0	0
T5	4044	0	0	0
T11	49807	8	0	0
T12	2377	0	0	0
T13	86036	0	0	0
T14	30058	0	0	0
T15	6021	0	0	0
T16	6507	0	0	0
T17	145290	0	0	0
T18	1756	0	0	0
T19	0	18	0	0
T20	0	17	0	0
T62	0	13	0	0
T63	0	13	0	0
T64	0	9	0	0
T65	0	8	0	0
T66	0	4	0	0
T67	0	5	0	0
T68	0	14	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	56125	0	0
T1	476532	63	0	0
T2	2586	3	0	0
T3	5314	3	0	0
T4	2529	0	0	0
T11	49807	8	0	0
T12	2377	3	0	0
T13	86036	21	0	0
T14	30058	2	0	0
T15	6021	3	0	0
T16	0	2	0	0
T17	0	105	0	0
T18	1756	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	346	0	0
ALWAYS	346	2	2	100.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
ALWAYS	429	9	9	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
ALWAYS	488	6	6	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	537	0	0
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
ALWAYS	561	5	5	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
ALWAYS	651	5	5	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	687	7	5	71.43
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	728	1	0	0.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
ALWAYS	765	3	3	100.00
ALWAYS	769	28	28	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	923	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1034	1	1	100.00
CONT_ASSIGN	1035	1	1	100.00
CONT_ASSIGN	1037	1	1	100.00
CONT_ASSIGN	1040	0	0
ALWAYS	1161	0	0
ALWAYS	1161	2	2	100.00
CONT_ASSIGN	1315	1	0	0.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1405	1	1	100.00
CONT_ASSIGN	1412	1	1	100.00
CONT_ASSIGN	1417	1	1	100.00
ALWAYS	1423	6	5	83.33
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
ALWAYS	1446	4	4	100.00
CONT_ASSIGN	1452	1	1	100.00
ALWAYS	1475	4	4	100.00
ALWAYS	1485	3	3	100.00
CONT_ASSIGN	1496	1	1	100.00
CONT_ASSIGN	1500	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T6,T9

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T9,T10

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T46,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T11
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T19,T20

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T24,T48

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T4,T13

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T48,T49,T50
1	Covered	T1,T2,T3

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T51,T31,T25
0	0	1	0	Not Covered
0	1	0	0	Covered	T11,T4,T5
1	0	0	0	Covered	T16,T36,T37

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T6,T9,T10
0	1	0	0	Unreachable
1	0	0	0	Covered	T6,T9,T10

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T6,T9,T10
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T6,T9,T10
0	0	1	0	0	0	Covered	T6,T9,T10
0	1	0	0	0	0	Covered	T6,T9,T10
1	0	0	0	0	0	Covered	T6,T9,T10

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T14,T16
1	Covered	T1,T2,T3

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T13,T21,T22
1	Covered	T1,T2,T3

 LINE       1029
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1162
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T53,T54
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T53,T54

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T53,T54
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T53,T54

 LINE       1434
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T6,T9,T10
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T6,T9,T10
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	64	100.00
Total Bits	4160	4160	100.00
Total Bits 0->1	2080	2080	100.00
Total Bits 1->0	2080	2080	100.00

Ports	64	64	100.00
Port Bits	4160	4160	100.00
Port Bits 0->1	2080	2080	100.00
Port Bits 1->0	2080	2080	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T18	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T11,T4	Yes	T1,T11,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T55,T39,T56	Yes	T55,T39,T56	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T18,T4,T5	Yes	T18,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T18,T4,T5	Yes	T18,T4,T5	OUTPUT
keymgr_key_i.key[0][3:0]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][6:4]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][7]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][8]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][10:9]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][11]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][12]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][14:13]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][19:15]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][20]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][21]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][23:22]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][24]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][29:25]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][30]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][32:31]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][33]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][37:34]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][38]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][40:39]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][41]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][42]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][44:43]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][45]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][50:46]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][51]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][52]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][54:53]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][58:55]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][59]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][63:60]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][65:64]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][66]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][67]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][71:68]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][72]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][73]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][76:74]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][77]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][82:78]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][84:83]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][85]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][86]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][92:87]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][93]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][97:94]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][98]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][103:99]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][104]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][109:105]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][110]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][112:111]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][113]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][114]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][115]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][116]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][119:117]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][120]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][121]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][122]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][126:123]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][127]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][128]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][129]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][136:130]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][137]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][138]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][139]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][146:140]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][147]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][150:148]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][151]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][154:152]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][155]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][164:156]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][165]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][172:166]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][174:173]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][180:175]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][182:181]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][184:183]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][185]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[0][195:186]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][196]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][200:197]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][201]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][205:202]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][206]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][209:207]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][210]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][211]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][212]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][213]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][215:214]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][220:216]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][221]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][226:222]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][227]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][230:228]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][232:231]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][233]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][234]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][236:235]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][238:237]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][240:239]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][241]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][242]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][243]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][246:244]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][247]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][249:248]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][250]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][252:251]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][253]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[0][255:254]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][0]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][3:1]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][4]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][6:5]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][7]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][8]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][9]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][10]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][11]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][12]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][13]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][19:14]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][20]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][24:21]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][25]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][35:26]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][36]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][40:37]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][42:41]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][43]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][44]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][49:45]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][50]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][53:51]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][54]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][55]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][56]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][61:57]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][62]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][64:63]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][65]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][66]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][67]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][72:68]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][73]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][80:74]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][81]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][84:82]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][85]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][86]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][87]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][92:88]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][93]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][94]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][95]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][97:96]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][98]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][99]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][101:100]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][102]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][111:103]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][112]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][114:113]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][115]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][122:116]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][123]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][125:124]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][126]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][127]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][128]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][129]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][130]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][131]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][132]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][133]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][134]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][135]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][138:136]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][139]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][140]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][141]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][148:142]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][149]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][150]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][151]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][152]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][153]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][154]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][156:155]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][157]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][159:158]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][160]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][161]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][162]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][163]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][164]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][166:165]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][167]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][170:168]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][171]	Yes	Yes	T1,T13,T57	Yes	T1,T13,T57	INPUT
keymgr_key_i.key[1][172]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][173]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][174]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][175]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][177:176]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][178]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][180:179]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][181]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][182]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][184:183]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][188:185]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][189]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][190]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][191]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][192]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][193]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][195:194]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][196]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][198:197]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][199]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][200]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][201]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][202]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][203]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][204]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][205]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][206]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][207]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][210:208]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][211]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][212]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][213]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][214]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][215]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][216]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][217]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][218]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][219]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][220]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][221]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][222]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][223]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][224]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][225]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][226]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][228:227]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][229]	Yes	Yes	T1,T13,T21	Yes	T1,T13,T21	INPUT
keymgr_key_i.key[1][230]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][231]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][232]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][233]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][234]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][235]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][238:236]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][239]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][240]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][241]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][242]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][243]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][251:244]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][252]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][253]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][254]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.key[1][255]	Yes	Yes	T1,T13,T28	Yes	T1,T13,T28	INPUT
keymgr_key_i.valid	Yes	Yes	T1,T13,T16	Yes	T1,T4,T13	INPUT
app_i[0].last	Yes	Yes	T11,T4,T13	Yes	T11,T4,T13	INPUT
app_i[0].strb[7:0]	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	INPUT
app_i[0].data[63:0]	Yes	Yes	T11,T4,T13	Yes	T11,T4,T13	INPUT
app_i[0].valid	Yes	Yes	T11,T4,T13	Yes	T11,T4,T13	INPUT
app_i[1].last	Yes	Yes	T13,T6,T9	Yes	T13,T21,T6	INPUT
app_i[1].strb[7:0]	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	INPUT
app_i[1].data[63:0]	Yes	Yes	T13,T6,T22	Yes	T13,T21,T6	INPUT
app_i[1].valid	Yes	Yes	T4,T13,T5	Yes	T4,T13,T5	INPUT
app_i[2].last	Yes	Yes	T13,T21,T6	Yes	T13,T21,T6	INPUT
app_i[2].strb[7:0]	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	INPUT
app_i[2].data[63:0]	Yes	Yes	T13,T21,T6	Yes	T13,T21,T6	INPUT
app_i[2].valid	Yes	Yes	T4,T13,T5	Yes	T4,T13,T5	INPUT
app_o[0].error	Yes	Yes	T11,T4,T16	Yes	T11,T4,T16	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	Yes	Yes	T13,T22,T36	Yes	T13,T22,T36	OUTPUT
app_o[0].done	Yes	Yes	T11,T13,T19	Yes	T11,T13,T19	OUTPUT
app_o[0].ready	Yes	Yes	T11,T4,T13	Yes	T11,T4,T13	OUTPUT
app_o[1].error	Yes	Yes	T37,T41,T33	Yes	T37,T41,T33	OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	Yes	Yes	T13,T46,T52	Yes	T13,T46,T52	OUTPUT
app_o[1].done	Yes	Yes	T13,T21,T22	Yes	T13,T21,T22	OUTPUT
app_o[1].ready	Yes	Yes	T13,T21,T22	Yes	T13,T21,T22	OUTPUT
app_o[2].error	Yes	Yes	T36,T37,T33	Yes	T36,T37,T33	OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	Yes	Yes	T13,T21,T46	Yes	T13,T21,T46	OUTPUT
app_o[2].done	Yes	Yes	T13,T21,T22	Yes	T13,T21,T22	OUTPUT
app_o[2].ready	Yes	Yes	T13,T21,T22	Yes	T13,T21,T22	OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	INPUT
intr_kmac_done_o	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	OUTPUT
intr_fifo_empty_o	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
intr_kmac_err_o	Yes	Yes	T11,T5,T19	Yes	T11,T5,T19	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	817	Covered	T1,T2,T3
KmacIdle	785	Covered	T1,T2,T3
KmacKeyBlock	792	Covered	T1,T2,T3
KmacMsgFeed	782	Covered	T1,T2,T3
KmacPrefix	779	Covered	T1,T2,T3
KmacTerminalError	834	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	826	Covered	T1,T2,T3
KmacDigest->KmacTerminalError	848	Covered	T58
KmacIdle->KmacMsgFeed	782	Covered	T1,T14,T16
KmacIdle->KmacPrefix	779	Covered	T1,T2,T3
KmacIdle->KmacTerminalError	848	Covered	T6,T9,T10
KmacKeyBlock->KmacMsgFeed	801	Covered	T1,T2,T3
KmacKeyBlock->KmacTerminalError	848	Covered	T7,T59,T43
KmacMsgFeed->KmacDigest	817	Covered	T1,T2,T3
KmacMsgFeed->KmacIdle	814	Covered	T11,T13,T19
KmacMsgFeed->KmacTerminalError	848	Covered	T4,T5,T44
KmacPrefix->KmacKeyBlock	792	Covered	T1,T2,T3
KmacPrefix->KmacMsgFeed	792	Covered	T13,T21,T22
KmacPrefix->KmacTerminalError	848	Covered	T41,T60,T61

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	426	2	2	100.00
TERNARY	635	4	4	100.00
TERNARY	643	4	4	100.00
TERNARY	648	2	2	100.00
CASE	434	6	5	83.33
IF	488	3	3	100.00
IF	561	3	3	100.00
IF	651	2	2	100.00
CASE	689	6	4	66.67
IF	765	2	2	100.00
CASE	774	15	15	100.00
IF	847	2	2	100.00
TERNARY	1162	2	2	100.00
IF	1423	4	3	75.00
IF	1446	3	3	100.00
IF	1475	3	3	100.00
IF	1485	2	2	100.00

426          assign sw_cmd = (cmd_update) ? cmd_q : CmdNone;
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

635          assign msgfifo_full_seen_d =
                                         
636              msgfifo_full          ? 1'b 1 :
                                       -1-  
                                       ==>  
637              msgfifo_empty_negedge ? 1'b 0 :
                                       -2-  
                                       ==>  
638              msgfifo2kmac_process  ? 1'b 0 : msgfifo_full_seen_q;
                                       -3-  
                                       ==>  
                                       ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T24,T48
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

643          assign msgfifo_empty_gate =
                                        
644              app_active                     ? 1'b 1 :
                                                -1-  
                                                ==>  
645              sha3_fsm != sha3_pkg::StAbsorb ? 1'b 1 :
                                                -2-  
                                                ==>  
646              msgfifo2kmac_process           ? 1'b 1 : ~msgfifo_full_seen_q;
                                                -3-  
                                                ==>  
                                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T4,T13
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

648          assign status_msgfifo_empty = msgfifo_empty_gate ? 1'b 0 : msgfifo_empty;
                                                              -1-  
                                                              ==>  
                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T48,T49,T50

434            unique case (kmac_cmd)
                      -1-  
435              CmdStart: begin
436                sha3_start = 1'b 1;
                   ==>
437              end
438        
439              CmdProcess: begin
440                reg2msgfifo_process = 1'b 1;
                   ==>
441              end
442        
443              CmdManualRun: begin
444                sha3_run = 1'b 1;
                   ==>
445              end
446        
447              CmdDone: begin
448                sha3_done_d = prim_mubi_pkg::MuBi4True;
                   ==>
449              end
450        
451              CmdNone: begin
                 ==>
452                // inactive state
453              end
454        
455              default: begin
                 ==>

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T1,T14,T16
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

488            if (!rst_ni) begin
               -1-  
489              sw_key_data_reg[0] <= '0;
                 ==>
490            end else if (engine_stable) begin
                        -2-  
491              for (int j = 0 ; j < MaxKeyLen/32 ; j++) begin
                 ==>
492                if (reg2hw.key_share0[j].qe) begin
493                  sw_key_data_reg[0][32*j+:32] <= reg2hw.key_share0[j].q;
494                end
495              end // for j
496            end // else if engine_stable
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

561            if (!rst_ni) begin
               -1-  
562              idle_o <= prim_mubi_pkg::MuBi4True;
                 ==>
563            end else if ((sha3_fsm == sha3_pkg::StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)) begin
                        -2-                                           
564              idle_o <= prim_mubi_pkg::MuBi4True;
                 ==>
565            end else begin
566              idle_o <= prim_mubi_pkg::MuBi4False;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

651            if (!rst_ni) begin
               -1-  
652              msgfifo_empty_q     <= 1'b 0;
                 ==>
653              msgfifo_full_seen_q <= 1'b 0;
654            end else begin
655              msgfifo_empty_q     <= msgfifo_empty;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

689            priority case (1'b 1)
                        -1-  
690              // app_err has the highest priority. If SW issues an incorrect command
691              // while app is in active state, the error from AppIntf is passed
692              // through.
693              app_err.valid: begin
694                hw2reg.err_code.d = {app_err.code, app_err.info};
                   ==>
695              end
696        
697              errchecker_err.valid: begin
698                hw2reg.err_code.d = {errchecker_err.code , errchecker_err.info};
                   ==>
699              end
700        
701              sha3_err.valid: begin
702                hw2reg.err_code.d = {sha3_err.code , sha3_err.info};
                   ==>
703              end
704        
705              entropy_err.valid: begin
706                hw2reg.err_code.d = {entropy_err.code, entropy_err.info};
                   ==>
707              end
708        
709              msgfifo_err.valid: begin
710                hw2reg.err_code.d = {msgfifo_err.code, msgfifo_err.info};
                   ==>
711              end
712        
713              default: begin
714                hw2reg.err_code.d = '0;
                   ==>

Branches:

-1-	Status	Tests
app_err.valid	Covered	T11,T4,T5
errchecker_err.valid	Covered	T51,T31,T25
sha3_err.valid	Covered	T16,T36,T37
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

765          `PRIM_FLOP_SPARSE_FSM(u_state_regs, kmac_st_d, kmac_st, kmac_st_e, KmacIdle)
             -1-                                                                            
             ==>                                                                            
             ==>                                                                            

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

774            unique case (kmac_st)
                      -1-  
775              KmacIdle: begin
776                if (kmac_cmd == CmdStart) begin
                   -2-  
777                  // If cSHAKE turned on
778                  if (sha3_pkg::CShake == app_sha3_mode) begin
                     -3-  
779                    kmac_st_d = KmacPrefix;
                       ==>
780                  end else begin
781                    // Jump to Msg feed directly
782                    kmac_st_d = KmacMsgFeed;
                       ==>
783                  end
784                end else begin
785                  kmac_st_d = KmacIdle;
                     ==>
786                end
787              end
788        
789              KmacPrefix: begin
790                // Wait until SHA3 processes one block
791                if (sha3_block_processed) begin
                   -4-  
792                  kmac_st_d = (app_kmac_en) ? KmacKeyBlock : KmacMsgFeed ;
                                               -5-  
                                               ==>  
                                               ==>  
793                end else begin
794                  kmac_st_d = KmacPrefix;
                     ==>
795                end
796              end
797        
798              KmacKeyBlock: begin
799                entropy_in_keyblock = 1'b 1;
800                if (sha3_block_processed) begin
                   -6-  
801                  kmac_st_d = KmacMsgFeed;
                     ==>
802                end else begin
803                  kmac_st_d = KmacKeyBlock;
                     ==>
804                end
805              end
806        
807              KmacMsgFeed: begin
808                // If absorbed, move to Digest
809                if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) &&
                   -7-  
810                  prim_mubi_pkg::mubi4_test_true_strict(sha3_done)) begin
811                  // absorbed and done can be asserted at a cycle if Applications have
812                  // requested the hash operation. kmac_app FSM issues CmdDone command
813                  // if it receives absorbed signal.
814                  kmac_st_d = KmacIdle;
                     ==>
815                end else if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) &&
                            -8-  
816                  prim_mubi_pkg::mubi4_test_false_loose(sha3_done)) begin
817                  kmac_st_d = KmacDigest;
                     ==>
818                end else begin
819                  kmac_st_d = KmacMsgFeed;
                     ==>
820                end
821              end
822        
823              KmacDigest: begin
824                // SW can manually run it, wait till done
825                if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done)) begin
                   -9-  
826                  kmac_st_d = KmacIdle;
                     ==>
827                end else begin
828                  kmac_st_d = KmacDigest;
                     ==>
829                end
830              end
831        
832              KmacTerminalError: begin
833                //this state is terminal
834                kmac_st_d = KmacTerminalError;
                   ==>
835                kmac_state_error = 1'b 1;
836              end
837        
838              default: begin
839                kmac_st_d = KmacTerminalError;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T14,T16
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T13,T21,T22
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T11,T13,T19
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T6,T9,T10

847            if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0])) begin
               -1-  
848              kmac_st_d = KmacTerminalError;
                 ==>
849            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

1162             reg_state_tl[i] = reg_state_valid ? reg_state[i] : 'b0;
                                                   -1-  
                                                   ==>  
                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

1423           if (!rst_ni) begin
               -1-  
1424             status_alert_recov_ctrl_update_err <= 1'b 0;
                 ==>
1425           end else if (alert_recov_operation) begin
                        -2-  
1426             status_alert_recov_ctrl_update_err <= 1'b 1;
                 ==>
1427           end else if (err_processed) begin
                        -3-  
1428             status_alert_recov_ctrl_update_err <= 1'b 0;
                 ==>
1429           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T11,T19,T20
0	0	0	Covered	T1,T2,T3

1446           if (!rst_ni) begin
               -1-  
1447             status_alert_fatal_fault <= 1'b 0;
                 ==>
1448           end else if (alert_fatal) begin
                        -2-  
1449             status_alert_fatal_fault <= 1'b 1;
                 ==>
1450           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

1475           if (!rst_ni) begin
               -1-  
1476             alerts_q[1] <= 1'b0;
                 ==>
1477           end else if (alerts[1]) begin
                        -2-  
1478             // fatal alerts cannot be cleared
1479             alerts_q[1] <= 1'b1;
                 ==>
1480           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

1485           if (!rst_ni) begin
               -1-  
1486             alerts_q[0] <= 1'b0;
                 ==>
1487           end else begin
1488             // recoverable alerts can be cleared so just latch the value
1489             alerts_q[0] <= alerts[0];
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	579142877	579015708	0	0
CmdSparse_M	579142877	314323	0	0
EnMaskingKnown_A	579142877	579015708	0	0
EntropyReadyLatched_A	579142877	55008	0	0
EntrySizeRegSameToEntrySizePkg_A	663	663	0	0
ErrProcessedLatched_A	579142877	458	0	0
FifoEmpty_A	579142877	579015708	0	0
FpvSecCmErrorCheckFsmCheck_A	579142877	70	0	0
FpvSecCmKeccackFsmCheck_A	579142877	70	0	0
FpvSecCmKeyIndexCountCheck_A	579142877	70	0	0
FpvSecCmKmacAppFsmCheck_A	579142877	70	0	0
FpvSecCmKmacCoreFsmCheck_A	579142877	70	0	0
FpvSecCmKmacFsmCheck_A	579142877	70	0	0
FpvSecCmRegWeOnehotCheck_A	579142877	70	0	0
FpvSecCmRoundCountCheck_A	579142877	70	0	0
FpvSecCmSHA3FsmCheck_A	579142877	70	0	0
FpvSecCmSHA3padFsmCheck_A	579142877	70	0	0
FpvSecCmSentMsgCountCheck_A	579142877	70	0	0
KmacCmd_A	579142877	579015708	0	0
KmacDone_A	579142877	579015708	0	0
KmacErr_A	579142877	579015708	0	0
KmacStKnown_A	579142877	579015708	0	0
NumAlerts2_A	663	663	0	0
NumEntriesRegSameToNumEntriesPkg_A	663	663	0	0
PrefixRegSameToPrefixPkg_A	663	663	0	0
SecretKeyDivideBy32_A	663	663	0	0
Sha3AbsorbedPulse_A	579142877	56125	0	0
TlOAReadyKnown_A	579142877	579015708	0	0
TlODValidKnown_A	579142877	579015708	0	0
u_state_regs_A	579142877	579015708	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	314323	0	0
T1	476532	452	0	0
T2	2586	10	0	0
T3	5314	10	0	0
T4	2529	1	0	0
T11	49807	8	0	0
T12	2377	9	0	0
T13	86036	5	0	0
T14	30058	14	0	0
T15	6021	9	0	0
T16	0	15	0	0
T18	1756	0	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	55008	0	0
T1	476532	63	0	0
T2	2586	3	0	0
T3	5314	3	0	0
T4	2529	1	0	0
T11	49807	8	0	0
T12	2377	3	0	0
T13	86036	0	0	0
T14	30058	2	0	0
T15	6021	3	0	0
T16	0	2	0	0
T17	0	101	0	0
T18	1756	0	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	458	0	0
T4	2529	0	0	0
T5	4044	0	0	0
T11	49807	8	0	0
T12	2377	0	0	0
T13	86036	0	0	0
T14	30058	0	0	0
T15	6021	0	0	0
T16	6507	0	0	0
T17	145290	0	0	0
T18	1756	0	0	0
T19	0	18	0	0
T20	0	17	0	0
T62	0	13	0	0
T63	0	13	0	0
T64	0	9	0	0
T65	0	8	0	0
T66	0	4	0	0
T67	0	5	0	0
T68	0	14	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	70	0	0
T6	256881	10	0	0
T9	157207	10	0	0
T10	0	10	0	0
T22	226224	0	0	0
T32	163064	0	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	218997	0	0	0
T72	178563	0	0	0
T73	2834	0	0	0
T74	3004	0	0	0
T75	77341	0	0	0
T76	104341	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	56125	0	0
T1	476532	63	0	0
T2	2586	3	0	0
T3	5314	3	0	0
T4	2529	0	0	0
T11	49807	8	0	0
T12	2377	3	0	0
T13	86036	21	0	0
T14	30058	2	0	0
T15	6021	3	0	0
T16	0	2	0	0
T17	0	105	0	0
T18	1756	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579142877	579015708	0	0
T1	476532	476455	0	0
T2	2586	2520	0	0
T3	5314	5222	0	0
T4	2529	2369	0	0
T11	49807	49724	0	0
T12	2377	2312	0	0
T13	86036	85980	0	0
T14	30058	29996	0	0
T15	6021	5961	0	0
T18	1756	1667	0	0