Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	580534699	11005	0	0
entropy_period_rd_A	580534699	1798	0	0
intr_enable_rd_A	580534699	2379	0	0
prefix_0_rd_A	580534699	1506	0	0
prefix_10_rd_A	580534699	1715	0	0
prefix_1_rd_A	580534699	1586	0	0
prefix_2_rd_A	580534699	1529	0	0
prefix_3_rd_A	580534699	1481	0	0
prefix_4_rd_A	580534699	1499	0	0
prefix_5_rd_A	580534699	1584	0	0
prefix_6_rd_A	580534699	1646	0	0
prefix_7_rd_A	580534699	1593	0	0
prefix_8_rd_A	580534699	1574	0	0
prefix_9_rd_A	580534699	1583	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	11005	0	0
T39	0	3987	0	0
T50	160503	0	0	0
T55	281278	3537	0	0
T56	0	105	0	0
T65	83884	0	0	0
T80	129320	0	0	0
T81	555774	0	0	0
T82	105361	0	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T112	0	204	0	0
T117	0	4	0	0
T118	0	3	0	0
T119	0	51	0	0
T122	72167	0	0	0
T123	466908	0	0	0
T124	57825	0	0	0
T125	723933	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1798	0	0
T86	3131	6	0	0
T89	2408	2	0	0
T96	11969	66	0	0
T98	2810	9	0	0
T114	1783	8	0	0
T136	51852	410	0	0
T137	24685	182	0	0
T138	26798	247	0	0
T139	5384	7	0	0
T140	7855	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	2379	0	0
T86	3131	12	0	0
T89	2408	4	0	0
T111	1434	10	0	0
T114	1783	7	0	0
T115	919	7	0	0
T136	51852	455	0	0
T137	24685	251	0	0
T138	26798	199	0	0
T141	1081	8	0	0
T142	1475	7	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1506	0	0
T86	3131	16	0	0
T89	2408	5	0	0
T96	11969	34	0	0
T98	2810	13	0	0
T114	1783	5	0	0
T136	51852	378	0	0
T137	24685	226	0	0
T138	26798	179	0	0
T139	5384	20	0	0
T140	7855	13	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1715	0	0
T86	3131	8	0	0
T89	2408	10	0	0
T96	11969	67	0	0
T98	2810	7	0	0
T114	1783	5	0	0
T136	51852	424	0	0
T137	24685	242	0	0
T138	26798	194	0	0
T139	5384	14	0	0
T140	7855	22	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1586	0	0
T86	3131	4	0	0
T89	2408	5	0	0
T96	11969	30	0	0
T98	2810	8	0	0
T114	1783	9	0	0
T136	51852	417	0	0
T137	24685	234	0	0
T138	26798	222	0	0
T139	5384	21	0	0
T140	7855	23	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1529	0	0
T86	3131	4	0	0
T89	2408	6	0	0
T96	11969	37	0	0
T98	2810	6	0	0
T114	1783	4	0	0
T136	51852	383	0	0
T137	24685	236	0	0
T138	26798	225	0	0
T139	5384	16	0	0
T140	7855	18	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1481	0	0
T86	3131	10	0	0
T89	2408	2	0	0
T96	11969	57	0	0
T98	2810	6	0	0
T114	1783	1	0	0
T136	51852	372	0	0
T137	24685	223	0	0
T138	26798	213	0	0
T139	5384	11	0	0
T140	7855	30	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1499	0	0
T86	3131	15	0	0
T89	2408	7	0	0
T96	11969	56	0	0
T98	2810	14	0	0
T114	1783	2	0	0
T136	51852	399	0	0
T137	24685	245	0	0
T138	26798	210	0	0
T139	5384	3	0	0
T140	7855	14	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1584	0	0
T86	3131	7	0	0
T89	2408	7	0	0
T96	11969	63	0	0
T98	2810	13	0	0
T114	1783	2	0	0
T136	51852	449	0	0
T137	24685	196	0	0
T138	26798	200	0	0
T140	7855	10	0	0
T143	10844	48	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1646	0	0
T86	3131	6	0	0
T89	2408	3	0	0
T96	11969	63	0	0
T98	2810	11	0	0
T114	1783	6	0	0
T136	51852	421	0	0
T137	24685	236	0	0
T138	26798	211	0	0
T139	5384	2	0	0
T140	7855	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1593	0	0
T89	2408	4	0	0
T96	11969	38	0	0
T98	2810	9	0	0
T136	51852	407	0	0
T137	24685	216	0	0
T138	26798	216	0	0
T140	7855	25	0	0
T143	10844	21	0	0
T144	24594	70	0	0
T145	11410	53	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1574	0	0
T86	3131	8	0	0
T89	2408	9	0	0
T96	11969	50	0	0
T114	1783	3	0	0
T136	51852	424	0	0
T137	24685	218	0	0
T138	26798	201	0	0
T139	5384	9	0	0
T140	7855	23	0	0
T143	10844	11	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580534699	1583	0	0
T86	3131	8	0	0
T89	2408	5	0	0
T96	11969	49	0	0
T98	2810	9	0	0
T114	1783	2	0	0
T136	51852	390	0	0
T137	24685	195	0	0
T138	26798	214	0	0
T139	5384	11	0	0
T140	7855	17	0	0