Unified Coverage Report :: Module

Module : kmac_staterd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00	100.00	70.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_staterd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_staterd	90.00	100.00	70.00			100.00

Module Instance : tb.dut.u_staterd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00	100.00	70.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.88	89.88	81.09			88.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_slicer[0].u_state_slice	100.00	100.00					100.00
u_tlul_adapter	89.67	89.39	81.51			87.78	100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_staterd

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
ALWAYS	87	4	4	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	101	3	3	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	123	1	1	100.00



86                        always_ff @(posedge clk_i or negedge rst_ni) begin
87         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
88         1/1                tlram_rdata <= '0;
           Tests:       T1 T2 T3 
89         1/1              end else if (tlram_req & ~tlram_we) begin
           Tests:       T1 T2 T3 
90         1/1                tlram_rdata <= conv_endian32(tlram_rdata_endian, endian_swap_i);
           Tests:       T1 T2 T3 
91                          end
                        MISSING_ELSE
92                        end
93                      
94                        // Always grant
95         1/1            assign tlram_gnt = tlram_req & ~tlram_we;
           Tests:       T1 T2 T3 
96                      
97                        // always no error on reading
98                        assign tlram_rerror = '0;
99                      
100                       always_ff @(posedge clk_i or negedge rst_ni) begin
101        2/2              if (!rst_ni) tlram_rvalid <= 1'b0;
           Tests:       T1 T2 T3  | T1 T2 T3 
102        1/1              else         tlram_rvalid <= tlram_req & !tlram_we;
           Tests:       T1 T2 T3 
103                       end
104                     
105                       logic [31:0] muxed_state [Share];
106                     
107                     
108                       for (genvar i = 0 ; i < Share ; i++) begin : gen_slicer
109                         prim_slicer #(
110                           .InW (sha3_pkg::StateW),
111                           .OutW (32),
112                           .IndexW (StateAddrW)
113                         ) u_state_slice (
114                           .sel_i (tlram_addr[StateAddrW-1:0]),
115                           .data_i (state_i[i]),
116                           .data_o (muxed_state[i])
117                         );
118                       end : gen_slicer
119                     
120                       logic [SelAddrW-1:0] addr_sel;
121        1/1            assign addr_sel = tlram_addr[StateAddrW+:SelAddrW];
           Tests:       T1 T2 T3 
122                     
123        1/1            assign tlram_rdata_endian = int'(addr_sel) < Share ? muxed_state[addr_sel] : 0;
           Tests:       T1 T2 T3

Cond Coverage for Module : kmac_staterd

	Total	Covered	Percent
Conditions	10	7	70.00
Logical	10	7	70.00
Non-Logical	0	0
Event	0	0

 LINE       89
 EXPRESSION (tlram_req & ((~tlram_we)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (tlram_req & ((~tlram_we)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       102
 EXPRESSION (tlram_req & ((!tlram_we)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION ((int'(addr_sel) < Share) ? muxed_state[addr_sel] : 0)
             ------------1-----------

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Module : kmac_staterd

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	123	1	1	100.00
IF	87	3	3	100.00
IF	101	2	2	100.00



123          assign tlram_rdata_endian = int'(addr_sel) < Share ? muxed_state[addr_sel] : 0;
                                                                -1-  
                                                                ==>  
                                                                ==> (Unreachable)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3



87             if (!rst_ni) begin
               -1-  
88               tlram_rdata <= '0;
                 ==>
89             end else if (tlram_req & ~tlram_we) begin
                        -2-  
90               tlram_rdata <= conv_endian32(tlram_rdata_endian, endian_swap_i);
                 ==>
91             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



101            if (!rst_ni) tlram_rvalid <= 1'b0;
               -1-  
               ==>
102            else         tlram_rvalid <= tlram_req & !tlram_we;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3