Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38383211	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

48500414

1

T1

542

T2

431

T3

737

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	46858626	1			T1	429		T2	303		T3	776
values[0x0]	19418487	1			T1	198		T2	127		T3	151
values[0x1]	20606512	1			T1	186		T2	153		T3	144

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29788966	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

57094659

1

T1

599

T2

467

T3

808

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	276551	1			T2	4		T13	26		T14	44
valid_sources[0x01]	274204	1			T2	5		T13	24		T14	61
valid_sources[0x02]	275376	1			T2	2		T3	27		T11	12
valid_sources[0x03]	368994	1			T1	12		T2	3		T3	7
valid_sources[0x04]	276924	1			T1	2		T2	5		T13	28
valid_sources[0x05]	271571	1			T1	5		T2	1		T13	16
valid_sources[0x06]	273404	1			T2	1		T11	7		T13	36
valid_sources[0x07]	411534	1			T1	3		T2	1		T3	13
valid_sources[0x08]	270307	1			T2	1		T13	44		T14	49
valid_sources[0x09]	274313	1			T2	1		T13	44		T14	31
valid_sources[0x0a]	357466	1			T2	1		T11	4		T13	47
valid_sources[0x0b]	271722	1			T2	6		T13	37		T14	33
valid_sources[0x0c]	271298	1			T2	1		T3	2		T11	13
valid_sources[0x0d]	276149	1			T1	4		T2	2		T13	24
valid_sources[0x0e]	340395	1			T1	15		T2	2		T3	16
valid_sources[0x0f]	1439943	1			T2	3		T3	16		T11	11
valid_sources[0x10]	276512	1			T13	25		T14	45		T16	77
valid_sources[0x11]	274117	1			T1	5		T2	1		T13	35
valid_sources[0x12]	277683	1			T1	4		T2	3		T3	11
valid_sources[0x13]	272619	1			T1	3		T2	4		T11	7
valid_sources[0x14]	273598	1			T1	11		T2	1		T13	54
valid_sources[0x15]	273158	1			T2	2		T3	6		T13	39
valid_sources[0x16]	273239	1			T2	4		T13	41		T14	33
valid_sources[0x17]	274833	1			T2	4		T13	29		T14	41
valid_sources[0x18]	272340	1			T1	21		T2	1		T11	2
valid_sources[0x19]	1206957	1			T2	2		T13	34		T14	38
valid_sources[0x1a]	1231746	1			T1	7		T2	5		T3	20
valid_sources[0x1b]	423812	1			T2	1		T3	3		T13	33
valid_sources[0x1c]	271831	1			T1	4		T2	4		T3	15
valid_sources[0x1d]	272263	1			T2	2		T11	15		T13	35
valid_sources[0x1e]	362927	1			T1	2		T13	39		T14	47
valid_sources[0x1f]	273421	1			T13	16		T14	66		T4	2
valid_sources[0x20]	275950	1			T1	3		T2	2		T11	17
valid_sources[0x21]	272589	1			T2	1		T11	23		T13	40
valid_sources[0x22]	377029	1			T2	1		T13	39		T14	30
valid_sources[0x23]	276116	1			T1	14		T2	1		T11	30
valid_sources[0x24]	273663	1			T2	3		T3	29		T13	40
valid_sources[0x25]	274777	1			T2	2		T13	32		T14	58
valid_sources[0x26]	277416	1			T2	1		T11	3		T13	47
valid_sources[0x27]	272296	1			T3	10		T11	21		T13	45
valid_sources[0x28]	275737	1			T2	2		T11	16		T13	34
valid_sources[0x29]	277051	1			T2	3		T3	2		T11	4
valid_sources[0x2a]	273200	1			T2	3		T13	30		T14	39
valid_sources[0x2b]	274426	1			T2	3		T3	3		T11	7
valid_sources[0x2c]	277361	1			T1	10		T13	25		T14	58
valid_sources[0x2d]	324112	1			T2	5		T11	6		T13	33
valid_sources[0x2e]	290130	1			T2	3		T13	31		T14	60
valid_sources[0x2f]	273456	1			T2	1		T3	4		T13	37
valid_sources[0x30]	334774	1			T1	2		T2	1		T11	4
valid_sources[0x31]	272327	1			T2	1		T11	10		T13	38
valid_sources[0x32]	272280	1			T13	35		T14	50		T4	2
valid_sources[0x33]	284629	1			T2	2		T13	40		T14	35
valid_sources[0x34]	272525	1			T2	3		T13	29		T14	47
valid_sources[0x35]	276849	1			T2	4		T3	9		T17	37
valid_sources[0x36]	274634	1			T1	13		T2	3		T3	7
valid_sources[0x37]	272930	1			T2	1		T3	1		T11	4
valid_sources[0x38]	274134	1			T1	5		T13	29		T14	20
valid_sources[0x39]	713910	1			T2	3		T3	1		T13	48
valid_sources[0x3a]	288065	1			T2	1		T11	6		T13	30
valid_sources[0x3b]	332319	1			T1	11		T2	2		T13	24
valid_sources[0x3c]	274996	1			T2	1		T3	5		T13	31
valid_sources[0x3d]	271421	1			T2	1		T3	11		T13	40
valid_sources[0x3e]	271674	1			T1	3		T2	3		T13	23
valid_sources[0x3f]	271350	1			T3	4		T11	6		T13	30
valid_sources[0x40]	272944	1			T2	1		T3	24		T11	2
valid_sources[0x41]	271441	1			T1	7		T2	2		T3	1
valid_sources[0x42]	276668	1			T3	7		T11	1		T13	31
valid_sources[0x43]	273884	1			T2	1		T11	1		T13	37
valid_sources[0x44]	1282997	1			T1	12		T2	3		T3	2
valid_sources[0x45]	500951	1			T2	1		T3	18		T11	3
valid_sources[0x46]	276780	1			T1	4		T2	2		T13	60
valid_sources[0x47]	313191	1			T2	1		T3	2		T11	1
valid_sources[0x48]	369379	1			T13	25		T14	74		T16	85
valid_sources[0x49]	275576	1			T1	13		T2	3		T3	22
valid_sources[0x4a]	271447	1			T2	2		T13	31		T14	39
valid_sources[0x4b]	412593	1			T13	31		T14	39		T4	1
valid_sources[0x4c]	274209	1			T11	6		T13	32		T14	66
valid_sources[0x4d]	276482	1			T2	3		T13	30		T14	37
valid_sources[0x4e]	320925	1			T1	6		T2	1		T11	6
valid_sources[0x4f]	768960	1			T1	2		T2	2		T3	9
valid_sources[0x50]	271890	1			T1	6		T2	1		T3	22
valid_sources[0x51]	276304	1			T1	20		T2	6		T11	5
valid_sources[0x52]	273948	1			T1	12		T2	1		T13	28
valid_sources[0x53]	1080728	1			T1	6		T2	3		T11	9
valid_sources[0x54]	270553	1			T2	4		T13	46		T14	44
valid_sources[0x55]	275173	1			T2	1		T11	9		T13	31
valid_sources[0x56]	272636	1			T1	1		T2	5		T3	6
valid_sources[0x57]	278098	1			T1	11		T2	2		T11	7
valid_sources[0x58]	350262	1			T2	2		T3	33		T13	24
valid_sources[0x59]	275583	1			T2	4		T13	19		T14	36
valid_sources[0x5a]	274649	1			T1	6		T2	1		T13	36
valid_sources[0x5b]	788541	1			T3	3		T11	11		T13	30
valid_sources[0x5c]	272258	1			T2	1		T13	31		T14	47
valid_sources[0x5d]	268520	1			T2	3		T13	36		T14	40
valid_sources[0x5e]	273956	1			T2	4		T13	49		T14	41
valid_sources[0x5f]	274919	1			T2	1		T11	3		T13	27
valid_sources[0x60]	379904	1			T2	1		T11	3		T13	17
valid_sources[0x61]	274542	1			T2	2		T3	1		T11	12
valid_sources[0x62]	273838	1			T1	7		T2	3		T3	6
valid_sources[0x63]	769461	1			T1	20		T2	2		T3	5
valid_sources[0x64]	433603	1			T2	3		T13	35		T14	56
valid_sources[0x65]	281706	1			T1	1		T3	15		T11	6
valid_sources[0x66]	273311	1			T2	5		T3	16		T11	3
valid_sources[0x67]	531627	1			T2	3		T3	3		T13	40
valid_sources[0x68]	275996	1			T2	3		T3	55		T13	35
valid_sources[0x69]	275258	1			T1	4		T13	26		T14	62
valid_sources[0x6a]	275609	1			T1	5		T2	6		T3	18
valid_sources[0x6b]	1098633	1			T1	4		T2	1		T13	38
valid_sources[0x6c]	1172304	1			T1	1		T2	4		T3	7
valid_sources[0x6d]	361531	1			T1	6		T2	2		T11	2
valid_sources[0x6e]	273357	1			T13	39		T14	53		T4	1
valid_sources[0x6f]	272212	1			T1	4		T3	17		T13	47
valid_sources[0x70]	272061	1			T2	3		T3	24		T11	2
valid_sources[0x71]	270800	1			T2	2		T13	32		T14	34
valid_sources[0x72]	276474	1			T1	10		T2	2		T11	2
valid_sources[0x73]	278513	1			T2	4		T3	24		T13	20
valid_sources[0x74]	274997	1			T2	4		T11	5		T13	18
valid_sources[0x75]	276012	1			T2	2		T3	7		T11	5
valid_sources[0x76]	275840	1			T2	2		T11	3		T13	28
valid_sources[0x77]	271944	1			T1	1		T2	3		T13	41
valid_sources[0x78]	272231	1			T1	7		T2	3		T3	1
valid_sources[0x79]	446655	1			T1	3		T2	3		T11	4
valid_sources[0x7a]	591297	1			T11	4		T13	50		T14	45
valid_sources[0x7b]	273254	1			T11	7		T13	29		T14	41
valid_sources[0x7c]	402105	1			T1	5		T2	5		T3	4
valid_sources[0x7d]	271808	1			T1	5		T2	3		T11	6
valid_sources[0x7e]	338490	1			T2	2		T11	1		T13	35
valid_sources[0x7f]	466558	1			T1	1		T2	3		T3	21
valid_sources[0x80]	338650	1			T2	3		T3	8		T13	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23165529

1

T1

256

T2

215

T3

552

values[0x0]

all_enables

biggest_size

13285686

1

T1

159

T2

99

T3

100

values[0x1]

all_enables

biggest_size

12049199

1

T1

127

T2

117

T3

85