Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38450220

1

T1

271

T2

152

T3

334

full_word

48504593

1

T1

542

T2

431

T3

737

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	86954523	1			T1	813		T2	583		T3	1071
auto[TlIntgErrCmd]	93	1			T108	6		T109	6		T110	7
auto[TlIntgErrData]	101	1			T108	10		T109	8		T110	7
auto[TlIntgErrBoth]	96	1			T108	4		T109	6		T110	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46874065

1

T1

429

T2

303

T3

776

auto[1]

40080748

1

T1

384

T2

280

T3

295

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23707257	1			T1	173		T2	88		T3	224
auto[TlIntgErrNone]	partial	auto[1]	14742694	1			T1	98		T2	64		T3	110
auto[TlIntgErrNone]	full_word	auto[0]	23166673	1			T1	256		T2	215		T3	552
auto[TlIntgErrNone]	full_word	auto[1]	25337899	1			T1	286		T2	216		T3	185
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T109	4		T110	4		T130	3
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T108	5		T109	1		T110	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T108	1		T110	1		T130	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T109	1		T144	1		T166	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T108	6		T109	2		T110	5
auto[TlIntgErrData]	partial	auto[1]	41	1			T108	2		T109	6		T110	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T110	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T108	2		T166	2		T167	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T108	2		T109	3		T110	4
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T109	3		T110	2		T130	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T108	1		T168	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T108	1		T169	1		T170	1