Line Coverage for Instance : tb.dut.u_reg.u_err_code.wr_en_data_arb
|  | Line No. | Total | Covered | Percent | 
|---|
| TOTAL |  | 2 | 2 | 100.00 | 
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 | 
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 | 
| CONT_ASSIGN | 51 | 0 | 0 |  | 
| CONT_ASSIGN | 52 | 0 | 0 |  | 
| CONT_ASSIGN | 53 | 0 | 0 |  | 
42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;